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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=baturo.alexey@gmail.com; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694197732640100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 1 + target/riscv/cpu_helper.c | 1 + target/riscv/csr.c | 4 ++++ target/riscv/machine.c | 1 + target/riscv/pmp.c | 1 + 5 files changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index af8f16b94f..928d4b5f5c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -891,6 +891,7 @@ static void riscv_cpu_reset_hold(Object *obj) } #endif env->xl =3D riscv_cpu_mxl(env); + riscv_cpu_update_mask(env); cs->exception_index =3D RISCV_EXCP_NONE; env->load_res =3D -1; set_default_nan_mode(1, &env->fp_status); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 6e68b2fc27..6cc1df4fcb 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -689,6 +689,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulon= g newpriv) /* tlb_flush is unnecessary as mode is contained in mmu_idx */ env->priv =3D newpriv; env->xl =3D cpu_recompute_xl(env); + riscv_cpu_update_mask(env); =20 /* * Clear the load reservation - otherwise a reservation placed in one diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c7e59168d2..7fe0d83877 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1321,6 +1321,7 @@ static RISCVException write_mstatus(CPURISCVState *en= v, int csrno, env->xl =3D cpu_recompute_xl(env); } =20 + riscv_cpu_update_mask(env); return RISCV_EXCP_NONE; } =20 @@ -1948,6 +1949,7 @@ static RISCVException write_menvcfg(CPURISCVState *en= v, int csrno, } env->menvcfg =3D (env->menvcfg & ~mask) | (val & mask); =20 + riscv_cpu_update_mask(env); return RISCV_EXCP_NONE; } =20 @@ -2002,6 +2004,8 @@ static RISCVException write_senvcfg(CPURISCVState *en= v, int csrno, mask |=3D SENVCFG_UPMEN; } env->senvcfg =3D (env->senvcfg & ~mask) | (val & mask); + + riscv_cpu_update_mask(env); return RISCV_EXCP_NONE; } =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index d50ff5421f..e63a9fc95f 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -258,6 +258,7 @@ static int riscv_cpu_post_load(void *opaque, int versio= n_id) CPURISCVState *env =3D &cpu->env; =20 env->xl =3D cpu_recompute_xl(env); + riscv_cpu_update_mask(env); return 0; } =20 diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 0db49173ef..5ca536bac0 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -586,6 +586,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong= val) } =20 env->mseccfg =3D val; + riscv_cpu_update_mask(env); } =20 /* --=20 2.34.1