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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q1-20020a170902dac100b001c3267ae31bsm715231plx.301.2023.09.07.23.08.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Sep 2023 23:08:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694153336; x=1694758136; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4999Ax6xk9vLcdpOVew5ohG5mMllXkx8uzAH+l1br7Q=; b=pKrr5fnsFjBTP+ijXlN1J5V5LyIJNemw1AqDuxwPuo/llk7wepKKrlAGHRs5eKaTN7 7ToloRjiOueCqMzvHGIeKQ6rDgHvuaU8YVi43csUhqOBkuzv7usoXZZ8I1i7tmL7F1y5 s4NCnccz+tB29TvtYxgQ0vj4+5da1lkTRwSU4+aTIQ1d9r2uDK1ZHBPScgjmIoJl4x03 E+WxA9RdcFakPrsbnVKglvLN+qYcXxogYdKHQBEnVvrCQE62BQ7Gn2k60feoi9r/OQ69 awj9KZPTx6gaIJYPDFbh6b96TkjGHkSp90Nq3vRDdtYCe6kE/Cp3EmnU85egI01Tw9Ss y7MA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694153336; x=1694758136; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4999Ax6xk9vLcdpOVew5ohG5mMllXkx8uzAH+l1br7Q=; b=NKGbGSoAddPBD4QcIL6iW4oIRCxT6JgiFkvE/EDekwwXI13m7ZWNWBzd3epTSDmEue ZQ7Dgb4rITcqacgXlBdtd2MRpjxNkPNRDkYbGGbBszD0TR8KXk+egyUGFetxZIyDWwcA JYhcyWu+SO1PJbVlAlXyZpo4fkhpIR+TnP4D9xnydRBVgQzgzkY77VOEYz38tuaWIQn4 LJ0P66FUj50dWsEYMsaLr39yKgLUWfbKT7+8Gfr1eaI1BMb9tuIDDbT5mHAw3eVSIzyZ a0dQBpWPYGiPVE+n9O7w/wggiHVqpm3dQekscR4WIZIX/1eTmSL5MDiTkaqBPEQysljE 8cHw== X-Gm-Message-State: AOJu0YzwY2RwOV+X4HNkyNkAcJAq6HTZKFDsJXbyzxDPDksbphsEkZKR fzXA1IcJIHpAlMiI25x7NPPqf9ErzgtzGFIY X-Google-Smtp-Source: AGHT+IEKletcIOICqqrrS9vkL+VA/Ei4at2+iN2i+z+MRfyefKUwxglVkbExMZ0Ogy7yjR90+CdG2w== X-Received: by 2002:a17:902:ea0a:b0:1bb:b30e:4364 with SMTP id s10-20020a170902ea0a00b001bbb30e4364mr2054692plg.39.1694153335908; Thu, 07 Sep 2023 23:08:55 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis , Andrew Jones Subject: [PULL 64/65] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update() Date: Fri, 8 Sep 2023 16:04:30 +1000 Message-ID: <20230908060431.1903919-65-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230908060431.1903919-1-alistair.francis@wdc.com> References: <20230908060431.1903919-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=alistair23@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694153657195100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Add a new cpu_cfg_ext_is_user_set() helper to check if an extension was set by the user in the command line. Use it inside cpu_cfg_ext_auto_update() to verify if the user set a certain extension and, if that's the case, do not change its value. This will make us honor user choice instead of overwriting the values. Users will then be informed whether they're using an incompatible set of extensions instead of QEMU setting a magic value that works. The reason why we're not implementing user choice for MISA extensions right now is because, today, we do not silently change any MISA bit during realize() time (we do warn when enabling bits if RVG is enabled). We do that - a lot - with multi-letter extensions though, so we're handling the most immediate concern first. After this patch, we'll now error out if the user explicitly set 'zce' to t= rue and 'zca' to false: $ ./build/qemu-system-riscv64 -M virt -cpu rv64,zce=3Dtrue,zca=3Dfalse -nog= raphic qemu-system-riscv64: Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca extension This didn't happen before because we were enabling 'zca' if 'zce' was enabl= ed regardless if the user set 'zca' to false. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones Message-ID: <20230901194627.1214811-20-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 617b861258..78382cb5f2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -195,6 +195,12 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_of= fset) g_assert_not_reached(); } =20 +static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) +{ + return g_hash_table_contains(multi_ext_user_opts, + GUINT_TO_POINTER(ext_offset)); +} + static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, bool value) { @@ -206,6 +212,10 @@ static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uin= t32_t ext_offset, return; } =20 + if (cpu_cfg_ext_is_user_set(ext_offset)) { + return; + } + if (value && env->priv_ver !=3D PRIV_VERSION_LATEST) { /* Do not enable it if priv_ver is older than min_version */ min_version =3D cpu_cfg_ext_get_min_version(ext_offset); @@ -1847,6 +1857,12 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { MISA_CFG(RVG, false), }; =20 +/* + * We do not support user choice tracking for MISA + * extensions yet because, so far, we do not silently + * change MISA bits during realize() (RVG enables MISA + * bits but the user is warned about it). + */ static void riscv_cpu_add_misa_properties(Object *cpu_obj) { int i; --=20 2.41.0