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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q1-20020a170902dac100b001c3267ae31bsm715231plx.301.2023.09.07.23.08.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Sep 2023 23:08:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694153325; x=1694758125; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X3TXakHoXRsT7MrbHl8Tk03e7NcDoueB5M4ZFXLQkgo=; b=K8+VKR2L8Su4Df1tYZoKuogiu+C2NgvOT2U+XhtiYRu8gL2ok1GhHGIyGfgVQ9vMLM UPhwZCl9rtI5/AgauBeID1TWopcXw1DapofoxZztrunM6Abtg4T+HKTkzoydM3apfLC2 U4JBgPUw4gtXr8gftEkb3ZlOm1afVL7gVMgZA4hnFqf5Zvk5g5H7y9nSsIk37wBMjQ9O AMXhb6H53G+OWkWkk1HUuHSIAelI2w5TG251/xyOCrYuVg4HCjup3VQOUPBYhF3XcxkH B+pVRPgfTlH0Y29l4ctjaFBA6eybsdbsLZcdQEGq5Zc5CbCtzLN7L2GtbUu85WbsZwhL VSeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694153325; x=1694758125; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X3TXakHoXRsT7MrbHl8Tk03e7NcDoueB5M4ZFXLQkgo=; b=ZJhCDZlUlNKpSZTwVr9La0G0ALBMr1S01tC5OskHGKi6eA5eF0TsrO+edGeAiiirCB g/n8DkRT1dFZFLSUuPfZ8gDvWcJ7MgtU7+FrA5O+/pAU1Y6zDE0MWje+Dy2fXhgmh4jQ 6i6RzQhew7K162fDSxkmK9EMhrZUJYE9vLqMuGQN0sSqxeyjWepo84Oyz7twsSoJSV81 EidqousrM/Hi5EbgQ67XOb5qMLHEzep9pN6pPe2H97FbhDtf7XazKWCxo+Nx9hHt5RnQ 1pnyzUDOs1Kz92ps5B0X0GWPsXiq4V1NfZxDmqpn8CABeIRm4AvBYRtX2tDfXCxGME79 g+AQ== X-Gm-Message-State: AOJu0YzDgPA83SRP8QFFv3U7/5T44IMRbcR0IqlODu+r7kNUQ+euD21P K87tUWhUNSnEnHrL4Ql4/yHejYsqJBG4Fojc X-Google-Smtp-Source: AGHT+IFI9bHWP6bMhCREv0J0+N4SZ+hcXkTJAFTXlAu3YWaLDtfpEHoGfphGofKZcU3EI1WZOfqFig== X-Received: by 2002:a17:902:c252:b0:1c3:6724:db6f with SMTP id 18-20020a170902c25200b001c36724db6fmr1616930plg.29.1694153325372; Thu, 07 Sep 2023 23:08:45 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis , Andrew Jones Subject: [PULL 61/65] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize() Date: Fri, 8 Sep 2023 16:04:27 +1000 Message-ID: <20230908060431.1903919-62-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230908060431.1903919-1-alistair.francis@wdc.com> References: <20230908060431.1903919-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694153429818100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Let's change the other instances in realize() where we're enabling an extension based on a certain criteria (e.g. it's a dependency of another extension). We're leaving icsr and ifencei being enabled during RVG for later - we'll want to error out in that case. Every other extension enablement during realize is now done via cpu_cfg_ext_auto_update(). The end goal is that only cpu init() functions will handle extension flags directly via "cpu->cfg.ext_N =3D true|false". Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones Message-ID: <20230901194627.1214811-17-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 50 +++++++++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a4876df5f4..eeaf69599e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1193,7 +1193,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) } =20 if (cpu->cfg.ext_zfh) { - cpu->cfg.ext_zfhmin =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true); } =20 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { @@ -1219,17 +1219,17 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cp= u, Error **errp) } =20 /* The V vector extension depends on the Zve64d extension */ - cpu->cfg.ext_zve64d =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true); } =20 /* The Zve64d extension depends on the Zve64f extension */ if (cpu->cfg.ext_zve64d) { - cpu->cfg.ext_zve64f =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true); } =20 /* The Zve64f extension depends on the Zve32f extension */ if (cpu->cfg.ext_zve64f) { - cpu->cfg.ext_zve32f =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true); } =20 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { @@ -1243,7 +1243,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) } =20 if (cpu->cfg.ext_zvfh) { - cpu->cfg.ext_zvfhmin =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true); } =20 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { @@ -1273,7 +1273,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) =20 /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_zhinx) { - cpu->cfg.ext_zhinxmin =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); } =20 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfi= nx) { @@ -1294,12 +1294,12 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cp= u, Error **errp) } =20 if (cpu->cfg.ext_zce) { - cpu->cfg.ext_zca =3D true; - cpu->cfg.ext_zcb =3D true; - cpu->cfg.ext_zcmp =3D true; - cpu->cfg.ext_zcmt =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { - cpu->cfg.ext_zcf =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } } =20 @@ -1367,26 +1367,26 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cp= u, Error **errp) } =20 if (cpu->cfg.ext_zk) { - cpu->cfg.ext_zkn =3D true; - cpu->cfg.ext_zkr =3D true; - cpu->cfg.ext_zkt =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true); } =20 if (cpu->cfg.ext_zkn) { - cpu->cfg.ext_zbkb =3D true; - cpu->cfg.ext_zbkc =3D true; - cpu->cfg.ext_zbkx =3D true; - cpu->cfg.ext_zkne =3D true; - cpu->cfg.ext_zknd =3D true; - cpu->cfg.ext_zknh =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true); } =20 if (cpu->cfg.ext_zks) { - cpu->cfg.ext_zbkb =3D true; - cpu->cfg.ext_zbkc =3D true; - cpu->cfg.ext_zbkx =3D true; - cpu->cfg.ext_zksed =3D true; - cpu->cfg.ext_zksh =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true); } =20 /* --=20 2.41.0