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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q1-20020a170902dac100b001c3267ae31bsm715231plx.301.2023.09.07.23.08.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Sep 2023 23:08:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694153322; x=1694758122; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FjeTfhuxehQRer2U4WGeHFMo635Td6Rnb8XNvF6bkS0=; b=eF60RYgnvr4JQ/Sn9ZDDe3fJ66QAwdXVC9gZTUiUNMhP0Y2OvyDvq1wmlmubikTBsN ecTpyuRLONXjW3Gb82A82CmTG4abgsm6t+oZngLOnjdwE2QAcw6/mcaYAdU/whdxTzp7 LP8PzlJIeneG/5As1iIGYJBueEZ/nRLlKO4KnEWCWYLPgp4PJcFQJbNhprrBdlJUCRKu dnQ4Bz11hgT2qy3Xjpe9RHa/bjs1FAvoCVRA16e57mm3Vf/3srgVJReSsxzslpQeRIzF aKm6UNPIYZyrOVif86ml/RtghmnvmAVPC2VvlQPVN9qvZxR8m7QBEeD41dIswucb2xTH /asg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694153322; x=1694758122; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FjeTfhuxehQRer2U4WGeHFMo635Td6Rnb8XNvF6bkS0=; b=evBKh8fXsoTy6qs4yfCAxBtoX6WVDFoWPopcBoPCI3apDPy01WzuZ4qzIdH/N+QP0/ Z8dZNFm1C0ud7wrQaQzFQbZl/d2hIS6nhSChUZe8QBXerNRaYE6GB1CliPZ+uFMp7H8F 5Shass8kdu1LYdjRf5WTlpjtVTYmL61dAQgUe+b9k2SR6wYNxAjjqVyPzly7AiHKR5Hi x+7UB5JjTc3Gl3DNR2lJ6imEVhasc8fzytPrqmFLe3fYLj4UddWhkEFOrESRtxXAJgGa zkqFCe67vIAzkd+SXQt1l5+nwtFsG59N0rjbFtHrLZwpDUNzqT2yQY1Cx+i3xNpmHmRr /KqQ== X-Gm-Message-State: AOJu0YyXVL6IuJXrWv6iFYuvXnFND0dR2HOKtGGzO9rIo4vRZciloKmS qgZO2C4fDM5ZyBP1B60G5v3WuFs4I7uT6idG X-Google-Smtp-Source: AGHT+IGCApZUxAjPCoL5aLipk8bzCIRGdCQRrkNgfduDLleikTvhsZkfooKWZ0nCyVkwKGEz5V4ZJw== X-Received: by 2002:a17:902:9b8f:b0:1b0:3637:384e with SMTP id y15-20020a1709029b8f00b001b03637384emr1497956plp.25.1694153322023; Thu, 07 Sep 2023 23:08:42 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis , Andrew Jones Subject: [PULL 60/65] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update() Date: Fri, 8 Sep 2023 16:04:26 +1000 Message-ID: <20230908060431.1903919-61-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230908060431.1903919-1-alistair.francis@wdc.com> References: <20230908060431.1903919-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=alistair23@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694153483114100005 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza During realize() time we're activating a lot of extensions based on some criteria, e.g.: if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn =3D true; cpu->cfg.ext_zkr =3D true; cpu->cfg.ext_zkt =3D true; } This practice resulted in at least one case where we ended up enabling something we shouldn't: RVC enabling zca/zcd/zcf when using a CPU that has priv_spec older than 1.12.0. We're also not considering user choice. There's no way of doing it now but this is about to change in the next few patches. cpu_cfg_ext_auto_update() will check for priv version mismatches before enabling extensions. If we have a mismatch between the current priv version and the extension we want to enable, do not enable it. In the near future, this same function will also consider user choice when deciding if we're going to enable/disable an extension or not. For now let's use it to handle zca/zcd/zcf enablement if RVC is enabled. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones Message-ID: <20230901194627.1214811-16-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 43 ++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 40 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 43c68e1792..a4876df5f4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -177,6 +177,43 @@ static void isa_ext_update_enabled(RISCVCPU *cpu, uint= 32_t ext_offset, *ext_enabled =3D en; } =20 +static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { + if (isa_edata_arr[i].ext_enable_offset !=3D ext_offset) { + continue; + } + + return isa_edata_arr[i].min_version; + } + + g_assert_not_reached(); +} + +static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, + bool value) +{ + CPURISCVState *env =3D &cpu->env; + bool prev_val =3D isa_ext_is_enabled(cpu, ext_offset); + int min_version; + + if (prev_val =3D=3D value) { + return; + } + + if (value && env->priv_ver !=3D PRIV_VERSION_LATEST) { + /* Do not enable it if priv_ver is older than min_version */ + min_version =3D cpu_cfg_ext_get_min_version(ext_offset); + if (env->priv_ver < min_version) { + return; + } + } + + isa_ext_update_enabled(cpu, ext_offset, value); +} + const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -1268,12 +1305,12 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cp= u, Error **errp) =20 /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ if (riscv_has_ext(env, RVC) && env->priv_ver >=3D PRIV_VERSION_1_12_0)= { - cpu->cfg.ext_zca =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { - cpu->cfg.ext_zcf =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } if (riscv_has_ext(env, RVD)) { - cpu->cfg.ext_zcd =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); } } =20 --=20 2.41.0