From nobody Thu Nov 28 09:49:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694153494; cv=none; d=zohomail.com; s=zohoarc; b=LUc99RZZfYURkl1WB8NMdmSzbrCNAFFi5AyMm+V57K5k24rCxHu7qTvJ+QSOAY5Uo+6nbxGiLdUm0jHxoqM01q2Zm/8QqXLDccn11vE7ay9kg6chgo8U0ZeHcDQTlyNHnTxsoAqdct+ZOW08xlmWfnvlcMfbtjOHoV0PZBdw9sg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694153494; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bABsxxQ7+tNcrX3qthQfqpT8IQqITVxbBzeGNSCTapU=; b=Az8l64+G1q36vSy26qQVxSbvbAv9BRAXI9RhWBvBx8gwIpAsv6yYKBo7D3NDWFMWLeEGNU5d4rBuPJFVYe1BLrCKR19ZanV4XaSCRevPD4Wn9MA2kWUi+7f2pbjUkmv3HI6A6QxJVSBXNNxpOs9z7hUY9OUiZFQin06mTYe3HsA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694153494794161.3370431075715; Thu, 7 Sep 2023 23:11:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qeUer-0001OJ-8K; Fri, 08 Sep 2023 02:07:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qeUep-0001Fm-6H for qemu-devel@nongnu.org; Fri, 08 Sep 2023 02:07:55 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qeUem-00087Z-MX for qemu-devel@nongnu.org; Fri, 08 Sep 2023 02:07:54 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1c1ff5b741cso15462145ad.2 for ; Thu, 07 Sep 2023 23:07:52 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q1-20020a170902dac100b001c3267ae31bsm715231plx.301.2023.09.07.23.07.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Sep 2023 23:07:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694153271; x=1694758071; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bABsxxQ7+tNcrX3qthQfqpT8IQqITVxbBzeGNSCTapU=; b=axjimo7DPY/qnFlsOrGtn6KA+Ai40PVnoWswh1dc+eLPmtjlT08ohj/I8pVyRsGfEk 1Pox3gmztosE4WtVRpADTEpNN1ZExYTRwi0uYYxOZxggbY+PtJD+PHmX8atEJLGpWdfS Sn9B7DL/RiiMGou3zoZvKJ9r36/h2GnaRC8PNqNREQhneoxVQWtgV//eOUWEB6bwATmZ n9FGyG1HwoKCU4Glf4aDioduBcr2dpxcNDdX+UVVXHy/pUKJqD3nFZv+knvZ6WpT4gwA N4CA459wG/YTm6x/AnrbPONipqH3+qgS5kVXLurLTFKTvNHyFsrhvpvM2GJWC7JGd5EI /iVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694153271; x=1694758071; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bABsxxQ7+tNcrX3qthQfqpT8IQqITVxbBzeGNSCTapU=; b=lcQJfBFSo+7w8GuyKmWMMwHV24+LooTR+hhOHWAtxpbqiSFHRG0n1KYfWCQYjWCibB KmA+jJYL7KXGg2lVlNuR3jciNWw0qSUHZLByp+o1ETAVuP5I3YqkKX4QcE++kmxhNmTV MAlDQdCn1orMWKRaPXLKLFXJOfoAQp4wxrTW/oVwuAREVApzZAJOYix0bXGryfai/tyu dWDTydoodXuVuQxGxNE5tz7zh4FxseeU9+6zuRsZKD2RKtauWd4w/OsK2BtBZNXBfAFN BdKnx0t4f/MuK4RpMXPaGwXvWtC4Vlozf5iDlbhKwJf7gmu2dLffeMVzpshziA5PpvrZ 2sWw== X-Gm-Message-State: AOJu0Yxk2xY03zSBpaDwiGPjfqRCTo0UGbiKi2ozKrXQqtZS6RPwJ91n DBymlX+GogPbDT2wXkqZ7dCTJv7/VijIIVQZ X-Google-Smtp-Source: AGHT+IGgCtGDccdTwMGxaluUHqwdIuq/t9bXaJsTVqcPB2qKa2gM+L7OlyTg4i2xfkMvcN4LuFUcIQ== X-Received: by 2002:a17:902:e74b:b0:1b9:ea60:cd82 with SMTP id p11-20020a170902e74b00b001b9ea60cd82mr1782952plf.5.1694153270954; Thu, 07 Sep 2023 23:07:50 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis , Andrew Jones Subject: [PULL 46/65] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] Date: Fri, 8 Sep 2023 16:04:12 +1000 Message-ID: <20230908060431.1903919-47-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230908060431.1903919-1-alistair.francis@wdc.com> References: <20230908060431.1903919-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=alistair23@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694153495400100005 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza We'll add a new CPU type that will enable a considerable amount of extensions. To make it easier for us we'll do a few cleanups in our existing riscv_cpu_extensions[] array. Start by splitting all CPU non-boolean options from it. Create a new riscv_cpu_options[] array for them. Add all these properties in riscv_cpu_add_user_properties() as it is already being done today. 'mmu' and 'pmp' aren't really extensions in the usual way we think about RISC-V extensions. These are closer to CPU features/options, so move both to riscv_cpu_options[] too. In the near future we'll need to match all extensions with all entries in isa_edata_arr[], and so it happens that both 'mmu' and 'pmp' do not have a riscv,isa string (thus, no priv spec version restriction). This further emphasizes the point that these are more a CPU option than an extension. No functional changes made. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones Message-ID: <20230901194627.1214811-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f227c7664e..fdbd8eb0b8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1810,7 +1810,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) =20 static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ - DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), @@ -1823,15 +1822,8 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), - DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), - DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), =20 - DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), - DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), - DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), - DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), - DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false), DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), @@ -1862,9 +1854,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), =20 DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true), - DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), - DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), =20 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), =20 @@ -1918,6 +1908,21 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static Property riscv_cpu_options[] =3D { + DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), + + DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), + DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + + DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), + DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), + + DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), + DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), + + DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), + DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), +}; =20 #ifndef CONFIG_USER_ONLY static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, @@ -1986,6 +1991,14 @@ static void riscv_cpu_add_user_properties(Object *ob= j) #endif qdev_property_add_static(dev, prop); } + + for (int i =3D 0; i < ARRAY_SIZE(riscv_cpu_options); i++) { + /* Check if KVM created the property already */ + if (object_property_find(obj, riscv_cpu_options[i].name)) { + continue; + } + qdev_property_add_static(dev, &riscv_cpu_options[i]); + } } =20 static Property riscv_cpu_properties[] =3D { --=20 2.41.0