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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q1-20020a170902dac100b001c3267ae31bsm715231plx.301.2023.09.07.23.07.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Sep 2023 23:07:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694153257; x=1694758057; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9BtKiY4lAmSAzTij8lSOcl0A+RCHDkyDwuH2ARMSmck=; b=bRSXjN5KHIptPtcEarMuQhMarGF2qwUbjrIBzBrtP6R//iHbIrLDXs9a8ZZ0Ue085O cxv3Q6uCa1i+c3LC+5rzIR1+sFjMgH3BXd7DATocaG+5Vu3aYno5vr/GvlR0VNbpgs8U KUE/FGdpcvEinbIwGFz9iqwXveBWHxvlGvEhJ/olMm+LsLDy439KJNXPnMLha+ir8Goi mvCV+HR2+iukt5lks/cCA92VkD29ikEUMh7Ee2Ej9WlEYg2+SGwysK4vZE9J+0190gfc rn0ZBBKh8Q+o3ZMux/odpaxq4IppDVVVrUS8phhvW/RJ5DCklv97R5xba4IB22iBLeOy nr+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694153257; x=1694758057; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9BtKiY4lAmSAzTij8lSOcl0A+RCHDkyDwuH2ARMSmck=; b=DjTqVgiKiaLoTfcRYm2jmkpaeV3wBk9soAMUjVkbqc3wIzO91DS/Vn9nSqKh5O+M3g G1Nppz8hgf5Zewm8Gm1Er1SwbD6IxHX1i9jbMLMtOaJX9o9X0btCv0CZMkumf4ja48nJ WH7NgTFo7Z/IrJv6I7RtCr4XLHrbCKHv9CPG/lf/7dyQ9SebHXCMWKMk25nNQXnN00Sw xECnCT/hmiiy5IQGzpqyWComohygMtKzMgcYGWvgyUyXKUprCXYd0toNGz+RoP9djEO4 WyToi8fHkUD8HCtNgNgIfOZ3PtdZvNH4cvbv+KXgo6x+GJsQXCmjFppvgIgYpWYsF0LA QvHg== X-Gm-Message-State: AOJu0Yzozfi3EcVdq5LfGJ1AbCCXYFqr1aIxT38O7wc2o/czQ2iQc0WJ gNdCpGbhY6kHq/6Pw21NXZQVzPEcokMc4qxj X-Google-Smtp-Source: AGHT+IEtGzk3ZXoYBuFnVsCODJr5pbDWTseufTMVZosJwV2G0QWeUi0vA1Evs2kqndh+b+29oyiTBg== X-Received: by 2002:a17:902:74c8:b0:1c3:2ee6:3811 with SMTP id f8-20020a17090274c800b001c32ee63811mr1873587plt.8.1694153257034; Thu, 07 Sep 2023 23:07:37 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Akihiko Odaki , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , LIU Zhiwei , Alistair Francis Subject: [PULL 42/65] target/riscv: Allocate itrigger timers only once Date: Fri, 8 Sep 2023 16:04:08 +1000 Message-ID: <20230908060431.1903919-43-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230908060431.1903919-1-alistair.francis@wdc.com> References: <20230908060431.1903919-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=alistair23@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694153575065100001 From: Akihiko Odaki riscv_trigger_init() had been called on reset events that can happen several times for a CPU and it allocated timers for itrigger. If old timers were present, they were simply overwritten by the new timers, resulting in a memory leak. Divide riscv_trigger_init() into two functions, namely riscv_trigger_realize() and riscv_trigger_reset() and call them in appropriate timing. The timer allocation will happen only once for a CPU in riscv_trigger_realize(). Fixes: 5a4ae64cac ("target/riscv: Add itrigger support when icount is enabl= ed") Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-ID: <20230818034059.9146-1-akihiko.odaki@daynix.com> Signed-off-by: Alistair Francis --- target/riscv/debug.h | 3 ++- target/riscv/cpu.c | 8 +++++++- target/riscv/debug.c | 15 ++++++++++++--- 3 files changed, 21 insertions(+), 5 deletions(-) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index c471748d5a..5794aa6ee5 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -143,7 +143,8 @@ void riscv_cpu_debug_excp_handler(CPUState *cs); bool riscv_cpu_debug_check_breakpoint(CPUState *cs); bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); =20 -void riscv_trigger_init(CPURISCVState *env); +void riscv_trigger_realize(CPURISCVState *env); +void riscv_trigger_reset_hold(CPURISCVState *env); =20 bool riscv_itrigger_enabled(CPURISCVState *env); void riscv_itrigger_update_priv(CPURISCVState *env); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bf0912014e..f227c7664e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -926,7 +926,7 @@ static void riscv_cpu_reset_hold(Object *obj) =20 #ifndef CONFIG_USER_ONLY if (cpu->cfg.debug) { - riscv_trigger_init(env); + riscv_trigger_reset_hold(env); } =20 if (kvm_enabled()) { @@ -1525,6 +1525,12 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) =20 riscv_cpu_register_gdb_regs_for_features(cs); =20 +#ifndef CONFIG_USER_ONLY + if (cpu->cfg.debug) { + riscv_trigger_realize(&cpu->env); + } +#endif + qemu_init_vcpu(cs); cpu_reset(cs); =20 diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 75ee1c4971..ddd46b2d3e 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -903,7 +903,17 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CP= UWatchpoint *wp) return false; } =20 -void riscv_trigger_init(CPURISCVState *env) +void riscv_trigger_realize(CPURISCVState *env) +{ + int i; + + for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { + env->itrigger_timer[i] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + riscv_itrigger_timer_cb, env= ); + } +} + +void riscv_trigger_reset_hold(CPURISCVState *env) { target_ulong tdata1 =3D build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0); int i; @@ -928,7 +938,6 @@ void riscv_trigger_init(CPURISCVState *env) env->tdata3[i] =3D 0; env->cpu_breakpoint[i] =3D NULL; env->cpu_watchpoint[i] =3D NULL; - env->itrigger_timer[i] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, - riscv_itrigger_timer_cb, env= ); + timer_del(env->itrigger_timer[i]); } } --=20 2.41.0