From nobody Thu Nov 28 10:35:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694153399; cv=none; d=zohomail.com; s=zohoarc; b=lt2raXCirKjqFo07VHzdOr2UBvhqJIsKyJCLliEDhve7nsLVvI55zrGH/8c9ef8/7Ai/vqSDfwR0A5ZuOpgAHqEmj/GnJqnytkWD/XPX5AIrWnh+d4AVDJBYiuHmZpJ7NR3c/1L/ROY1O8/fegrIKG8AnFB1Gr5cb7lMyEtveUU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694153399; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LC1iRCb/qoM78YnEP3ofg9nP8nM+h7xg35CBjBCHbHg=; b=G6GN+Iy4m3KrmvG/G9x2/KVvxbMNqDLni72BsHz5Mtiy5dcaLvFisoIN8prLXc+C7c+CiYkr2RG6ieOWG3igkTHXe4lNDrYvMvszRFi1hgUBERp47ohbuPoCe1Oyv996E4fqQi9A5EO14WEXeIJAcqFnzJmEQDozK+PlsTSTbZo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694153399869103.47545899238503; Thu, 7 Sep 2023 23:09:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qeUe1-0004Ui-C1; Fri, 08 Sep 2023 02:07:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qeUdz-0004Iw-53 for qemu-devel@nongnu.org; Fri, 08 Sep 2023 02:07:03 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qeUdw-0006Xh-7a for qemu-devel@nongnu.org; Fri, 08 Sep 2023 02:07:02 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1bc8a2f71eeso14848215ad.0 for ; Thu, 07 Sep 2023 23:06:59 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q1-20020a170902dac100b001c3267ae31bsm715231plx.301.2023.09.07.23.06.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Sep 2023 23:06:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694153218; x=1694758018; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LC1iRCb/qoM78YnEP3ofg9nP8nM+h7xg35CBjBCHbHg=; b=hS3htWtoJHn4JI6pA8MRcpm0YC/SnO9R8wHKqzQRlCCPSDYptUObHtT6cT2yTZfuLm /rCDhWHV0pJcEseRuv1fffHfINzmSYtwO80f9M0G1iPml3fYE8LDM2ZwJUYKynVpgzit eczTCr6crKNsyQ6tGQoQak/VbSHaNAiR2gUGTHmU8izpCROUAVLp/K8w/f9bRr8kVTOh 5okfND9bh/gEU/awEHy7NxjTRX57DFbFwGyHmOawL+BF1Nig274Sap5iRCwF3Hio3KEj gsjuOOw9blhrw2jS00C8Tt0z8dOxf++20jFSTBsUvVpxtzgpC9tE6yPpnWOxyQz66lTI MOuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694153218; x=1694758018; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LC1iRCb/qoM78YnEP3ofg9nP8nM+h7xg35CBjBCHbHg=; b=m5bSlFQaDSVwzTdakLreczF+YFnT3YTxM17l2MMe/Ni9Tl9svWYwvNwmZvoeSGfklg sBJKaYAqK7e0uIVM42xuSa0s9KV9GtA+CiGRlBPS90mnYgGIcelyj6bJphWe34tEKKUU pTYNa1/evUSyk9Zg/mYFlxd6mJBZ5hcguWJFS/PoZGVCo73NPgajuU7tKySSxE/ml/mV gnF5qbX2fB54WKKHvPpGVUdKQbdCJKa7pJd5s7Ch9T/r9jnOHdjOgutvH2zVpIavm7Fa DHZABgvnXi49cRLgA0xEB9VBpjC1Fs6EuhASkxdQOSv0JEy5vTvkXzzxZCl12vdGJTXe Rlaw== X-Gm-Message-State: AOJu0Yzwuuk0a8rj4KT957zMsYRTff5fsPN/4r3+mCAE1/aiRr3R31YO 6Pc2AQyuYmC7tXdmtC3Uytck1zCenEIOg4na X-Google-Smtp-Source: AGHT+IFfWv1GmyIdO3JIejM485TOadT74WYATLo4SY7TxZ4zuaMj/llhDuRRvK/ZI7w+RBBZOk/0xw== X-Received: by 2002:a17:903:1c5:b0:1b8:865d:6e1d with SMTP id e5-20020a17090301c500b001b8865d6e1dmr1649351plh.51.1694153218392; Thu, 07 Sep 2023 23:06:58 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Yong-Xuan Wang , Jim Shu , Daniel Henrique Barboza , Andrew Jones , Alistair Francis Subject: [PULL 32/65] target/riscv: update APLIC and IMSIC to support KVM AIA Date: Fri, 8 Sep 2023 16:03:58 +1000 Message-ID: <20230908060431.1903919-33-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230908060431.1903919-1-alistair.francis@wdc.com> References: <20230908060431.1903919-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=alistair23@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694153401885100011 Content-Type: text/plain; charset="utf-8" From: Yong-Xuan Wang KVM AIA can't emulate APLIC only. When "aia=3Daplic" parameter is passed, APLIC devices is emulated by QEMU. For "aia=3Daplic-imsic", remove the mmio operations of APLIC when using KVM AIA and send wired interrupt signal via KVM_IRQ_LINE API. After KVM AIA enabled, MSI messages are delivered by KVM_SIGNAL_MSI API when the IMSICs receive mmio write requests. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Message-ID: <20230727102439.22554-5-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis --- hw/intc/riscv_aplic.c | 56 ++++++++++++++++++++++++++++++------------- hw/intc/riscv_imsic.c | 25 +++++++++++++++---- 2 files changed, 61 insertions(+), 20 deletions(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 4bdc6a5d1a..592c3ce768 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -31,6 +31,7 @@ #include "hw/irq.h" #include "target/riscv/cpu.h" #include "sysemu/sysemu.h" +#include "sysemu/kvm.h" #include "migration/vmstate.h" =20 #define APLIC_MAX_IDC (1UL << 14) @@ -148,6 +149,15 @@ =20 #define APLIC_IDC_CLAIMI 0x1c =20 +/* + * KVM AIA only supports APLIC MSI, fallback to QEMU emulation if we want = to use + * APLIC Wired. + */ +static bool is_kvm_aia(bool msimode) +{ + return kvm_irqchip_in_kernel() && msimode; +} + static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic, uint32_t word) { @@ -471,6 +481,11 @@ static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState= *aplic, uint32_t idc) return topi; } =20 +static void riscv_kvm_aplic_request(void *opaque, int irq, int level) +{ + kvm_set_irq(kvm_state, irq, !!level); +} + static void riscv_aplic_request(void *opaque, int irq, int level) { bool update =3D false; @@ -801,29 +816,35 @@ static void riscv_aplic_realize(DeviceState *dev, Err= or **errp) uint32_t i; RISCVAPLICState *aplic =3D RISCV_APLIC(dev); =20 - aplic->bitfield_words =3D (aplic->num_irqs + 31) >> 5; - aplic->sourcecfg =3D g_new0(uint32_t, aplic->num_irqs); - aplic->state =3D g_new0(uint32_t, aplic->num_irqs); - aplic->target =3D g_new0(uint32_t, aplic->num_irqs); - if (!aplic->msimode) { - for (i =3D 0; i < aplic->num_irqs; i++) { - aplic->target[i] =3D 1; + if (!is_kvm_aia(aplic->msimode)) { + aplic->bitfield_words =3D (aplic->num_irqs + 31) >> 5; + aplic->sourcecfg =3D g_new0(uint32_t, aplic->num_irqs); + aplic->state =3D g_new0(uint32_t, aplic->num_irqs); + aplic->target =3D g_new0(uint32_t, aplic->num_irqs); + if (!aplic->msimode) { + for (i =3D 0; i < aplic->num_irqs; i++) { + aplic->target[i] =3D 1; + } } - } - aplic->idelivery =3D g_new0(uint32_t, aplic->num_harts); - aplic->iforce =3D g_new0(uint32_t, aplic->num_harts); - aplic->ithreshold =3D g_new0(uint32_t, aplic->num_harts); + aplic->idelivery =3D g_new0(uint32_t, aplic->num_harts); + aplic->iforce =3D g_new0(uint32_t, aplic->num_harts); + aplic->ithreshold =3D g_new0(uint32_t, aplic->num_harts); =20 - memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, apl= ic, - TYPE_RISCV_APLIC, aplic->aperture_size); - sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio); + memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, + aplic, TYPE_RISCV_APLIC, aplic->aperture_siz= e); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio); + } =20 /* * Only root APLICs have hardware IRQ lines. All non-root APLICs * have IRQ lines delegated by their parent APLIC. */ if (!aplic->parent) { - qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs); + if (is_kvm_aia(aplic->msimode)) { + qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irq= s); + } else { + qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs); + } } =20 /* Create output IRQ lines for non-MSI mode */ @@ -958,7 +979,10 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr si= ze, qdev_prop_set_bit(dev, "mmode", mmode); =20 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + + if (!is_kvm_aia(msimode)) { + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + } =20 if (parent) { riscv_aplic_add_child(parent, dev); diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index fea3385b51..760dbddcf7 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -32,6 +32,7 @@ #include "target/riscv/cpu.h" #include "target/riscv/cpu_bits.h" #include "sysemu/sysemu.h" +#include "sysemu/kvm.h" #include "migration/vmstate.h" =20 #define IMSIC_MMIO_PAGE_LE 0x00 @@ -283,6 +284,20 @@ static void riscv_imsic_write(void *opaque, hwaddr add= r, uint64_t value, goto err; } =20 +#if defined(CONFIG_KVM) + if (kvm_irqchip_in_kernel()) { + struct kvm_msi msi; + + msi.address_lo =3D extract64(imsic->mmio.addr + addr, 0, 32); + msi.address_hi =3D extract64(imsic->mmio.addr + addr, 32, 32); + msi.data =3D le32_to_cpu(value); + + kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi); + + return; + } +#endif + /* Writes only supported for MSI little-endian registers */ page =3D addr >> IMSIC_MMIO_PAGE_SHIFT; if ((addr & (IMSIC_MMIO_PAGE_SZ - 1)) =3D=3D IMSIC_MMIO_PAGE_LE) { @@ -320,10 +335,12 @@ static void riscv_imsic_realize(DeviceState *dev, Err= or **errp) CPUState *cpu =3D cpu_by_arch_id(imsic->hartid); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; =20 - imsic->num_eistate =3D imsic->num_pages * imsic->num_irqs; - imsic->eidelivery =3D g_new0(uint32_t, imsic->num_pages); - imsic->eithreshold =3D g_new0(uint32_t, imsic->num_pages); - imsic->eistate =3D g_new0(uint32_t, imsic->num_eistate); + if (!kvm_irqchip_in_kernel()) { + imsic->num_eistate =3D imsic->num_pages * imsic->num_irqs; + imsic->eidelivery =3D g_new0(uint32_t, imsic->num_pages); + imsic->eithreshold =3D g_new0(uint32_t, imsic->num_pages); + imsic->eistate =3D g_new0(uint32_t, imsic->num_eistate); + } =20 memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops, imsic, TYPE_RISCV_IMSIC, --=20 2.41.0