From nobody Fri Nov 15 11:35:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=jia.je ARC-Seal: i=1; a=rsa-sha256; t=1694139998; cv=none; d=zohomail.com; s=zohoarc; b=mMO4aPBHbsmIKQNtueBIar9HXV0frI5uAn3gQaLTb129S5nDJuIRbP9BU9Tm10/7LL4Vr1l8dqrQx13Z0sou9r9Z0XbODu6ORpjGfjv7t7/NF/Lys3Rx6q7lD52w1/x8Yh1uDaeXJI480GqnO4ingWLJysUYZD0d9qw6sU2eyJA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694139998; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Q5Z/SYfeh0dWR8MNSoRWiXQMpV3f30oYafU/hT7IPis=; b=lPwaEawrrwXirSYGWsOpBNzh+gipl7ev0UoNeTs2Pm4q77TupPnsotuA24iM+/4ewp25QGfFfEI0+tUkbOHKpXw9OHeurL4FxRfXwZRjAIwpgeAEeespq7E09vwkMnw4JOQwSoK2KRAkyWbaHuXFC/65uuJDOW2Fh+QPiXyitDw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694139998668418.60915469804957; Thu, 7 Sep 2023 19:26:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qeRAN-0002lF-SB; Thu, 07 Sep 2023 22:24:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qeRAN-0002l6-1a for qemu-devel@nongnu.org; Thu, 07 Sep 2023 22:24:15 -0400 Received: from hognose1.porkbun.com ([35.82.102.206]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qeRAK-0006xY-Kt for qemu-devel@nongnu.org; Thu, 07 Sep 2023 22:24:14 -0400 Received: from ls3a6000.. (unknown [223.72.41.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: c@jia.je) by hognose1.porkbun.com (Postfix) with ESMTPSA id EB36B44218; Fri, 8 Sep 2023 02:23:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jia.je; s=default; t=1694139841; bh=Q5Z/SYfeh0dWR8MNSoRWiXQMpV3f30oYafU/hT7IPis=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=CGiRtZEBFHvlBOB7+51tttgAiDVjNkymgRJHEIjs0ttKaRAfhDa9QEgkPJdva/28p 918fQw5RUwRM11LCsOtwNc3vv3Ln1WEVMoNobqvZ5nKvb2tzYBxN6GvBwrfpkvwzSj 7VLfcJXe6eBDNP4ymRn7x1Govb1rITz/Ch0h6nkE= From: Jiajie Chen To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, git@xen0n.name, Jiajie Chen Subject: [PATCH v4 16/16] tcg/loongarch64: Implement 128-bit load & store Date: Fri, 8 Sep 2023 10:21:23 +0800 Message-ID: <20230908022302.180442-17-c@jia.je> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230908022302.180442-1-c@jia.je> References: <20230908022302.180442-1-c@jia.je> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=35.82.102.206; envelope-from=c@jia.je; helo=hognose1.porkbun.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @jia.je) X-ZM-MESSAGEID: 1694140000609100003 Content-Type: text/plain; charset="utf-8" If LSX is available, use LSX instructions to implement 128-bit load & store when MO_128 is required, otherwise use two 64-bit loads & stores. Signed-off-by: Jiajie Chen --- tcg/loongarch64/tcg-target-con-set.h | 2 + tcg/loongarch64/tcg-target.c.inc | 59 ++++++++++++++++++++++++++++ tcg/loongarch64/tcg-target.h | 2 +- 3 files changed, 62 insertions(+), 1 deletion(-) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-tar= get-con-set.h index 914572d21b..77d62e38e7 100644 --- a/tcg/loongarch64/tcg-target-con-set.h +++ b/tcg/loongarch64/tcg-target-con-set.h @@ -18,6 +18,7 @@ C_O0_I1(r) C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) C_O0_I2(w, r) +C_O0_I3(r, r, r) C_O1_I1(r, r) C_O1_I1(w, r) C_O1_I1(w, w) @@ -37,3 +38,4 @@ C_O1_I2(w, w, wM) C_O1_I2(w, w, wA) C_O1_I3(w, w, w, w) C_O1_I4(r, rZ, rJ, rZ, rZ) +C_O2_I1(r, r, r) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 82901d678a..6e9f334fed 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1081,6 +1081,48 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg da= ta_reg, TCGReg addr_reg, } } =20 +static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg data_lo, TCGReg d= ata_hi, + TCGReg addr_reg, MemOpIdx oi, bool is_l= d) +{ + TCGLabelQemuLdst *ldst; + HostAddress h; + + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, true); + + if (h.aa.atom =3D=3D MO_128) { + /* + * Use VLDX/VSTX when 128-bit atomicity is required. + * If address is aligned to 16-bytes, the 128-bit load/store is at= omic. + */ + if (is_ld) { + tcg_out_opc_vldx(s, TCG_VEC_TMP0, h.base, h.index); + tcg_out_opc_vpickve2gr_d(s, data_lo, TCG_VEC_TMP0, 0); + tcg_out_opc_vpickve2gr_d(s, data_hi, TCG_VEC_TMP0, 1); + } else { + tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_lo, 0); + tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_hi, 1); + tcg_out_opc_vstx(s, TCG_VEC_TMP0, h.base, h.index); + } + } else { + /* otherwise use a pair of LD/ST */ + tcg_out_opc_add_d(s, TCG_REG_TMP0, h.base, h.index); + if (is_ld) { + tcg_out_opc_ld_d(s, data_lo, TCG_REG_TMP0, 0); + tcg_out_opc_ld_d(s, data_hi, TCG_REG_TMP0, 8); + } else { + tcg_out_opc_st_d(s, data_lo, TCG_REG_TMP0, 0); + tcg_out_opc_st_d(s, data_hi, TCG_REG_TMP0, 8); + } + } + + if (ldst) { + ldst->type =3D TCG_TYPE_I128; + ldst->datalo_reg =3D data_lo; + ldst->datahi_reg =3D data_hi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); + } +} + /* * Entry-points */ @@ -1145,6 +1187,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGArg a0 =3D args[0]; TCGArg a1 =3D args[1]; TCGArg a2 =3D args[2]; + TCGArg a3 =3D args[3]; int c2 =3D const_args[2]; =20 switch (opc) { @@ -1507,6 +1550,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_qemu_ld_a64_i64: tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); break; + case INDEX_op_qemu_ld_a32_i128: + case INDEX_op_qemu_ld_a64_i128: + tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, true); + break; case INDEX_op_qemu_st_a32_i32: case INDEX_op_qemu_st_a64_i32: tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); @@ -1515,6 +1562,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_qemu_st_a64_i64: tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); break; + case INDEX_op_qemu_st_a32_i128: + case INDEX_op_qemu_st_a64_i128: + tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, false); + break; =20 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: @@ -1996,6 +2047,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_qemu_st_a64_i64: return C_O0_I2(rZ, r); =20 + case INDEX_op_qemu_ld_a32_i128: + case INDEX_op_qemu_ld_a64_i128: + return C_O2_I1(r, r, r); + + case INDEX_op_qemu_st_a32_i128: + case INDEX_op_qemu_st_a64_i128: + return C_O0_I3(r, r, r); + case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: return C_O0_I2(rZ, rZ); diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index 67b0a95532..03017672f6 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -171,7 +171,7 @@ extern bool use_lsx_instructions; #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 =20 -#define TCG_TARGET_HAS_qemu_ldst_i128 0 +#define TCG_TARGET_HAS_qemu_ldst_i128 use_lsx_instructions =20 #define TCG_TARGET_HAS_v64 0 #define TCG_TARGET_HAS_v128 use_lsx_instructions --=20 2.42.0