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Thu, 07 Sep 2023 16:32:03 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bxxsx+ivlk8FVwAA--.49124S6; Thu, 07 Sep 2023 16:32:02 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, maobibo@loongson.cn Subject: [PATCH RESEND v5 04/57] target/loongarch: Use gen_helper_gvec_4 for 4OP vector instructions Date: Thu, 7 Sep 2023 16:31:05 +0800 Message-Id: <20230907083158.3975132-5-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230907083158.3975132-1-gaosong@loongson.cn> References: <20230907083158.3975132-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8Bxxsx+ivlk8FVwAA--.49124S6 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1694076106570100002 Content-Type: text/plain; charset="utf-8" Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/helper.h | 2 +- target/loongarch/vec_helper.c | 11 +++++------ target/loongarch/insn_trans/trans_vec.c.inc | 22 ++++++++++++--------- 3 files changed, 19 insertions(+), 16 deletions(-) diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h index ead16567c2..727ccfb32c 100644 --- a/target/loongarch/helper.h +++ b/target/loongarch/helper.h @@ -682,7 +682,7 @@ DEF_HELPER_4(vilvh_h, void, env, i32, i32, i32) DEF_HELPER_4(vilvh_w, void, env, i32, i32, i32) DEF_HELPER_4(vilvh_d, void, env, i32, i32, i32) =20 -DEF_HELPER_5(vshuf_b, void, env, i32, i32, i32, i32) +DEF_HELPER_FLAGS_5(vshuf_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_4(vshuf_h, void, env, i32, i32, i32) DEF_HELPER_4(vshuf_w, void, env, i32, i32, i32) DEF_HELPER_4(vshuf_d, void, env, i32, i32, i32) diff --git a/target/loongarch/vec_helper.c b/target/loongarch/vec_helper.c index 3a7a620227..7078c4c845 100644 --- a/target/loongarch/vec_helper.c +++ b/target/loongarch/vec_helper.c @@ -2899,15 +2899,14 @@ VILVH(vilvh_h, 32, H) VILVH(vilvh_w, 64, W) VILVH(vilvh_d, 128, D) =20 -void HELPER(vshuf_b)(CPULoongArchState *env, - uint32_t vd, uint32_t vj, uint32_t vk, uint32_t va) +void HELPER(vshuf_b)(void *vd, void *vj, void *vk, void *va, uint32_t desc) { int i, m; VReg temp; - VReg *Vd =3D &(env->fpr[vd].vreg); - VReg *Vj =3D &(env->fpr[vj].vreg); - VReg *Vk =3D &(env->fpr[vk].vreg); - VReg *Va =3D &(env->fpr[va].vreg); + VReg *Vd =3D (VReg *)vd; + VReg *Vj =3D (VReg *)vj; + VReg *Vk =3D (VReg *)vk; + VReg *Va =3D (VReg *)va; =20 m =3D LSX_LEN/8; for (i =3D 0; i < m ; i++) { diff --git a/target/loongarch/insn_trans/trans_vec.c.inc b/target/loongarch= /insn_trans/trans_vec.c.inc index 85bc8670a7..6f45296987 100644 --- a/target/loongarch/insn_trans/trans_vec.c.inc +++ b/target/loongarch/insn_trans/trans_vec.c.inc @@ -34,18 +34,22 @@ static bool gen_vvvv_ptr(DisasContext *ctx, arg_vvvv *a, return gen_vvvv_ptr_vl(ctx, a, 16, fn); } =20 -static bool gen_vvvv(DisasContext *ctx, arg_vvvv *a, - void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32, - TCGv_i32, TCGv_i32)) +static bool gen_vvvv_vl(DisasContext *ctx, arg_vvvv *a, uint32_t oprsz, + gen_helper_gvec_4 *fn) { - TCGv_i32 vd =3D tcg_constant_i32(a->vd); - TCGv_i32 vj =3D tcg_constant_i32(a->vj); - TCGv_i32 vk =3D tcg_constant_i32(a->vk); - TCGv_i32 va =3D tcg_constant_i32(a->va); + tcg_gen_gvec_4_ool(vec_full_offset(a->vd), + vec_full_offset(a->vj), + vec_full_offset(a->vk), + vec_full_offset(a->va), + oprsz, ctx->vl / 8, oprsz, fn); + return true; +} =20 +static bool gen_vvvv(DisasContext *ctx, arg_vvvv *a, + gen_helper_gvec_4 *fn) +{ CHECK_SXE; - func(cpu_env, vd, vj, vk, va); - return true; + return gen_vvvv_vl(ctx, a, 16, fn); } =20 static bool gen_vvv(DisasContext *ctx, arg_vvv *a, --=20 2.39.1