From nobody Thu Nov 28 10:59:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694075811826752.3125965805579; Thu, 7 Sep 2023 01:36:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qeARe-0004ew-Tq; Thu, 07 Sep 2023 04:32:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qeARX-0004Oi-QO for qemu-devel@nongnu.org; Thu, 07 Sep 2023 04:32:51 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qeARU-0002Mr-3V for qemu-devel@nongnu.org; Thu, 07 Sep 2023 04:32:51 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8AxlPChivlkOjkhAA--.786S3; Thu, 07 Sep 2023 16:32:33 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bxxsx+ivlk8FVwAA--.49124S40; Thu, 07 Sep 2023 16:32:33 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, maobibo@loongson.cn Subject: [PATCH RESEND v5 38/57] target/loongarch: Implement xvsrln xvsran Date: Thu, 7 Sep 2023 16:31:39 +0800 Message-Id: <20230907083158.3975132-39-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230907083158.3975132-1-gaosong@loongson.cn> References: <20230907083158.3975132-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8Bxxsx+ivlk8FVwAA--.49124S40 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1694075813677100001 Content-Type: text/plain; charset="utf-8" This patch includes: - XVSRLN.{B.H/H.W/W.D}; - XVSRAN.{B.H/H.W/W.D}; - XVSRLNI.{B.H/H.W/W.D/D.Q}; - XVSRANI.{B.H/H.W/W.D/D.Q}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 16 ++ target/loongarch/disas.c | 16 ++ target/loongarch/vec_helper.c | 166 +++++++++++--------- target/loongarch/insn_trans/trans_vec.c.inc | 14 ++ 4 files changed, 137 insertions(+), 75 deletions(-) diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index ca0951e1cc..204dcfa075 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -1678,6 +1678,22 @@ xvsrari_h 0111 01101010 10000 1 .... ..... ..= ... @vv_ui4 xvsrari_w 0111 01101010 10001 ..... ..... ..... @vv_ui5 xvsrari_d 0111 01101010 1001 ...... ..... ..... @vv_ui6 =20 +xvsrln_b_h 0111 01001111 01001 ..... ..... ..... @vvv +xvsrln_h_w 0111 01001111 01010 ..... ..... ..... @vvv +xvsrln_w_d 0111 01001111 01011 ..... ..... ..... @vvv +xvsran_b_h 0111 01001111 01101 ..... ..... ..... @vvv +xvsran_h_w 0111 01001111 01110 ..... ..... ..... @vvv +xvsran_w_d 0111 01001111 01111 ..... ..... ..... @vvv + +xvsrlni_b_h 0111 01110100 00000 1 .... ..... ..... @vv_ui4 +xvsrlni_h_w 0111 01110100 00001 ..... ..... ..... @vv_ui5 +xvsrlni_w_d 0111 01110100 0001 ...... ..... ..... @vv_ui6 +xvsrlni_d_q 0111 01110100 001 ....... ..... ..... @vv_ui7 +xvsrani_b_h 0111 01110101 10000 1 .... ..... ..... @vv_ui4 +xvsrani_h_w 0111 01110101 10001 ..... ..... ..... @vv_ui5 +xvsrani_w_d 0111 01110101 1001 ...... ..... ..... @vv_ui6 +xvsrani_d_q 0111 01110101 101 ....... ..... ..... @vv_ui7 + xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c index bc5eb82b49..28e5e16eb2 100644 --- a/target/loongarch/disas.c +++ b/target/loongarch/disas.c @@ -2104,6 +2104,22 @@ INSN_LASX(xvsrari_h, vv_i) INSN_LASX(xvsrari_w, vv_i) INSN_LASX(xvsrari_d, vv_i) =20 +INSN_LASX(xvsrln_b_h, vvv) +INSN_LASX(xvsrln_h_w, vvv) +INSN_LASX(xvsrln_w_d, vvv) +INSN_LASX(xvsran_b_h, vvv) +INSN_LASX(xvsran_h_w, vvv) +INSN_LASX(xvsran_w_d, vvv) + +INSN_LASX(xvsrlni_b_h, vv_i) +INSN_LASX(xvsrlni_h_w, vv_i) +INSN_LASX(xvsrlni_w_d, vv_i) +INSN_LASX(xvsrlni_d_q, vv_i) +INSN_LASX(xvsrani_b_h, vv_i) +INSN_LASX(xvsrani_h_w, vv_i) +INSN_LASX(xvsrani_w_d, vv_i) +INSN_LASX(xvsrani_d_q, vv_i) + INSN_LASX(xvreplgr2vr_b, vr) INSN_LASX(xvreplgr2vr_h, vr) INSN_LASX(xvreplgr2vr_w, vr) diff --git a/target/loongarch/vec_helper.c b/target/loongarch/vec_helper.c index bb30d24b89..8c405ce32b 100644 --- a/target/loongarch/vec_helper.c +++ b/target/loongarch/vec_helper.c @@ -1109,105 +1109,121 @@ VSRARI(vsrari_d, 64, D) =20 #define R_SHIFT(a, b) (a >> b) =20 -#define VSRLN(NAME, BIT, T, E1, E2) \ -void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \ -{ \ - int i; \ - VReg *Vd =3D (VReg *)vd; \ - VReg *Vj =3D (VReg *)vj; \ - VReg *Vk =3D (VReg *)vk; \ - \ - for (i =3D 0; i < LSX_LEN/BIT; i++) { \ - Vd->E1(i) =3D R_SHIFT((T)Vj->E2(i),((T)Vk->E2(i)) % BIT); \ - } \ - Vd->D(1) =3D 0; \ +#define VSRLN(NAME, BIT, E1, E2) \ +void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \ +{ \ + int i, j, ofs; \ + VReg *Vd =3D (VReg *)vd; = \ + VReg *Vj =3D (VReg *)vj; = \ + VReg *Vk =3D (VReg *)vk; = \ + int oprsz =3D simd_oprsz(desc); = \ + \ + ofs =3D LSX_LEN / BIT; = \ + for (i =3D 0; i < oprsz / 16; i++) { = \ + for (j =3D 0; j < ofs; j++) { = \ + Vd->E1(j + ofs * 2 * i) =3D R_SHIFT(Vj->E2(j + ofs * i), = \ + Vk->E2(j + ofs * i) % BIT); \ + } \ + Vd->D(2 * i + 1) =3D 0; = \ + } \ } =20 -VSRLN(vsrln_b_h, 16, uint16_t, B, H) -VSRLN(vsrln_h_w, 32, uint32_t, H, W) -VSRLN(vsrln_w_d, 64, uint64_t, W, D) +VSRLN(vsrln_b_h, 16, B, UH) +VSRLN(vsrln_h_w, 32, H, UW) +VSRLN(vsrln_w_d, 64, W, UD) =20 -#define VSRAN(NAME, BIT, T, E1, E2) \ -void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \ -{ \ - int i; \ - VReg *Vd =3D (VReg *)vd; \ - VReg *Vj =3D (VReg *)vj; \ - VReg *Vk =3D (VReg *)vk; \ - \ - for (i =3D 0; i < LSX_LEN/BIT; i++) { \ - Vd->E1(i) =3D R_SHIFT(Vj->E2(i), ((T)Vk->E2(i)) % BIT); \ - } \ - Vd->D(1) =3D 0; \ +#define VSRAN(NAME, BIT, E1, E2, E3) \ +void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \ +{ \ + int i, j, ofs; \ + VReg *Vd =3D (VReg *)vd; = \ + VReg *Vj =3D (VReg *)vj; = \ + VReg *Vk =3D (VReg *)vk; = \ + int oprsz =3D simd_oprsz(desc); = \ + \ + ofs =3D LSX_LEN / BIT; = \ + for (i =3D 0; i < oprsz / 16; i++) { = \ + for (j =3D 0; j < ofs; j++) { = \ + Vd->E1(j + ofs * 2 * i) =3D R_SHIFT(Vj->E2(j + ofs * i), = \ + Vk->E3(j + ofs * i) % BIT); \ + } \ + Vd->D(2 * i + 1) =3D 0; = \ + } \ } =20 -VSRAN(vsran_b_h, 16, uint16_t, B, H) -VSRAN(vsran_h_w, 32, uint32_t, H, W) -VSRAN(vsran_w_d, 64, uint64_t, W, D) +VSRAN(vsran_b_h, 16, B, H, UH) +VSRAN(vsran_h_w, 32, H, W, UW) +VSRAN(vsran_w_d, 64, W, D, UD) =20 -#define VSRLNI(NAME, BIT, T, E1, E2) \ -void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \ -{ \ - int i, max; \ - VReg temp; \ - VReg *Vd =3D (VReg *)vd; \ - VReg *Vj =3D (VReg *)vj; \ - \ - temp.D(0) =3D 0; \ - temp.D(1) =3D 0; \ - max =3D LSX_LEN/BIT; \ - for (i =3D 0; i < max; i++) { \ - temp.E1(i) =3D R_SHIFT((T)Vj->E2(i), imm); \ - temp.E1(i + max) =3D R_SHIFT((T)Vd->E2(i), imm); \ - } \ - *Vd =3D temp; \ +#define VSRLNI(NAME, BIT, E1, E2) \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \ +{ \ + int i, j, ofs; \ + VReg temp =3D {}; = \ + VReg *Vd =3D (VReg *)vd; = \ + VReg *Vj =3D (VReg *)vj; = \ + int oprsz =3D simd_oprsz(desc); = \ + \ + ofs =3D LSX_LEN / BIT; = \ + for (i =3D 0; i < oprsz / 16; i++) { = \ + for (j =3D 0; j < ofs; j++) { = \ + temp.E1(j + ofs * 2 * i) =3D R_SHIFT(Vj->E2(j + ofs * i), imm)= ; \ + temp.E1(j + ofs * (2 * i + 1)) =3D R_SHIFT(Vd->E2(j + ofs * i)= , \ + imm); \ + } \ + } \ + *Vd =3D temp; = \ } =20 void HELPER(vsrlni_d_q)(void *vd, void *vj, uint64_t imm, uint32_t desc) { - VReg temp; + int i; + VReg temp =3D {}; VReg *Vd =3D (VReg *)vd; VReg *Vj =3D (VReg *)vj; =20 - temp.D(0) =3D 0; - temp.D(1) =3D 0; - temp.D(0) =3D int128_getlo(int128_urshift(Vj->Q(0), imm % 128)); - temp.D(1) =3D int128_getlo(int128_urshift(Vd->Q(0), imm % 128)); + for (i =3D 0; i < 2; i++) { + temp.D(2 * i) =3D int128_getlo(int128_urshift(Vj->Q(i), imm % 128)= ); + temp.D(2 * i +1) =3D int128_getlo(int128_urshift(Vd->Q(i), imm % 1= 28)); + } *Vd =3D temp; } =20 -VSRLNI(vsrlni_b_h, 16, uint16_t, B, H) -VSRLNI(vsrlni_h_w, 32, uint32_t, H, W) -VSRLNI(vsrlni_w_d, 64, uint64_t, W, D) +VSRLNI(vsrlni_b_h, 16, B, UH) +VSRLNI(vsrlni_h_w, 32, H, UW) +VSRLNI(vsrlni_w_d, 64, W, UD) =20 -#define VSRANI(NAME, BIT, E1, E2) \ -void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \ -{ \ - int i, max; \ - VReg temp; \ - VReg *Vd =3D (VReg *)vd; \ - VReg *Vj =3D (VReg *)vj; \ - \ - temp.D(0) =3D 0; \ - temp.D(1) =3D 0; \ - max =3D LSX_LEN/BIT; \ - for (i =3D 0; i < max; i++) { \ - temp.E1(i) =3D R_SHIFT(Vj->E2(i), imm); \ - temp.E1(i + max) =3D R_SHIFT(Vd->E2(i), imm); \ - } \ - *Vd =3D temp; \ +#define VSRANI(NAME, BIT, E1, E2) \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \ +{ \ + int i, j, ofs; \ + VReg temp =3D {}; = \ + VReg *Vd =3D (VReg *)vd; = \ + VReg *Vj =3D (VReg *)vj; = \ + int oprsz =3D simd_oprsz(desc); = \ + \ + ofs =3D LSX_LEN / BIT; = \ + for (i =3D 0; i < oprsz / 16; i++) { = \ + for (j =3D 0; j < ofs; j++) { = \ + temp.E1(j + ofs * 2 * i) =3D R_SHIFT(Vj->E2(j + ofs * i), imm)= ; \ + temp.E1(j + ofs * (2 * i + 1)) =3D R_SHIFT(Vd->E2(j + ofs * i)= , \ + imm); \ + } \ + } \ + *Vd =3D temp; = \ } =20 void HELPER(vsrani_d_q)(void *vd, void *vj, uint64_t imm, uint32_t desc) { - VReg temp; + int i; + VReg temp =3D {}; VReg *Vd =3D (VReg *)vd; VReg *Vj =3D (VReg *)vj; =20 - temp.D(0) =3D 0; - temp.D(1) =3D 0; - temp.D(0) =3D int128_getlo(int128_rshift(Vj->Q(0), imm % 128)); - temp.D(1) =3D int128_getlo(int128_rshift(Vd->Q(0), imm % 128)); + for (i =3D 0; i < 2; i++) { + temp.D(2 * i) =3D int128_getlo(int128_rshift(Vj->Q(i), imm % 128)); + temp.D(2 * i + 1) =3D int128_getlo(int128_rshift(Vd->Q(i), imm % 1= 28)); + } *Vd =3D temp; } =20 diff --git a/target/loongarch/insn_trans/trans_vec.c.inc b/target/loongarch= /insn_trans/trans_vec.c.inc index 9d95c42708..01934e5f97 100644 --- a/target/loongarch/insn_trans/trans_vec.c.inc +++ b/target/loongarch/insn_trans/trans_vec.c.inc @@ -3835,6 +3835,12 @@ TRANS(vsrln_w_d, LSX, gen_vvv, gen_helper_vsrln_w_d) TRANS(vsran_b_h, LSX, gen_vvv, gen_helper_vsran_b_h) TRANS(vsran_h_w, LSX, gen_vvv, gen_helper_vsran_h_w) TRANS(vsran_w_d, LSX, gen_vvv, gen_helper_vsran_w_d) +TRANS(xvsrln_b_h, LASX, gen_xxx, gen_helper_vsrln_b_h) +TRANS(xvsrln_h_w, LASX, gen_xxx, gen_helper_vsrln_h_w) +TRANS(xvsrln_w_d, LASX, gen_xxx, gen_helper_vsrln_w_d) +TRANS(xvsran_b_h, LASX, gen_xxx, gen_helper_vsran_b_h) +TRANS(xvsran_h_w, LASX, gen_xxx, gen_helper_vsran_h_w) +TRANS(xvsran_w_d, LASX, gen_xxx, gen_helper_vsran_w_d) =20 TRANS(vsrlni_b_h, LSX, gen_vv_i, gen_helper_vsrlni_b_h) TRANS(vsrlni_h_w, LSX, gen_vv_i, gen_helper_vsrlni_h_w) @@ -3844,6 +3850,14 @@ TRANS(vsrani_b_h, LSX, gen_vv_i, gen_helper_vsrani_b= _h) TRANS(vsrani_h_w, LSX, gen_vv_i, gen_helper_vsrani_h_w) TRANS(vsrani_w_d, LSX, gen_vv_i, gen_helper_vsrani_w_d) TRANS(vsrani_d_q, LSX, gen_vv_i, gen_helper_vsrani_d_q) +TRANS(xvsrlni_b_h, LASX, gen_xx_i, gen_helper_vsrlni_b_h) +TRANS(xvsrlni_h_w, LASX, gen_xx_i, gen_helper_vsrlni_h_w) +TRANS(xvsrlni_w_d, LASX, gen_xx_i, gen_helper_vsrlni_w_d) +TRANS(xvsrlni_d_q, LASX, gen_xx_i, gen_helper_vsrlni_d_q) +TRANS(xvsrani_b_h, LASX, gen_xx_i, gen_helper_vsrani_b_h) +TRANS(xvsrani_h_w, LASX, gen_xx_i, gen_helper_vsrani_h_w) +TRANS(xvsrani_w_d, LASX, gen_xx_i, gen_helper_vsrani_w_d) +TRANS(xvsrani_d_q, LASX, gen_xx_i, gen_helper_vsrani_d_q) =20 TRANS(vsrlrn_b_h, LSX, gen_vvv, gen_helper_vsrlrn_b_h) TRANS(vsrlrn_h_w, LSX, gen_vvv, gen_helper_vsrlrn_h_w) --=20 2.39.1