From nobody Thu Nov 28 09:49:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694075928490793.7914101406402; Thu, 7 Sep 2023 01:38:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qeARI-0003sZ-5T; Thu, 07 Sep 2023 04:32:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qeARF-0003nz-CY for qemu-devel@nongnu.org; Thu, 07 Sep 2023 04:32:33 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qeARC-0002Jo-6r for qemu-devel@nongnu.org; Thu, 07 Sep 2023 04:32:33 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8CxruuSivlkAjkhAA--.63511S3; Thu, 07 Sep 2023 16:32:18 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bxxsx+ivlk8FVwAA--.49124S21; Thu, 07 Sep 2023 16:32:17 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, maobibo@loongson.cn Subject: [PATCH RESEND v5 19/57] target/loongarch: Implement xvhaddw/xvhsubw Date: Thu, 7 Sep 2023 16:31:20 +0800 Message-Id: <20230907083158.3975132-20-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230907083158.3975132-1-gaosong@loongson.cn> References: <20230907083158.3975132-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8Bxxsx+ivlk8FVwAA--.49124S21 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1694075930125100001 Content-Type: text/plain; charset="utf-8" This patch includes: - XVHADDW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}; - XVHSUBW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 18 +++++++++++ target/loongarch/disas.c | 17 +++++++++++ target/loongarch/vec_helper.c | 34 ++++++++++++++++----- target/loongarch/insn_trans/trans_vec.c.inc | 26 ++++++++++++++++ 4 files changed, 88 insertions(+), 7 deletions(-) diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index 32f857ff7c..ba0b36f4a7 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -1343,6 +1343,24 @@ xvssub_hu 0111 01000100 11001 ..... ..... ...= .. @vvv xvssub_wu 0111 01000100 11010 ..... ..... ..... @vvv xvssub_du 0111 01000100 11011 ..... ..... ..... @vvv =20 +xvhaddw_h_b 0111 01000101 01000 ..... ..... ..... @vvv +xvhaddw_w_h 0111 01000101 01001 ..... ..... ..... @vvv +xvhaddw_d_w 0111 01000101 01010 ..... ..... ..... @vvv +xvhaddw_q_d 0111 01000101 01011 ..... ..... ..... @vvv +xvhaddw_hu_bu 0111 01000101 10000 ..... ..... ..... @vvv +xvhaddw_wu_hu 0111 01000101 10001 ..... ..... ..... @vvv +xvhaddw_du_wu 0111 01000101 10010 ..... ..... ..... @vvv +xvhaddw_qu_du 0111 01000101 10011 ..... ..... ..... @vvv + +xvhsubw_h_b 0111 01000101 01100 ..... ..... ..... @vvv +xvhsubw_w_h 0111 01000101 01101 ..... ..... ..... @vvv +xvhsubw_d_w 0111 01000101 01110 ..... ..... ..... @vvv +xvhsubw_q_d 0111 01000101 01111 ..... ..... ..... @vvv +xvhsubw_hu_bu 0111 01000101 10100 ..... ..... ..... @vvv +xvhsubw_wu_hu 0111 01000101 10101 ..... ..... ..... @vvv +xvhsubw_du_wu 0111 01000101 10110 ..... ..... ..... @vvv +xvhsubw_qu_du 0111 01000101 10111 ..... ..... ..... @vvv + xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c index 4ba4fbfc64..c810a52f0d 100644 --- a/target/loongarch/disas.c +++ b/target/loongarch/disas.c @@ -1765,6 +1765,23 @@ INSN_LASX(xvssub_hu, vvv) INSN_LASX(xvssub_wu, vvv) INSN_LASX(xvssub_du, vvv) =20 +INSN_LASX(xvhaddw_h_b, vvv) +INSN_LASX(xvhaddw_w_h, vvv) +INSN_LASX(xvhaddw_d_w, vvv) +INSN_LASX(xvhaddw_q_d, vvv) +INSN_LASX(xvhaddw_hu_bu, vvv) +INSN_LASX(xvhaddw_wu_hu, vvv) +INSN_LASX(xvhaddw_du_wu, vvv) +INSN_LASX(xvhaddw_qu_du, vvv) +INSN_LASX(xvhsubw_h_b, vvv) +INSN_LASX(xvhsubw_w_h, vvv) +INSN_LASX(xvhsubw_d_w, vvv) +INSN_LASX(xvhsubw_q_d, vvv) +INSN_LASX(xvhsubw_hu_bu, vvv) +INSN_LASX(xvhsubw_wu_hu, vvv) +INSN_LASX(xvhsubw_du_wu, vvv) +INSN_LASX(xvhsubw_qu_du, vvv) + INSN_LASX(xvreplgr2vr_b, vr) INSN_LASX(xvreplgr2vr_h, vr) INSN_LASX(xvreplgr2vr_w, vr) diff --git a/target/loongarch/vec_helper.c b/target/loongarch/vec_helper.c index c784f98ab2..2ce0ca41a7 100644 --- a/target/loongarch/vec_helper.c +++ b/target/loongarch/vec_helper.c @@ -13,6 +13,7 @@ #include "internals.h" #include "tcg/tcg.h" #include "vec.h" +#include "tcg/tcg-gvec-desc.h" =20 #define DO_ADD(a, b) (a + b) #define DO_SUB(a, b) (a - b) @@ -25,8 +26,9 @@ void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t = desc) \ VReg *Vj =3D (VReg *)vj; \ VReg *Vk =3D (VReg *)vk; \ typedef __typeof(Vd->E1(0)) TD; \ + int oprsz =3D simd_oprsz(desc); \ \ - for (i =3D 0; i < LSX_LEN/BIT; i++) { \ + for (i =3D 0; i < oprsz / (BIT / 8); i++) { \ Vd->E1(i) =3D DO_OP((TD)Vj->E2(2 * i + 1), (TD)Vk->E2(2 * i)); \ } \ } @@ -37,11 +39,16 @@ DO_ODD_EVEN(vhaddw_d_w, 64, D, W, DO_ADD) =20 void HELPER(vhaddw_q_d)(void *vd, void *vj, void *vk, uint32_t desc) { + int i; VReg *Vd =3D (VReg *)vd; VReg *Vj =3D (VReg *)vj; VReg *Vk =3D (VReg *)vk; + int oprsz =3D simd_oprsz(desc); =20 - Vd->Q(0) =3D int128_add(int128_makes64(Vj->D(1)), int128_makes64(Vk->D= (0))); + for (i =3D 0; i < oprsz / 16 ; i++) { + Vd->Q(i) =3D int128_add(int128_makes64(Vj->D(2 * i + 1)), + int128_makes64(Vk->D(2 * i))); + } } =20 DO_ODD_EVEN(vhsubw_h_b, 16, H, B, DO_SUB) @@ -50,11 +57,16 @@ DO_ODD_EVEN(vhsubw_d_w, 64, D, W, DO_SUB) =20 void HELPER(vhsubw_q_d)(void *vd, void *vj, void *vk, uint32_t desc) { + int i; VReg *Vd =3D (VReg *)vd; VReg *Vj =3D (VReg *)vj; VReg *Vk =3D (VReg *)vk; + int oprsz =3D simd_oprsz(desc); =20 - Vd->Q(0) =3D int128_sub(int128_makes64(Vj->D(1)), int128_makes64(Vk->D= (0))); + for (i =3D 0; i < oprsz / 16; i++) { + Vd->Q(i) =3D int128_sub(int128_makes64(Vj->D(2 * i + 1)), + int128_makes64(Vk->D(2 * i))); + } } =20 DO_ODD_EVEN(vhaddw_hu_bu, 16, UH, UB, DO_ADD) @@ -63,12 +75,16 @@ DO_ODD_EVEN(vhaddw_du_wu, 64, UD, UW, DO_ADD) =20 void HELPER(vhaddw_qu_du)(void *vd, void *vj, void *vk, uint32_t desc) { + int i; VReg *Vd =3D (VReg *)vd; VReg *Vj =3D (VReg *)vj; VReg *Vk =3D (VReg *)vk; + int oprsz =3D simd_oprsz(desc); =20 - Vd->Q(0) =3D int128_add(int128_make64((uint64_t)Vj->D(1)), - int128_make64((uint64_t)Vk->D(0))); + for (i =3D 0; i < oprsz / 16; i ++) { + Vd->Q(i) =3D int128_add(int128_make64(Vj->UD(2 * i + 1)), + int128_make64(Vk->UD(2 * i))); + } } =20 DO_ODD_EVEN(vhsubw_hu_bu, 16, UH, UB, DO_SUB) @@ -77,12 +93,16 @@ DO_ODD_EVEN(vhsubw_du_wu, 64, UD, UW, DO_SUB) =20 void HELPER(vhsubw_qu_du)(void *vd, void *vj, void *vk, uint32_t desc) { + int i; VReg *Vd =3D (VReg *)vd; VReg *Vj =3D (VReg *)vj; VReg *Vk =3D (VReg *)vk; + int oprsz =3D simd_oprsz(desc); =20 - Vd->Q(0) =3D int128_sub(int128_make64((uint64_t)Vj->D(1)), - int128_make64((uint64_t)Vk->D(0))); + for (i =3D 0; i < oprsz / 16; i++) { + Vd->Q(i) =3D int128_sub(int128_make64(Vj->UD(2 * i + 1)), + int128_make64(Vk->UD(2 * i))); + } } =20 #define DO_EVEN(NAME, BIT, E1, E2, DO_OP) \ diff --git a/target/loongarch/insn_trans/trans_vec.c.inc b/target/loongarch= /insn_trans/trans_vec.c.inc index fd18f4cef7..b2bc11fed1 100644 --- a/target/loongarch/insn_trans/trans_vec.c.inc +++ b/target/loongarch/insn_trans/trans_vec.c.inc @@ -113,6 +113,15 @@ static bool gen_vvv(DisasContext *ctx, arg_vvv *a, gen= _helper_gvec_3 *fn) return gen_vvv_vl(ctx, a, 16, fn); } =20 +static bool gen_xxx(DisasContext *ctx, arg_vvv *a, gen_helper_gvec_3 *fn) +{ + if (!check_vec(ctx, 32)) { + return true; + } + + return gen_vvv_vl(ctx, a, 32, fn); +} + static bool gen_vv_ptr_vl(DisasContext *ctx, arg_vv *a, uint32_t oprsz, gen_helper_gvec_2_ptr *fn) { @@ -465,6 +474,23 @@ TRANS(vhsubw_wu_hu, LSX, gen_vvv, gen_helper_vhsubw_wu= _hu) TRANS(vhsubw_du_wu, LSX, gen_vvv, gen_helper_vhsubw_du_wu) TRANS(vhsubw_qu_du, LSX, gen_vvv, gen_helper_vhsubw_qu_du) =20 +TRANS(xvhaddw_h_b, LASX, gen_xxx, gen_helper_vhaddw_h_b) +TRANS(xvhaddw_w_h, LASX, gen_xxx, gen_helper_vhaddw_w_h) +TRANS(xvhaddw_d_w, LASX, gen_xxx, gen_helper_vhaddw_d_w) +TRANS(xvhaddw_q_d, LASX, gen_xxx, gen_helper_vhaddw_q_d) +TRANS(xvhaddw_hu_bu, LASX, gen_xxx, gen_helper_vhaddw_hu_bu) +TRANS(xvhaddw_wu_hu, LASX, gen_xxx, gen_helper_vhaddw_wu_hu) +TRANS(xvhaddw_du_wu, LASX, gen_xxx, gen_helper_vhaddw_du_wu) +TRANS(xvhaddw_qu_du, LASX, gen_xxx, gen_helper_vhaddw_qu_du) +TRANS(xvhsubw_h_b, LASX, gen_xxx, gen_helper_vhsubw_h_b) +TRANS(xvhsubw_w_h, LASX, gen_xxx, gen_helper_vhsubw_w_h) +TRANS(xvhsubw_d_w, LASX, gen_xxx, gen_helper_vhsubw_d_w) +TRANS(xvhsubw_q_d, LASX, gen_xxx, gen_helper_vhsubw_q_d) +TRANS(xvhsubw_hu_bu, LASX, gen_xxx, gen_helper_vhsubw_hu_bu) +TRANS(xvhsubw_wu_hu, LASX, gen_xxx, gen_helper_vhsubw_wu_hu) +TRANS(xvhsubw_du_wu, LASX, gen_xxx, gen_helper_vhsubw_du_wu) +TRANS(xvhsubw_qu_du, LASX, gen_xxx, gen_helper_vhsubw_qu_du) + static void gen_vaddwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec = b) { TCGv_vec t1, t2; --=20 2.39.1