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Thu, 07 Sep 2023 04:09:32 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8CxtPAyhflkVTQhAA--.1614S3; Thu, 07 Sep 2023 16:09:22 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxviMthflkXE1wAA--.31585S11; Thu, 07 Sep 2023 16:09:21 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, maobibo@loongson.cn Subject: [PATCH v5 09/57] target/loongarch: Use gen_helper_gvec_2i for 2OP + imm vector instructions Date: Thu, 7 Sep 2023 16:08:28 +0800 Message-Id: <20230907080916.3974502-10-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230907080916.3974502-1-gaosong@loongson.cn> References: <20230907080916.3974502-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8DxviMthflkXE1wAA--.31585S11 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 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charset="utf-8" Signed-off-by: Song Gao --- target/loongarch/helper.h | 146 +++---- target/loongarch/vec_helper.c | 445 +++++++++----------- target/loongarch/insn_trans/trans_vec.c.inc | 18 +- 3 files changed, 291 insertions(+), 318 deletions(-) diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h index 523591035d..1abd9e1410 100644 --- a/target/loongarch/helper.h +++ b/target/loongarch/helper.h @@ -354,32 +354,32 @@ DEF_HELPER_FLAGS_3(vmsknz_b, TCG_CALL_NO_RWG, void, p= tr, ptr, i32) =20 DEF_HELPER_FLAGS_4(vnori_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) =20 -DEF_HELPER_4(vsllwil_h_b, void, env, i32, i32, i32) -DEF_HELPER_4(vsllwil_w_h, void, env, i32, i32, i32) -DEF_HELPER_4(vsllwil_d_w, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_4(vsllwil_h_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsllwil_w_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsllwil_d_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) DEF_HELPER_FLAGS_3(vextl_q_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_4(vsllwil_hu_bu, void, env, i32, i32, i32) -DEF_HELPER_4(vsllwil_wu_hu, void, env, i32, i32, i32) -DEF_HELPER_4(vsllwil_du_wu, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_4(vsllwil_hu_bu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i3= 2) +DEF_HELPER_FLAGS_4(vsllwil_wu_hu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i3= 2) +DEF_HELPER_FLAGS_4(vsllwil_du_wu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i3= 2) DEF_HELPER_FLAGS_3(vextl_qu_du, TCG_CALL_NO_RWG, void, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_4(vsrlr_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vsrlr_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vsrlr_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vsrlr_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_4(vsrlri_b, void, env, i32, i32, i32) -DEF_HELPER_4(vsrlri_h, void, env, i32, i32, i32) -DEF_HELPER_4(vsrlri_w, void, env, i32, i32, i32) -DEF_HELPER_4(vsrlri_d, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_4(vsrlri_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsrlri_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsrlri_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsrlri_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) =20 DEF_HELPER_FLAGS_4(vsrar_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vsrar_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vsrar_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vsrar_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_4(vsrari_b, void, env, i32, i32, i32) -DEF_HELPER_4(vsrari_h, void, env, i32, i32, i32) -DEF_HELPER_4(vsrari_w, void, env, i32, i32, i32) -DEF_HELPER_4(vsrari_d, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_4(vsrari_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsrari_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsrari_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsrari_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) =20 DEF_HELPER_FLAGS_4(vsrln_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vsrln_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) @@ -388,14 +388,14 @@ DEF_HELPER_FLAGS_4(vsran_b_h, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vsran_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vsran_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 -DEF_HELPER_4(vsrlni_b_h, void, env, i32, i32, i32) -DEF_HELPER_4(vsrlni_h_w, void, env, i32, i32, i32) -DEF_HELPER_4(vsrlni_w_d, void, env, i32, i32, i32) -DEF_HELPER_4(vsrlni_d_q, void, env, i32, i32, i32) -DEF_HELPER_4(vsrani_b_h, void, env, i32, i32, i32) -DEF_HELPER_4(vsrani_h_w, void, env, i32, i32, i32) -DEF_HELPER_4(vsrani_w_d, void, env, i32, i32, i32) -DEF_HELPER_4(vsrani_d_q, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_4(vsrlni_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsrlni_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsrlni_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsrlni_d_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsrani_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsrani_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsrani_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsrani_d_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) =20 DEF_HELPER_FLAGS_4(vsrlrn_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vsrlrn_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) @@ -404,14 +404,14 @@ DEF_HELPER_FLAGS_4(vsrarn_b_h, TCG_CALL_NO_RWG, void,= ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vsrarn_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vsrarn_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 -DEF_HELPER_4(vsrlrni_b_h, void, env, i32, i32, i32) -DEF_HELPER_4(vsrlrni_h_w, void, env, i32, i32, i32) -DEF_HELPER_4(vsrlrni_w_d, void, env, i32, i32, i32) -DEF_HELPER_4(vsrlrni_d_q, void, env, i32, i32, i32) -DEF_HELPER_4(vsrarni_b_h, void, env, i32, i32, i32) -DEF_HELPER_4(vsrarni_h_w, void, env, i32, i32, i32) -DEF_HELPER_4(vsrarni_w_d, void, env, i32, i32, i32) -DEF_HELPER_4(vsrarni_d_q, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_4(vsrlrni_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsrlrni_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsrlrni_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsrlrni_d_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsrarni_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsrarni_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsrarni_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsrarni_d_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) =20 DEF_HELPER_FLAGS_4(vssrln_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vssrln_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) @@ -426,22 +426,22 @@ DEF_HELPER_FLAGS_4(vssran_bu_h, TCG_CALL_NO_RWG, void= , ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vssran_hu_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vssran_wu_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 -DEF_HELPER_4(vssrlni_b_h, void, env, i32, i32, i32) -DEF_HELPER_4(vssrlni_h_w, void, env, i32, i32, i32) -DEF_HELPER_4(vssrlni_w_d, void, env, i32, i32, i32) -DEF_HELPER_4(vssrlni_d_q, void, env, i32, i32, i32) -DEF_HELPER_4(vssrani_b_h, void, env, i32, i32, i32) -DEF_HELPER_4(vssrani_h_w, void, env, i32, i32, i32) -DEF_HELPER_4(vssrani_w_d, void, env, i32, i32, i32) -DEF_HELPER_4(vssrani_d_q, void, env, i32, i32, i32) -DEF_HELPER_4(vssrlni_bu_h, void, env, i32, i32, i32) -DEF_HELPER_4(vssrlni_hu_w, void, env, i32, i32, i32) -DEF_HELPER_4(vssrlni_wu_d, void, env, i32, i32, i32) -DEF_HELPER_4(vssrlni_du_q, void, env, i32, i32, i32) -DEF_HELPER_4(vssrani_bu_h, void, env, i32, i32, i32) -DEF_HELPER_4(vssrani_hu_w, void, env, i32, i32, i32) -DEF_HELPER_4(vssrani_wu_d, void, env, i32, i32, i32) -DEF_HELPER_4(vssrani_du_q, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_4(vssrlni_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrlni_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrlni_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrlni_d_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrani_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrani_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrani_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrani_d_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrlni_bu_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrlni_hu_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrlni_wu_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrlni_du_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrani_bu_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrani_hu_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrani_wu_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrani_du_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) =20 DEF_HELPER_FLAGS_4(vssrlrn_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vssrlrn_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) @@ -456,22 +456,22 @@ DEF_HELPER_FLAGS_4(vssrarn_bu_h, TCG_CALL_NO_RWG, voi= d, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vssrarn_hu_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vssrarn_wu_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 -DEF_HELPER_4(vssrlrni_b_h, void, env, i32, i32, i32) -DEF_HELPER_4(vssrlrni_h_w, void, env, i32, i32, i32) -DEF_HELPER_4(vssrlrni_w_d, void, env, i32, i32, i32) -DEF_HELPER_4(vssrlrni_d_q, void, env, i32, i32, i32) -DEF_HELPER_4(vssrarni_b_h, void, env, i32, i32, i32) -DEF_HELPER_4(vssrarni_h_w, void, env, i32, i32, i32) -DEF_HELPER_4(vssrarni_w_d, void, env, i32, i32, i32) -DEF_HELPER_4(vssrarni_d_q, void, env, i32, i32, i32) -DEF_HELPER_4(vssrlrni_bu_h, void, env, i32, i32, i32) -DEF_HELPER_4(vssrlrni_hu_w, void, env, i32, i32, i32) -DEF_HELPER_4(vssrlrni_wu_d, void, env, i32, i32, i32) -DEF_HELPER_4(vssrlrni_du_q, void, env, i32, i32, i32) -DEF_HELPER_4(vssrarni_bu_h, void, env, i32, i32, i32) -DEF_HELPER_4(vssrarni_hu_w, void, env, i32, i32, i32) -DEF_HELPER_4(vssrarni_wu_d, void, env, i32, i32, i32) -DEF_HELPER_4(vssrarni_du_q, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_4(vssrlrni_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrlrni_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrlrni_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrlrni_d_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrarni_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrarni_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrarni_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrarni_d_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vssrlrni_bu_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i3= 2) +DEF_HELPER_FLAGS_4(vssrlrni_hu_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i3= 2) +DEF_HELPER_FLAGS_4(vssrlrni_wu_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i3= 2) +DEF_HELPER_FLAGS_4(vssrlrni_du_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i3= 2) +DEF_HELPER_FLAGS_4(vssrarni_bu_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i3= 2) +DEF_HELPER_FLAGS_4(vssrarni_hu_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i3= 2) +DEF_HELPER_FLAGS_4(vssrarni_wu_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i3= 2) +DEF_HELPER_FLAGS_4(vssrarni_du_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i3= 2) =20 DEF_HELPER_FLAGS_3(vclo_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(vclo_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) @@ -516,8 +516,8 @@ DEF_HELPER_FLAGS_4(vbitrevi_d, TCG_CALL_NO_RWG, void, p= tr, ptr, i64, i32) =20 DEF_HELPER_FLAGS_4(vfrstp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vfrstp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_4(vfrstpi_b, void, env, i32, i32, i32) -DEF_HELPER_4(vfrstpi_h, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_4(vfrstpi_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vfrstpi_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) =20 DEF_HELPER_FLAGS_5(vfadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) DEF_HELPER_FLAGS_5(vfadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) @@ -686,14 +686,14 @@ DEF_HELPER_FLAGS_5(vshuf_b, TCG_CALL_NO_RWG, void, pt= r, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vshuf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vshuf_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(vshuf_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_4(vshuf4i_b, void, env, i32, i32, i32) -DEF_HELPER_4(vshuf4i_h, void, env, i32, i32, i32) -DEF_HELPER_4(vshuf4i_w, void, env, i32, i32, i32) -DEF_HELPER_4(vshuf4i_d, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_4(vshuf4i_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vshuf4i_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vshuf4i_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vshuf4i_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) =20 -DEF_HELPER_4(vpermi_w, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_4(vpermi_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) =20 -DEF_HELPER_4(vextrins_b, void, env, i32, i32, i32) -DEF_HELPER_4(vextrins_h, void, env, i32, i32, i32) -DEF_HELPER_4(vextrins_w, void, env, i32, i32, i32) -DEF_HELPER_4(vextrins_d, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_4(vextrins_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vextrins_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vextrins_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vextrins_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) diff --git a/target/loongarch/vec_helper.c b/target/loongarch/vec_helper.c index fd38b47c28..4e10957b90 100644 --- a/target/loongarch/vec_helper.c +++ b/target/loongarch/vec_helper.c @@ -791,22 +791,21 @@ void HELPER(vnori_b)(void *vd, void *vj, uint64_t imm= , uint32_t v) } } =20 -#define VSLLWIL(NAME, BIT, E1, E2) \ -void HELPER(NAME)(CPULoongArchState *env, \ - uint32_t vd, uint32_t vj, uint32_t imm) \ -{ \ - int i; \ - VReg temp; \ - VReg *Vd =3D &(env->fpr[vd].vreg); \ - VReg *Vj =3D &(env->fpr[vj].vreg); \ - typedef __typeof(temp.E1(0)) TD; \ - \ - temp.D(0) =3D 0; \ - temp.D(1) =3D 0; \ - for (i =3D 0; i < LSX_LEN/BIT; i++) { \ - temp.E1(i) =3D (TD)Vj->E2(i) << (imm % BIT); \ - } \ - *Vd =3D temp; \ +#define VSLLWIL(NAME, BIT, E1, E2) \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \ +{ \ + int i; \ + VReg temp; \ + VReg *Vd =3D (VReg *)vd; \ + VReg *Vj =3D (VReg *)vj; \ + typedef __typeof(temp.E1(0)) TD; \ + \ + temp.D(0) =3D 0; \ + temp.D(1) =3D 0; \ + for (i =3D 0; i < LSX_LEN/BIT; i++) { \ + temp.E1(i) =3D (TD)Vj->E2(i) << (imm % BIT); \ + } \ + *Vd =3D temp; \ } =20 void HELPER(vextl_q_d)(void *vd, void *vj, uint32_t desc) @@ -865,17 +864,16 @@ VSRLR(vsrlr_h, 16, uint16_t, H) VSRLR(vsrlr_w, 32, uint32_t, W) VSRLR(vsrlr_d, 64, uint64_t, D) =20 -#define VSRLRI(NAME, BIT, E) \ -void HELPER(NAME)(CPULoongArchState *env, \ - uint32_t vd, uint32_t vj, uint32_t imm) \ -{ \ - int i; \ - VReg *Vd =3D &(env->fpr[vd].vreg); \ - VReg *Vj =3D &(env->fpr[vj].vreg); \ - \ - for (i =3D 0; i < LSX_LEN/BIT; i++) { \ - Vd->E(i) =3D do_vsrlr_ ## E(Vj->E(i), imm); \ - } \ +#define VSRLRI(NAME, BIT, E) \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \ +{ \ + int i; \ + VReg *Vd =3D (VReg *)vd; \ + VReg *Vj =3D (VReg *)vj; \ + \ + for (i =3D 0; i < LSX_LEN/BIT; i++) { \ + Vd->E(i) =3D do_vsrlr_ ## E(Vj->E(i), imm); \ + } \ } =20 VSRLRI(vsrlri_b, 8, B) @@ -916,17 +914,16 @@ VSRAR(vsrar_h, 16, uint16_t, H) VSRAR(vsrar_w, 32, uint32_t, W) VSRAR(vsrar_d, 64, uint64_t, D) =20 -#define VSRARI(NAME, BIT, E) \ -void HELPER(NAME)(CPULoongArchState *env, \ - uint32_t vd, uint32_t vj, uint32_t imm) \ -{ \ - int i; \ - VReg *Vd =3D &(env->fpr[vd].vreg); \ - VReg *Vj =3D &(env->fpr[vj].vreg); \ - \ - for (i =3D 0; i < LSX_LEN/BIT; i++) { \ - Vd->E(i) =3D do_vsrar_ ## E(Vj->E(i), imm); \ - } \ +#define VSRARI(NAME, BIT, E) \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \ +{ \ + int i; \ + VReg *Vd =3D (VReg *)vd; \ + VReg *Vj =3D (VReg *)vj; \ + \ + for (i =3D 0; i < LSX_LEN/BIT; i++) { \ + Vd->E(i) =3D do_vsrar_ ## E(Vj->E(i), imm); \ + } \ } =20 VSRARI(vsrari_b, 8, B) @@ -972,31 +969,29 @@ VSRAN(vsran_b_h, 16, uint16_t, B, H) VSRAN(vsran_h_w, 32, uint32_t, H, W) VSRAN(vsran_w_d, 64, uint64_t, W, D) =20 -#define VSRLNI(NAME, BIT, T, E1, E2) \ -void HELPER(NAME)(CPULoongArchState *env, \ - uint32_t vd, uint32_t vj, uint32_t imm) \ -{ \ - int i, max; \ - VReg temp; \ - VReg *Vd =3D &(env->fpr[vd].vreg); \ - VReg *Vj =3D &(env->fpr[vj].vreg); \ - \ - temp.D(0) =3D 0; \ - temp.D(1) =3D 0; \ - max =3D LSX_LEN/BIT; \ - for (i =3D 0; i < max; i++) { \ - temp.E1(i) =3D R_SHIFT((T)Vj->E2(i), imm); \ - temp.E1(i + max) =3D R_SHIFT((T)Vd->E2(i), imm); \ - } \ - *Vd =3D temp; \ -} - -void HELPER(vsrlni_d_q)(CPULoongArchState *env, - uint32_t vd, uint32_t vj, uint32_t imm) +#define VSRLNI(NAME, BIT, T, E1, E2) \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \ +{ \ + int i, max; \ + VReg temp; \ + VReg *Vd =3D (VReg *)vd; \ + VReg *Vj =3D (VReg *)vj; \ + \ + temp.D(0) =3D 0; \ + temp.D(1) =3D 0; \ + max =3D LSX_LEN/BIT; \ + for (i =3D 0; i < max; i++) { \ + temp.E1(i) =3D R_SHIFT((T)Vj->E2(i), imm); \ + temp.E1(i + max) =3D R_SHIFT((T)Vd->E2(i), imm); \ + } \ + *Vd =3D temp; \ +} + +void HELPER(vsrlni_d_q)(void *vd, void *vj, uint64_t imm, uint32_t desc) { VReg temp; - VReg *Vd =3D &(env->fpr[vd].vreg); - VReg *Vj =3D &(env->fpr[vj].vreg); + VReg *Vd =3D (VReg *)vd; + VReg *Vj =3D (VReg *)vj; =20 temp.D(0) =3D 0; temp.D(1) =3D 0; @@ -1009,31 +1004,29 @@ VSRLNI(vsrlni_b_h, 16, uint16_t, B, H) VSRLNI(vsrlni_h_w, 32, uint32_t, H, W) VSRLNI(vsrlni_w_d, 64, uint64_t, W, D) =20 -#define VSRANI(NAME, BIT, E1, E2) \ -void HELPER(NAME)(CPULoongArchState *env, \ - uint32_t vd, uint32_t vj, uint32_t imm) \ -{ \ - int i, max; \ - VReg temp; \ - VReg *Vd =3D &(env->fpr[vd].vreg); \ - VReg *Vj =3D &(env->fpr[vj].vreg); \ - \ - temp.D(0) =3D 0; \ - temp.D(1) =3D 0; \ - max =3D LSX_LEN/BIT; \ - for (i =3D 0; i < max; i++) { \ - temp.E1(i) =3D R_SHIFT(Vj->E2(i), imm); \ - temp.E1(i + max) =3D R_SHIFT(Vd->E2(i), imm); \ - } \ - *Vd =3D temp; \ -} - -void HELPER(vsrani_d_q)(CPULoongArchState *env, - uint32_t vd, uint32_t vj, uint32_t imm) +#define VSRANI(NAME, BIT, E1, E2) \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \ +{ \ + int i, max; \ + VReg temp; \ + VReg *Vd =3D (VReg *)vd; \ + VReg *Vj =3D (VReg *)vj; \ + \ + temp.D(0) =3D 0; \ + temp.D(1) =3D 0; \ + max =3D LSX_LEN/BIT; \ + for (i =3D 0; i < max; i++) { \ + temp.E1(i) =3D R_SHIFT(Vj->E2(i), imm); \ + temp.E1(i + max) =3D R_SHIFT(Vd->E2(i), imm); \ + } \ + *Vd =3D temp; \ +} + +void HELPER(vsrani_d_q)(void *vd, void *vj, uint64_t imm, uint32_t desc) { VReg temp; - VReg *Vd =3D &(env->fpr[vd].vreg); - VReg *Vj =3D &(env->fpr[vj].vreg); + VReg *Vd =3D (VReg *)vd; + VReg *Vj =3D (VReg *)vj; =20 temp.D(0) =3D 0; temp.D(1) =3D 0; @@ -1082,31 +1075,29 @@ VSRARN(vsrarn_b_h, 16, uint8_t, B, H) VSRARN(vsrarn_h_w, 32, uint16_t, H, W) VSRARN(vsrarn_w_d, 64, uint32_t, W, D) =20 -#define VSRLRNI(NAME, BIT, E1, E2) \ -void HELPER(NAME)(CPULoongArchState *env, \ - uint32_t vd, uint32_t vj, uint32_t imm) \ -{ \ - int i, max; \ - VReg temp; \ - VReg *Vd =3D &(env->fpr[vd].vreg); \ - VReg *Vj =3D &(env->fpr[vj].vreg); \ - \ - temp.D(0) =3D 0; \ - temp.D(1) =3D 0; \ - max =3D LSX_LEN/BIT; \ - for (i =3D 0; i < max; i++) { \ - temp.E1(i) =3D do_vsrlr_ ## E2(Vj->E2(i), imm); \ - temp.E1(i + max) =3D do_vsrlr_ ## E2(Vd->E2(i), imm); \ - } \ - *Vd =3D temp; \ -} - -void HELPER(vsrlrni_d_q)(CPULoongArchState *env, - uint32_t vd, uint32_t vj, uint32_t imm) +#define VSRLRNI(NAME, BIT, E1, E2) \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \ +{ \ + int i, max; \ + VReg temp; \ + VReg *Vd =3D (VReg *)vd; \ + VReg *Vj =3D (VReg *)vj; \ + \ + temp.D(0) =3D 0; \ + temp.D(1) =3D 0; \ + max =3D LSX_LEN/BIT; \ + for (i =3D 0; i < max; i++) { \ + temp.E1(i) =3D do_vsrlr_ ## E2(Vj->E2(i), imm); \ + temp.E1(i + max) =3D do_vsrlr_ ## E2(Vd->E2(i), imm); \ + } \ + *Vd =3D temp; \ +} + +void HELPER(vsrlrni_d_q)(void *vd, void *vj, uint64_t imm, uint32_t desc) { VReg temp; - VReg *Vd =3D &(env->fpr[vd].vreg); - VReg *Vj =3D &(env->fpr[vj].vreg); + VReg *Vd =3D (VReg *)vd; + VReg *Vj =3D (VReg *)vj; Int128 r1, r2; =20 if (imm =3D=3D 0) { @@ -1126,31 +1117,29 @@ VSRLRNI(vsrlrni_b_h, 16, B, H) VSRLRNI(vsrlrni_h_w, 32, H, W) VSRLRNI(vsrlrni_w_d, 64, W, D) =20 -#define VSRARNI(NAME, BIT, E1, E2) \ -void HELPER(NAME)(CPULoongArchState *env, \ - uint32_t vd, uint32_t vj, uint32_t imm) \ -{ \ - int i, max; \ - VReg temp; \ - VReg *Vd =3D &(env->fpr[vd].vreg); \ - VReg *Vj =3D &(env->fpr[vj].vreg); \ - \ - temp.D(0) =3D 0; \ - temp.D(1) =3D 0; \ - max =3D LSX_LEN/BIT; \ - for (i =3D 0; i < max; i++) { \ - temp.E1(i) =3D do_vsrar_ ## E2(Vj->E2(i), imm); \ - temp.E1(i + max) =3D do_vsrar_ ## E2(Vd->E2(i), imm); \ - } \ - *Vd =3D temp; \ -} - -void HELPER(vsrarni_d_q)(CPULoongArchState *env, - uint32_t vd, uint32_t vj, uint32_t imm) +#define VSRARNI(NAME, BIT, E1, E2) \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \ +{ \ + int i, max; \ + VReg temp; \ + VReg *Vd =3D (VReg *)vd; \ + VReg *Vj =3D (VReg *)vj; \ + \ + temp.D(0) =3D 0; \ + temp.D(1) =3D 0; \ + max =3D LSX_LEN/BIT; \ + for (i =3D 0; i < max; i++) { \ + temp.E1(i) =3D do_vsrar_ ## E2(Vj->E2(i), imm); \ + temp.E1(i + max) =3D do_vsrar_ ## E2(Vd->E2(i), imm); \ + } \ + *Vd =3D temp; \ +} + +void HELPER(vsrarni_d_q)(void *vd, void *vj, uint64_t imm, uint32_t desc) { VReg temp; - VReg *Vd =3D &(env->fpr[vd].vreg); - VReg *Vj =3D &(env->fpr[vj].vreg); + VReg *Vd =3D (VReg *)vd; + VReg *Vj =3D (VReg *)vj; Int128 r1, r2; =20 if (imm =3D=3D 0) { @@ -1336,13 +1325,12 @@ VSSRANU(vssran_hu_w, 32, uint32_t, H, W) VSSRANU(vssran_wu_d, 64, uint64_t, W, D) =20 #define VSSRLNI(NAME, BIT, E1, E2) = \ -void HELPER(NAME)(CPULoongArchState *env, = \ - uint32_t vd, uint32_t vj, uint32_t imm) = \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) = \ { = \ int i; = \ VReg temp; = \ - VReg *Vd =3D &(env->fpr[vd].vreg); = \ - VReg *Vj =3D &(env->fpr[vj].vreg); = \ + VReg *Vd =3D (VReg *)vd; = \ + VReg *Vj =3D (VReg *)vj; = \ = \ for (i =3D 0; i < LSX_LEN/BIT; i++) { = \ temp.E1(i) =3D do_ssrlns_ ## E1(Vj->E2(i), imm, BIT/2 -1); = \ @@ -1351,12 +1339,11 @@ void HELPER(NAME)(CPULoongArchState *env, = \ *Vd =3D temp; = \ } =20 -void HELPER(vssrlni_d_q)(CPULoongArchState *env, - uint32_t vd, uint32_t vj, uint32_t imm) +void HELPER(vssrlni_d_q)(void *vd, void *vj, uint64_t imm, uint32_t desc) { Int128 shft_res1, shft_res2, mask; - VReg *Vd =3D &(env->fpr[vd].vreg); - VReg *Vj =3D &(env->fpr[vj].vreg); + VReg *Vd =3D (VReg *)vd; + VReg *Vj =3D (VReg *)vj; =20 if (imm =3D=3D 0) { shft_res1 =3D Vj->Q(0); @@ -1385,13 +1372,12 @@ VSSRLNI(vssrlni_h_w, 32, H, W) VSSRLNI(vssrlni_w_d, 64, W, D) =20 #define VSSRANI(NAME, BIT, E1, E2) = \ -void HELPER(NAME)(CPULoongArchState *env, = \ - uint32_t vd, uint32_t vj, uint32_t imm) = \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) = \ { = \ int i; = \ VReg temp; = \ - VReg *Vd =3D &(env->fpr[vd].vreg); = \ - VReg *Vj =3D &(env->fpr[vj].vreg); = \ + VReg *Vd =3D (VReg *)vd; = \ + VReg *Vj =3D (VReg *)vj; = \ = \ for (i =3D 0; i < LSX_LEN/BIT; i++) { = \ temp.E1(i) =3D do_ssrans_ ## E1(Vj->E2(i), imm, BIT/2 -1); = \ @@ -1400,12 +1386,11 @@ void HELPER(NAME)(CPULoongArchState *env, = \ *Vd =3D temp; = \ } =20 -void HELPER(vssrani_d_q)(CPULoongArchState *env, - uint32_t vd, uint32_t vj, uint32_t imm) +void HELPER(vssrani_d_q)(void *vd, void *vj, uint64_t imm, uint32_t desc) { Int128 shft_res1, shft_res2, mask, min; - VReg *Vd =3D &(env->fpr[vd].vreg); - VReg *Vj =3D &(env->fpr[vj].vreg); + VReg *Vd =3D (VReg *)vd; + VReg *Vj =3D (VReg *)vj; =20 if (imm =3D=3D 0) { shft_res1 =3D Vj->Q(0); @@ -1439,13 +1424,12 @@ VSSRANI(vssrani_h_w, 32, H, W) VSSRANI(vssrani_w_d, 64, W, D) =20 #define VSSRLNUI(NAME, BIT, E1, E2) = \ -void HELPER(NAME)(CPULoongArchState *env, = \ - uint32_t vd, uint32_t vj, uint32_t imm) = \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) = \ { = \ int i; = \ VReg temp; = \ - VReg *Vd =3D &(env->fpr[vd].vreg); = \ - VReg *Vj =3D &(env->fpr[vj].vreg); = \ + VReg *Vd =3D (VReg *)vd; = \ + VReg *Vj =3D (VReg *)vj; = \ = \ for (i =3D 0; i < LSX_LEN/BIT; i++) { = \ temp.E1(i) =3D do_ssrlnu_ ## E1(Vj->E2(i), imm, BIT/2); = \ @@ -1454,12 +1438,11 @@ void HELPER(NAME)(CPULoongArchState *env, = \ *Vd =3D temp; = \ } =20 -void HELPER(vssrlni_du_q)(CPULoongArchState *env, - uint32_t vd, uint32_t vj, uint32_t imm) +void HELPER(vssrlni_du_q)(void *vd, void *vj, uint64_t imm, uint32_t desc) { Int128 shft_res1, shft_res2, mask; - VReg *Vd =3D &(env->fpr[vd].vreg); - VReg *Vj =3D &(env->fpr[vj].vreg); + VReg *Vd =3D (VReg *)vd; + VReg *Vj =3D (VReg *)vj; =20 if (imm =3D=3D 0) { shft_res1 =3D Vj->Q(0); @@ -1488,13 +1471,12 @@ VSSRLNUI(vssrlni_hu_w, 32, H, W) VSSRLNUI(vssrlni_wu_d, 64, W, D) =20 #define VSSRANUI(NAME, BIT, E1, E2) = \ -void HELPER(NAME)(CPULoongArchState *env, = \ - uint32_t vd, uint32_t vj, uint32_t imm) = \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) = \ { = \ int i; = \ VReg temp; = \ - VReg *Vd =3D &(env->fpr[vd].vreg); = \ - VReg *Vj =3D &(env->fpr[vj].vreg); = \ + VReg *Vd =3D (VReg *)vd; = \ + VReg *Vj =3D (VReg *)vj; = \ = \ for (i =3D 0; i < LSX_LEN/BIT; i++) { = \ temp.E1(i) =3D do_ssranu_ ## E1(Vj->E2(i), imm, BIT/2); = \ @@ -1503,12 +1485,11 @@ void HELPER(NAME)(CPULoongArchState *env, = \ *Vd =3D temp; = \ } =20 -void HELPER(vssrani_du_q)(CPULoongArchState *env, - uint32_t vd, uint32_t vj, uint32_t imm) +void HELPER(vssrani_du_q)(void *vd, void *vj, uint64_t imm, uint32_t desc) { Int128 shft_res1, shft_res2, mask; - VReg *Vd =3D &(env->fpr[vd].vreg); - VReg *Vj =3D &(env->fpr[vj].vreg); + VReg *Vd =3D (VReg *)vd; + VReg *Vj =3D (VReg *)vj; =20 if (imm =3D=3D 0) { shft_res1 =3D Vj->Q(0); @@ -1701,13 +1682,12 @@ VSSRARNU(vssrarn_hu_w, 32, uint32_t, H, W) VSSRARNU(vssrarn_wu_d, 64, uint64_t, W, D) =20 #define VSSRLRNI(NAME, BIT, E1, E2) = \ -void HELPER(NAME)(CPULoongArchState *env, = \ - uint32_t vd, uint32_t vj, uint32_t imm) = \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) = \ { = \ int i; = \ VReg temp; = \ - VReg *Vd =3D &(env->fpr[vd].vreg); = \ - VReg *Vj =3D &(env->fpr[vj].vreg); = \ + VReg *Vd =3D (VReg *)vd; = \ + VReg *Vj =3D (VReg *)vj; = \ = \ for (i =3D 0; i < LSX_LEN/BIT; i++) { = \ temp.E1(i) =3D do_ssrlrns_ ## E1(Vj->E2(i), imm, BIT/2 -1); = \ @@ -1717,12 +1697,11 @@ void HELPER(NAME)(CPULoongArchState *env, = \ } =20 #define VSSRLRNI_Q(NAME, sh) = \ -void HELPER(NAME)(CPULoongArchState *env, = \ - uint32_t vd, uint32_t vj, uint32_t imm) = \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) = \ { = \ Int128 shft_res1, shft_res2, mask, r1, r2; = \ - VReg *Vd =3D &(env->fpr[vd].vreg); = \ - VReg *Vj =3D &(env->fpr[vj].vreg); = \ + VReg *Vd =3D (VReg *)vd; = \ + VReg *Vj =3D (VReg *)vj; = \ = \ if (imm =3D=3D 0) { = \ shft_res1 =3D Vj->Q(0); = \ @@ -1756,13 +1735,12 @@ VSSRLRNI(vssrlrni_w_d, 64, W, D) VSSRLRNI_Q(vssrlrni_d_q, 63) =20 #define VSSRARNI(NAME, BIT, E1, E2) = \ -void HELPER(NAME)(CPULoongArchState *env, = \ - uint32_t vd, uint32_t vj, uint32_t imm) = \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) = \ { = \ int i; = \ VReg temp; = \ - VReg *Vd =3D &(env->fpr[vd].vreg); = \ - VReg *Vj =3D &(env->fpr[vj].vreg); = \ + VReg *Vd =3D (VReg *)vd; = \ + VReg *Vj =3D (VReg *)vj; = \ = \ for (i =3D 0; i < LSX_LEN/BIT; i++) { = \ temp.E1(i) =3D do_ssrarns_ ## E1(Vj->E2(i), imm, BIT/2 -1); = \ @@ -1771,12 +1749,11 @@ void HELPER(NAME)(CPULoongArchState *env, *Vd =3D temp; = \ } =20 -void HELPER(vssrarni_d_q)(CPULoongArchState *env, - uint32_t vd, uint32_t vj, uint32_t imm) +void HELPER(vssrarni_d_q)(void *vd, void *vj, uint64_t imm, uint32_t desc) { Int128 shft_res1, shft_res2, mask1, mask2, r1, r2; - VReg *Vd =3D &(env->fpr[vd].vreg); - VReg *Vj =3D &(env->fpr[vj].vreg); + VReg *Vd =3D (VReg *)vd; + VReg *Vj =3D (VReg *)vj; =20 if (imm =3D=3D 0) { shft_res1 =3D Vj->Q(0); @@ -1814,13 +1791,12 @@ VSSRARNI(vssrarni_h_w, 32, H, W) VSSRARNI(vssrarni_w_d, 64, W, D) =20 #define VSSRLRNUI(NAME, BIT, E1, E2) = \ -void HELPER(NAME)(CPULoongArchState *env, = \ - uint32_t vd, uint32_t vj, uint32_t imm) = \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) = \ { = \ int i; = \ VReg temp; = \ - VReg *Vd =3D &(env->fpr[vd].vreg); = \ - VReg *Vj =3D &(env->fpr[vj].vreg); = \ + VReg *Vd =3D (VReg *)vd; = \ + VReg *Vj =3D (VReg *)vj; = \ = \ for (i =3D 0; i < LSX_LEN/BIT; i++) { = \ temp.E1(i) =3D do_ssrlrnu_ ## E1(Vj->E2(i), imm, BIT/2); = \ @@ -1835,13 +1811,12 @@ VSSRLRNUI(vssrlrni_wu_d, 64, W, D) VSSRLRNI_Q(vssrlrni_du_q, 64) =20 #define VSSRARNUI(NAME, BIT, E1, E2) = \ -void HELPER(NAME)(CPULoongArchState *env, = \ - uint32_t vd, uint32_t vj, uint32_t imm) = \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) = \ { = \ int i; = \ VReg temp; = \ - VReg *Vd =3D &(env->fpr[vd].vreg); = \ - VReg *Vj =3D &(env->fpr[vj].vreg); = \ + VReg *Vd =3D (VReg *)vd; = \ + VReg *Vj =3D (VReg *)vj; = \ = \ for (i =3D 0; i < LSX_LEN/BIT; i++) { = \ temp.E1(i) =3D do_ssrarnu_ ## E1(Vj->E2(i), imm, BIT/2); = \ @@ -1850,12 +1825,11 @@ void HELPER(NAME)(CPULoongArchState *env, = \ *Vd =3D temp; = \ } =20 -void HELPER(vssrarni_du_q)(CPULoongArchState *env, - uint32_t vd, uint32_t vj, uint32_t imm) +void HELPER(vssrarni_du_q)(void *vd, void *vj, uint64_t imm, uint32_t desc) { Int128 shft_res1, shft_res2, mask1, mask2, r1, r2; - VReg *Vd =3D &(env->fpr[vd].vreg); - VReg *Vj =3D &(env->fpr[vj].vreg); + VReg *Vd =3D (VReg *)vd; + VReg *Vj =3D (VReg *)vj; =20 if (imm =3D=3D 0) { shft_res1 =3D Vj->Q(0); @@ -2023,21 +1997,20 @@ void HELPER(NAME)(void *vd, void *vj, void *vk, uin= t32_t desc) \ VFRSTP(vfrstp_b, 8, 0xf, B) VFRSTP(vfrstp_h, 16, 0x7, H) =20 -#define VFRSTPI(NAME, BIT, E) \ -void HELPER(NAME)(CPULoongArchState *env, \ - uint32_t vd, uint32_t vj, uint32_t imm) \ -{ \ - int i, m; \ - VReg *Vd =3D &(env->fpr[vd].vreg); \ - VReg *Vj =3D &(env->fpr[vj].vreg); \ - \ - for (i =3D 0; i < LSX_LEN/BIT; i++) { \ - if (Vj->E(i) < 0) { \ - break; \ - } \ - } \ - m =3D imm % (LSX_LEN/BIT); \ - Vd->E(m) =3D i; \ +#define VFRSTPI(NAME, BIT, E) \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \ +{ \ + int i, m; \ + VReg *Vd =3D (VReg *)vd; \ + VReg *Vj =3D (VReg *)vj; \ + \ + for (i =3D 0; i < LSX_LEN/BIT; i++) { \ + if (Vj->E(i) < 0) { \ + break; \ + } \ + } \ + m =3D imm % (LSX_LEN/BIT); \ + Vd->E(m) =3D i; \ } =20 VFRSTPI(vfrstpi_b, 8, B) @@ -2923,31 +2896,29 @@ VSHUF(vshuf_h, 16, H) VSHUF(vshuf_w, 32, W) VSHUF(vshuf_d, 64, D) =20 -#define VSHUF4I(NAME, BIT, E) \ -void HELPER(NAME)(CPULoongArchState *env, \ - uint32_t vd, uint32_t vj, uint32_t imm) \ -{ \ - int i; \ - VReg temp; \ - VReg *Vd =3D &(env->fpr[vd].vreg); \ - VReg *Vj =3D &(env->fpr[vj].vreg); \ - \ - for (i =3D 0; i < LSX_LEN/BIT; i++) { \ - temp.E(i) =3D Vj->E(((i) & 0xfc) + (((imm) >> \ - (2 * ((i) & 0x03))) & 0x03)); \ - } \ - *Vd =3D temp; \ +#define VSHUF4I(NAME, BIT, E) \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \ +{ \ + int i; \ + VReg temp; \ + VReg *Vd =3D (VReg *)vd; \ + VReg *Vj =3D (VReg *)vj; \ + \ + for (i =3D 0; i < LSX_LEN/BIT; i++) { \ + temp.E(i) =3D Vj->E(((i) & 0xfc) + (((imm) >> \ + (2 * ((i) & 0x03))) & 0x03)); \ + } \ + *Vd =3D temp; \ } =20 VSHUF4I(vshuf4i_b, 8, B) VSHUF4I(vshuf4i_h, 16, H) VSHUF4I(vshuf4i_w, 32, W) =20 -void HELPER(vshuf4i_d)(CPULoongArchState *env, - uint32_t vd, uint32_t vj, uint32_t imm) +void HELPER(vshuf4i_d)(void *vd, void *vj, uint64_t imm, uint32_t desc) { - VReg *Vd =3D &(env->fpr[vd].vreg); - VReg *Vj =3D &(env->fpr[vj].vreg); + VReg *Vd =3D (VReg *)vd; + VReg *Vj =3D (VReg *)vj; =20 VReg temp; temp.D(0) =3D (imm & 2 ? Vj : Vd)->D(imm & 1); @@ -2955,12 +2926,11 @@ void HELPER(vshuf4i_d)(CPULoongArchState *env, *Vd =3D temp; } =20 -void HELPER(vpermi_w)(CPULoongArchState *env, - uint32_t vd, uint32_t vj, uint32_t imm) +void HELPER(vpermi_w)(void *vd, void *vj, uint64_t imm, uint32_t desc) { VReg temp; - VReg *Vd =3D &(env->fpr[vd].vreg); - VReg *Vj =3D &(env->fpr[vj].vreg); + VReg *Vd =3D (VReg *)vd; + VReg *Vj =3D (VReg *)vj; =20 temp.W(0) =3D Vj->W(imm & 0x3); temp.W(1) =3D Vj->W((imm >> 2) & 0x3); @@ -2969,17 +2939,16 @@ void HELPER(vpermi_w)(CPULoongArchState *env, *Vd =3D temp; } =20 -#define VEXTRINS(NAME, BIT, E, MASK) \ -void HELPER(NAME)(CPULoongArchState *env, \ - uint32_t vd, uint32_t vj, uint32_t imm) \ -{ \ - int ins, extr; \ - VReg *Vd =3D &(env->fpr[vd].vreg); \ - VReg *Vj =3D &(env->fpr[vj].vreg); \ - \ - ins =3D (imm >> 4) & MASK; \ - extr =3D imm & MASK; \ - Vd->E(ins) =3D Vj->E(extr); \ +#define VEXTRINS(NAME, BIT, E, MASK) \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \ +{ \ + int ins, extr; \ + VReg *Vd =3D (VReg *)vd; \ + VReg *Vj =3D (VReg *)vj; \ + \ + ins =3D (imm >> 4) & MASK; \ + extr =3D imm & MASK; \ + Vd->E(ins) =3D Vj->E(extr); \ } =20 VEXTRINS(vextrins_b, 8, B, 0xf) diff --git a/target/loongarch/insn_trans/trans_vec.c.inc b/target/loongarch= /insn_trans/trans_vec.c.inc index 4c3d206df1..41c2996e90 100644 --- a/target/loongarch/insn_trans/trans_vec.c.inc +++ b/target/loongarch/insn_trans/trans_vec.c.inc @@ -118,16 +118,20 @@ static bool gen_vv(DisasContext *ctx, arg_vv *a, gen_= helper_gvec_2 *fn) return gen_vv_vl(ctx, a, 16, fn); } =20 -static bool gen_vv_i(DisasContext *ctx, arg_vv_i *a, - void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32)) +static bool gen_vv_i_vl(DisasContext *ctx, arg_vv_i *a, uint32_t oprsz, + gen_helper_gvec_2i *fn) { - TCGv_i32 vd =3D tcg_constant_i32(a->vd); - TCGv_i32 vj =3D tcg_constant_i32(a->vj); - TCGv_i32 imm =3D tcg_constant_i32(a->imm); + tcg_gen_gvec_2i_ool(vec_full_offset(a->vd), + vec_full_offset(a->vj), + tcg_constant_i64(a->imm), + oprsz, ctx->vl / 8, oprsz, fn); + return true; +} =20 +static bool gen_vv_i(DisasContext *ctx, arg_vv_i *a, gen_helper_gvec_2i *f= n) +{ CHECK_SXE; - func(cpu_env, vd, vj, imm); - return true; + return gen_vv_i_vl(ctx, a, 16, fn); } =20 static bool gen_cv(DisasContext *ctx, arg_cv *a, --=20 2.39.1