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([177.94.15.194]) by smtp.gmail.com with ESMTPSA id n21-20020a9d6f15000000b006b75242d6c3sm6229228otq.38.2023.09.06.02.17.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 02:17:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693991845; x=1694596645; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g5E9LLyNurxOieuuNS1GPdHvFJKI2dYtdPNFC2nvFyI=; b=R4O3hV5e95MoiAbVvsuiMVN/srlM6xvM+cPRAtZnXbtT/lGwGVf+r/L+gxyCrYYBx8 NFjo0EdnSgNmoCDNcawAusvfVsBjapi4ZqSCGqtD2TtCRpzhvqRJI6M6wk819URR3nPI 8zZvespzo4CQONFPcsvi8so74ReTJlhNbiN7Yiz3e+ITnWFXtcxNRTVBQbxQBMeGUgyn Fq9DlhyOyCbNzQB9NmES8QfF5Zpf+XdvRxLEIiibjonaadQr8vGZGTdZrjlyGQKbVwhj oy9OY2mgtRFoNsscGgkO61eWRrBzOFl1y5Fd1XBiqh9xSwXoLfWPj4dJnXkjJ+y9wNj6 KfJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693991845; x=1694596645; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g5E9LLyNurxOieuuNS1GPdHvFJKI2dYtdPNFC2nvFyI=; b=HoMdBWt0eYYd4weNytiYKoB+2E5mo/3CZN3HT2CPa7+Z0+60ky7YMK6fP9Z/KsxvHu urDIeyT+EoTwQmeQHsMFfjpIgn6KzfDvtx0saEYOkiAEfPq48QPS+Qt3Z/5fvW5f/kVD bNgbpeo/lQn8zp3S4HwaAsqQ4bSJzgZNqYYCir0lU3XU3oOaocWw8+5tkXRJjfoTDSez mj6PI+aosD8YmG/c/Z0/toW/H/CDi+gtjOBb54VeJYXwjxOZ7RfTv1GmeYa7uyCuyOtp dA3NTAjgNVK7asWFMps3wwTdB/ZCJHmqsGytnIGN3duMCjCe2yYXwi5/E2/NJZtHr6ed NMAA== X-Gm-Message-State: AOJu0YzVfC8y/GnTmwsx30c2Tv976IhsJ0/R54b4a6MURmgDYRRn8Ht3 NI7R30fATIPLeqBxqlhhO/PSze6V8ZFOKdncwXc= X-Google-Smtp-Source: AGHT+IHVrzotwCtpzjDsNAyJ6JLgNxIpWI6aqaoPIk8jUysidX88bHXc325peq9uvaWtwqeEoPeIJA== X-Received: by 2002:a9d:6659:0:b0:6bd:7252:9db1 with SMTP id q25-20020a9d6659000000b006bd72529db1mr16592617otm.11.1693991844801; Wed, 06 Sep 2023 02:17:24 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 09/19] target/riscv: make riscv_add_satp_mode_properties() public Date: Wed, 6 Sep 2023 06:16:36 -0300 Message-ID: <20230906091647.1667171-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com> References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1693991898915100001 Content-Type: text/plain; charset="utf-8" This function is used for both accelerators. Make it public, and call it from kvm_riscv_cpu_add_kvm_properties(). This will make it easier to split KVM specific code for the KVM accelerator class in the next patch. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 5 ++--- target/riscv/cpu.h | 1 + target/riscv/kvm.c | 1 + 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0dc9b3201d..50be127f36 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1115,7 +1115,7 @@ static void cpu_riscv_set_satp(Object *obj, Visitor *= v, const char *name, satp_map->init |=3D 1 << satp; } =20 -static void riscv_add_satp_mode_properties(Object *obj) +void riscv_add_satp_mode_properties(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); =20 @@ -1589,12 +1589,11 @@ static void riscv_cpu_add_multiext_prop_array(Objec= t *obj, static void riscv_cpu_add_user_properties(Object *obj) { #ifndef CONFIG_USER_ONLY - riscv_add_satp_mode_properties(obj); - if (kvm_enabled()) { kvm_riscv_cpu_add_kvm_properties(obj); return; } + riscv_add_satp_mode_properties(obj); #endif =20 riscv_cpu_add_misa_properties(obj); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b9c4bea3f7..950c2301f2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -726,6 +726,7 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_experimen= tal_exts[]; extern Property riscv_cpu_options[]; =20 void riscv_cpu_add_misa_properties(Object *cpu_obj); +void riscv_add_satp_mode_properties(Object *obj); =20 /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 7dac01374f..ef6b2cfffe 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -1279,6 +1279,7 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj) DeviceState *dev =3D DEVICE(obj); =20 riscv_init_user_properties(obj); + riscv_add_satp_mode_properties(obj); riscv_cpu_add_misa_properties(obj); =20 riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); --=20 2.41.0