From nobody Thu Nov 28 08:03:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1693991931; cv=none; d=zohomail.com; s=zohoarc; b=IfINbRtq1CCSYP9dLCOpPG0MDdo4LCorXBTeYQiSBEx848j1g8jZ3fhXKLr31W1gtbMBC1z3w2seH7ZM3qyTrlZRU+zMHPr06Ml//q1rbLrHQFlZdu3pH6WY0YobL7eL9mVR4JqR9A6JAPOraqQTAjy/MhijRzYVi35uv5Azee0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693991931; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oFl+a2Kq0b0p8yaPzRI+x2lm+P3JwkJ8h7I1Xdl+LTo=; b=g9peQDt8jkM/8GBE0iW9yVu4niiEVYjR9kFcJXuPebT9d92BU9YoRzYf5e+RMsgfuraYl0RyCIPOFO/2d7/u9jGA1LdlDZnlNxV2H9ZTYJG2a3e+7BKVWT8tfOm7X3+cfufZI0nS23S53V9YWEb7VHvSkVYrF1cD6ytgNjo+maQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693991931138914.2996592524809; Wed, 6 Sep 2023 02:18:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qdoey-0002xp-7y; Wed, 06 Sep 2023 05:17:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qdoen-0002jH-Ba for qemu-devel@nongnu.org; Wed, 06 Sep 2023 05:17:06 -0400 Received: from mail-ot1-x332.google.com ([2607:f8b0:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qdoeh-0005bq-2U for qemu-devel@nongnu.org; Wed, 06 Sep 2023 05:17:03 -0400 Received: by mail-ot1-x332.google.com with SMTP id 46e09a7af769-6bf298ef1f5so2574839a34.0 for ; Wed, 06 Sep 2023 02:16:58 -0700 (PDT) Received: from grind.. ([177.94.15.194]) by smtp.gmail.com with ESMTPSA id n21-20020a9d6f15000000b006b75242d6c3sm6229228otq.38.2023.09.06.02.16.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 02:16:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693991817; x=1694596617; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oFl+a2Kq0b0p8yaPzRI+x2lm+P3JwkJ8h7I1Xdl+LTo=; b=J7fB+XfOUvArqxJLCvWgdG6ruB1fr75AG2yfiJ8RtOYCOhG9AnKsPvrV/07GZFUa+d 1N83cKHTxnkkXaNKxvPMmq+9oZdYX9XxM5Bn57eOmbEvyHhiq42pWz85xYKo/95IQfyS XglBXHHa+pdO6jry8U+cKUeAYCR1PEY2U4peUF2g/MchFcEMFeEKyWN6feIFHF0kNyqw zcOHJdVI8wl8f1HcVOQWP7xkgLj3FYg0FiKGa/KqkBay/BksVpiJx2ItEDNMWDpFI2nU ksvSCwfW3P08DrxjzlSOU+LVfhFce+gugJzB1/3moxf0Su04x9p1yq424dXNlA1lQDlz LQgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693991817; x=1694596617; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oFl+a2Kq0b0p8yaPzRI+x2lm+P3JwkJ8h7I1Xdl+LTo=; b=PtXNqDnztIqFAgK9xiGYf4ch9cPIjlI2/WYG6tXIG4zTNq3tR07LpEUwGAeFqzAuA+ Mkygfyd9qKgi9KO3JE31hN/sw7iO6B7WhnPW1B1hyfTL4LyNgsVZUA0MxGu48vJ90l4r 1pbBdv+hdfyb5tpiRD0sdvMR3O6ReUqbEkKqAijPHoPrDRE70ToCcfk0HkgFTWEB6tX4 ghT28IHAc0Mnpjnxrw5qdK+85LXRyy+pZwiSsxQ2aWwIDGl75CHgzBL+iUP6BpYWO04e Lm/iaut8sYqNctdWddX4kkORGm9wDXvpq75dFYOEaXXyphT/MUVY2K8vfKXKll01D8Hj hgWg== X-Gm-Message-State: AOJu0YyM/lo1Wp8wocg48tX+ogxzxg8AZ9dlzt7igFBPFexhBXQIonTn oFyfkK+ab+KXPl5g8YNajChxhsSl+a/390FksMI= X-Google-Smtp-Source: AGHT+IHhQxV2Lv5ABkIeJa+9VxQYE+0tk6eZltI2ZEs2jyq67O0cJhd87e68kgI9MxVntTxzeg3ilA== X-Received: by 2002:a9d:7486:0:b0:6bf:1444:966d with SMTP id t6-20020a9d7486000000b006bf1444966dmr13991975otk.1.1693991817579; Wed, 06 Sep 2023 02:16:57 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 01/19] target/riscv: introduce TCG AccelCPUClass Date: Wed, 6 Sep 2023 06:16:28 -0300 Message-ID: <20230906091647.1667171-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com> References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1693991932949100003 Content-Type: text/plain; charset="utf-8" target/riscv/cpu.c needs to handle all possible accelerators (TCG and KVM at this moment) during both init() and realize() time. This forces us to resort to a lot of "if tcg" and "if kvm" throughout the code, which isn't wrong, but can get cluttered over time. Splitting acceleration specific code from cpu.c to its own file will help to declutter the existing code and it will also make it easier to support KVM/TCG only builds in the future. We'll start by adding a new subdir called 'tcg' and a new file called 'tcg-cpu.c'. This file will be used to introduce a new accelerator class for TCG acceleration in RISC-V, allowing us to center all TCG exclusive code in its file instead of using 'cpu.c' for everything. This design is inpired by the work Claudio Fontana did in x86 a few years ago in commit f5cc5a5c1 ("i386: split cpu accelerators from cpu.c, using AccelCPUClass"). To avoid moving too much code at once we'll start by adding the new file and TCG AccelCPUClass declaration. The 'class_init' from the accel class will init 'tcg_ops', relieving the common riscv_cpu_class_init() from doing it. 'riscv_tcg_ops' is being exported from 'cpu.c' for now to avoid having to deal with moving code and files around right now. We'll focus on decoupling the realize() logic first. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 5 +--- target/riscv/cpu.h | 4 +++ target/riscv/meson.build | 2 ++ target/riscv/tcg/meson.build | 2 ++ target/riscv/tcg/tcg-cpu.c | 58 ++++++++++++++++++++++++++++++++++++ 5 files changed, 67 insertions(+), 4 deletions(-) create mode 100644 target/riscv/tcg/meson.build create mode 100644 target/riscv/tcg/tcg-cpu.c diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index be1c028095..2c6972fa0d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2290,9 +2290,7 @@ static const struct SysemuCPUOps riscv_sysemu_ops =3D= { }; #endif =20 -#include "hw/core/tcg-cpu-ops.h" - -static const struct TCGCPUOps riscv_tcg_ops =3D { +const struct TCGCPUOps riscv_tcg_ops =3D { .initialize =3D riscv_translate_init, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, .restore_state_to_opc =3D riscv_restore_state_to_opc, @@ -2451,7 +2449,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; - cc->tcg_ops =3D &riscv_tcg_ops; =20 object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, cpu_set_mvendorid, NULL, NULL); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 577abcd724..b84b62f84e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -707,6 +707,10 @@ enum riscv_pmu_event_idx { RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS =3D 0x10021, }; =20 +/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */ +#include "hw/core/tcg-cpu-ops.h" +extern const struct TCGCPUOps riscv_tcg_ops; + /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; =20 diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 660078bda1..f0486183fa 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -38,5 +38,7 @@ riscv_system_ss.add(files( 'riscv-qmp-cmds.c', )) =20 +subdir('tcg') + target_arch +=3D {'riscv': riscv_ss} target_softmmu_arch +=3D {'riscv': riscv_system_ss} diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build new file mode 100644 index 0000000000..061df3d74a --- /dev/null +++ b/target/riscv/tcg/meson.build @@ -0,0 +1,2 @@ +riscv_ss.add(when: 'CONFIG_TCG', if_true: files( + 'tcg-cpu.c')) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c new file mode 100644 index 0000000000..0326cead0d --- /dev/null +++ b/target/riscv/tcg/tcg-cpu.c @@ -0,0 +1,58 @@ +/* + * riscv TCG cpu class initialization + * + * Copyright (c) 2023 Ventana Micro Systems Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "qemu/accel.h" +#include "hw/core/accel-cpu.h" + +static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) +{ + /* + * All cpus use the same set of operations. + * riscv_tcg_ops is being imported from cpu.c for now. + */ + cc->tcg_ops =3D &riscv_tcg_ops; +} + +static void tcg_cpu_class_init(CPUClass *cc) +{ + cc->init_accel_cpu =3D tcg_cpu_init_ops; +} + +static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_class_init =3D tcg_cpu_class_init; +} + +static const TypeInfo tcg_cpu_accel_type_info =3D { + .name =3D ACCEL_CPU_NAME("tcg"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D tcg_cpu_accel_class_init, + .abstract =3D true, +}; + +static void tcg_cpu_accel_register_types(void) +{ + type_register_static(&tcg_cpu_accel_type_info); +} +type_init(tcg_cpu_accel_register_types); --=20 2.41.0 From nobody Thu Nov 28 08:03:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1693991885; cv=none; d=zohomail.com; s=zohoarc; b=bBow8f2YQ7KeKWxD9V0VLfnoLBIbuOb51+2TEk7xiqyF9i7QKmCPzSKs2Lvufw6Q9JjsE3q2tpvpuMY8BN3miwJzKKM0+0VzznItBlH1rhJe+9FnPK/A9RA88c4cXsyKNi5AxNwHDmdgd68SfGu794SOsI/8vEKGHVD2inQcwzk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693991885; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gdwtg7k7ecWU2m8jdUTwhHMZ9nILSouycHYrm1CtkOY=; b=Jr3f6XmHLbo53wetZ11rttcac0+OHN2nSahRWbq1uFd/TTHA5i+lkYOfHqTROHks0TeyGgmjSsE4I4EqAUOn/M1eFmywqlUtQ1htKAg5TQqzWrM760ZvKJaxV5Vl0z/IHOD0gr2mhzibOTR0N4WbXl9DgnNL+MZoYgzRaj6dZV8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169399188546515.676461844195273; Wed, 6 Sep 2023 02:18:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qdoew-0002sj-01; Wed, 06 Sep 2023 05:17:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qdoeo-0002jQ-0Q for qemu-devel@nongnu.org; Wed, 06 Sep 2023 05:17:06 -0400 Received: from mail-ot1-x32a.google.com ([2607:f8b0:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qdoek-0005cH-Nh for qemu-devel@nongnu.org; Wed, 06 Sep 2023 05:17:05 -0400 Received: by mail-ot1-x32a.google.com with SMTP id 46e09a7af769-6bcac140aaaso2690224a34.2 for ; Wed, 06 Sep 2023 02:17:02 -0700 (PDT) Received: from grind.. ([177.94.15.194]) by smtp.gmail.com with ESMTPSA id n21-20020a9d6f15000000b006b75242d6c3sm6229228otq.38.2023.09.06.02.16.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 02:17:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693991821; x=1694596621; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gdwtg7k7ecWU2m8jdUTwhHMZ9nILSouycHYrm1CtkOY=; b=KezWpziCBtU+Vzr5QiT1QobJgh0tPtKKiKaBJdMEXYvWQkOJuY7bS9pioB7QyX7gWH MsH0Hm3Kgf0IxzbPGQnwUgQ4VXzxDtWg7VLBOoH51y3SLlCptOOslzMEZrKtSkkYis8k TzI6D6Tc80Oyo43RL0VdEoii5+LKWEtzSB32uBEtgQRbmZBMcHD4zjNqk/5zEPNzVt9F wl53P2+D51qsSRyOtrOfVmpVuxARJwLwHj21RUK/i9s22/tkWFKrqJzTRwjIO0bUR5vf J8TQ049IBZ/7hBRVf+IEpfVYA/LJQSdMTB6qSQ98dVYI0hEShNBvXhkogXUKapDerboB 1sVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693991821; x=1694596621; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gdwtg7k7ecWU2m8jdUTwhHMZ9nILSouycHYrm1CtkOY=; b=KKYY2QgLxgYotjsSFRQOZW3s1+aUvR7TZZhpYU32z94lBhQ2XAMj3RER0HBNLbzeom T2rtBMFubrEv1UCxZsenf9nMXJoJRG4qmoJF7jqIudGvkWKQIiLuD/dP8fPRjhKieZPp XOevzTHc2NjYxNarmt4GorPAUHXqH+sW9Rb7UKZNWaHcl9b/DH0s/miljxzVl0CHDUCm mDSbUZiTztDtoCs6vVQlPUSdEQDFeO6C10SYpP+/aY3PFegOcqio18z3xoHpSTY9D2hk 7ynDCEZw0GgH7JCmYxe+cSYXGZCVooRStQwiiw4C55L+4mKmO1O08saixt+g0j1crSi7 l8YA== X-Gm-Message-State: AOJu0Yw9zoAPIZ4UjlyIn1Q3u/ylqUBjlsXAC275tW0mXGj+dYMvi3QB CDfdVIaowpF24S5Se9j9lTW7bCN39dsfLmsjgrk= X-Google-Smtp-Source: AGHT+IHqImpK4V4DyJlOmjfP/WW4FXwtC1Rg0Bu9NdyBjtVS1EVOkskTluAams8ty+8qyKooV0u50g== X-Received: by 2002:a9d:7f85:0:b0:6aa:ecb5:f186 with SMTP id t5-20020a9d7f85000000b006aaecb5f186mr18429811otp.7.1693991821423; Wed, 06 Sep 2023 02:17:01 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 02/19] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn() Date: Wed, 6 Sep 2023 06:16:29 -0300 Message-ID: <20230906091647.1667171-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com> References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1693991887438100002 Content-Type: text/plain; charset="utf-8" riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different realize() path during the common riscv_cpu_realize(), making it a good choice to start moving TCG exclusive code to tcg-cpu.c. Rename it to tcg_cpu_realizefn() and assign it as a implementation of accel::cpu_realizefn(). tcg_cpu_realizefn() will then be called during riscv_cpu_realize() via cpu_exec_realizefn(). We'll use a similar approach with KVM in the near future. riscv_cpu_validate_set_extensions() is too big and with too many dependencies to be moved in this same patch. We'll do that next. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 128 ----------------------------------- target/riscv/tcg/tcg-cpu.c | 132 +++++++++++++++++++++++++++++++++++++ 2 files changed, 132 insertions(+), 128 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2c6972fa0d..59785f5d9a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -23,9 +23,7 @@ #include "qemu/log.h" #include "cpu.h" #include "cpu_vendorid.h" -#include "pmu.h" #include "internals.h" -#include "time_helper.h" #include "exec/exec-all.h" #include "qapi/error.h" #include "qapi/visitor.h" @@ -1064,29 +1062,6 @@ static void riscv_cpu_validate_v(CPURISCVState *env,= RISCVCPUConfig *cfg, } } =20 -static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) -{ - CPURISCVState *env =3D &cpu->env; - int priv_version =3D -1; - - if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { - priv_version =3D PRIV_VERSION_1_12_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { - priv_version =3D PRIV_VERSION_1_11_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { - priv_version =3D PRIV_VERSION_1_10_0; - } else { - error_setg(errp, - "Unsupported privilege spec version '%s'", - cpu->cfg.priv_spec); - return; - } - - env->priv_ver =3D priv_version; - } -} - static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) { CPURISCVState *env =3D &cpu->env; @@ -1111,33 +1086,6 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RIS= CVCPU *cpu) } } =20 -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) -{ - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); - CPUClass *cc =3D CPU_CLASS(mcc); - CPURISCVState *env =3D &cpu->env; - - /* Validate that MISA_MXL is set properly. */ - switch (env->misa_mxl_max) { -#ifdef TARGET_RISCV64 - case MXL_RV64: - case MXL_RV128: - cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; - break; -#endif - case MXL_RV32: - cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; - break; - default: - g_assert_not_reached(); - } - - if (env->misa_mxl_max !=3D env->misa_mxl) { - error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); - return; - } -} - /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -1511,74 +1459,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cp= u, Error **errp) #endif } =20 -static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) -{ - if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { - error_setg(errp, "H extension requires priv spec 1.12.0"); - return; - } -} - -static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp) -{ - RISCVCPU *cpu =3D RISCV_CPU(dev); - CPURISCVState *env =3D &cpu->env; - Error *local_err =3D NULL; - - if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) { - error_setg(errp, "'host' CPU is not compatible with TCG accelerati= on"); - return; - } - - riscv_cpu_validate_misa_mxl(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - - riscv_cpu_validate_priv_spec(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - - riscv_cpu_validate_misa_priv(env, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - - if (cpu->cfg.epmp && !cpu->cfg.pmp) { - /* - * Enhanced PMP should only be available - * on harts with PMP support - */ - error_setg(errp, "Invalid configuration: EPMP requires PMP support= "); - return; - } - - riscv_cpu_validate_set_extensions(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - -#ifndef CONFIG_USER_ONLY - CPU(dev)->tcg_cflags |=3D CF_PCREL; - - if (cpu->cfg.ext_sstc) { - riscv_timer_init(cpu); - } - - if (cpu->cfg.pmu_num) { - if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpm= f) { - cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, - riscv_pmu_timer_cb, cpu); - } - } -#endif -} - static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -1597,14 +1477,6 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) return; } =20 - if (tcg_enabled()) { - riscv_cpu_realize_tcg(dev, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - } - riscv_cpu_finalize_features(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 0326cead0d..84ad6f1daf 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -19,9 +19,140 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "pmu.h" +#include "time_helper.h" +#include "qapi/error.h" #include "qemu/accel.h" #include "hw/core/accel-cpu.h" =20 + +static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) +{ + if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { + error_setg(errp, "H extension requires priv spec 1.12.0"); + return; + } +} + +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); + CPUClass *cc =3D CPU_CLASS(mcc); + CPURISCVState *env =3D &cpu->env; + + /* Validate that MISA_MXL is set properly. */ + switch (env->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + case MXL_RV128: + cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; + break; +#endif + case MXL_RV32: + cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; + break; + default: + g_assert_not_reached(); + } + + if (env->misa_mxl_max !=3D env->misa_mxl) { + error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); + return; + } +} + +static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env =3D &cpu->env; + int priv_version =3D -1; + + if (cpu->cfg.priv_spec) { + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { + priv_version =3D PRIV_VERSION_1_12_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { + priv_version =3D PRIV_VERSION_1_11_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { + priv_version =3D PRIV_VERSION_1_10_0; + } else { + error_setg(errp, + "Unsupported privilege spec version '%s'", + cpu->cfg.priv_spec); + return; + } + + env->priv_ver =3D priv_version; + } +} + +/* + * We'll get here via the following path: + * + * riscv_cpu_realize() + * -> cpu_exec_realizefn() + * -> tcg_cpu_realizefn() (via accel_cpu_realizefn()) + */ +static bool tcg_cpu_realizefn(CPUState *cs, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + Error *local_err =3D NULL; + + if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { + error_setg(errp, "'host' CPU is not compatible with TCG accelerati= on"); + return false; + } + + riscv_cpu_validate_misa_mxl(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return false; + } + + riscv_cpu_validate_priv_spec(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return false; + } + + riscv_cpu_validate_misa_priv(env, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return false; + } + + if (cpu->cfg.epmp && !cpu->cfg.pmp) { + /* + * Enhanced PMP should only be available + * on harts with PMP support + */ + error_setg(errp, "Invalid configuration: EPMP requires PMP support= "); + return false; + } + + riscv_cpu_validate_set_extensions(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return false; + } + +#ifndef CONFIG_USER_ONLY + CPU(cs)->tcg_cflags |=3D CF_PCREL; + + if (cpu->cfg.ext_sstc) { + riscv_timer_init(cpu); + } + + if (cpu->cfg.pmu_num) { + if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpm= f) { + cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + riscv_pmu_timer_cb, cpu); + } + } +#endif + + return true; +} + static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) { /* @@ -41,6 +172,7 @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, vo= id *data) AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); =20 acc->cpu_class_init =3D tcg_cpu_class_init; + acc->cpu_realizefn =3D tcg_cpu_realizefn; } =20 static const TypeInfo tcg_cpu_accel_type_info =3D { --=20 2.41.0 From nobody Thu Nov 28 08:03:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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([177.94.15.194]) by smtp.gmail.com with ESMTPSA id n21-20020a9d6f15000000b006b75242d6c3sm6229228otq.38.2023.09.06.02.17.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 02:17:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693991825; x=1694596625; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OS7xlh2RVlzNnHxGen3zvqhSWmzvT5qWtbZ7JCqt058=; b=oiePYBhku6ZhTJzKsrkRYM//WBZGtsLOnIcwCkwfYfm3IRfDtH5Yz2gYjVq1CmOw58 8HakUvwKVaL+uCJDm0dulB64qEAywPS2052cxs4TAhGwh4fzYrW4JNXv5UcEamEorvYw BB97f+I6yO+C8z0Y2WjV2M1v38NIMoOFWv62PHaZgd/8LUDINMA73gztjiTTWsjwRhkm EmR7RXGo04sbB/AsolYc5tjZTvJ8xgdfj1asPjzFEtvdyjWpxcCHWPgONg8WGoXG5fdP Y0bWe21w7296PpV6OK5jOvQvKl16f0JzX0qQC+OMzkkrA8EIDL9TM887341CyiEJCuXI 9VeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693991825; x=1694596625; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OS7xlh2RVlzNnHxGen3zvqhSWmzvT5qWtbZ7JCqt058=; b=fHw0kpkgchG07KVMUoIqs4SNF0LozWHELz13qBATmBAGsizB6y8Yxm4PoFxIBwq0Gy IyK2tBIKW4Lb9BOLGsSTxS0d0SsEg6TtITh9Mn9PvxGCDR11/aySlNGnwx8y4zjTXXSo eNl0M+Wa9LgljOVfOo3KnbFIKfNw8HIT0ai0ud071s/CUXoq+rIaOkXYP9tNq8x9dCpQ 2NprA7aqouA0eXk29kEoxju9yWqkV8nw/xSYePO7nCkxMDaoCdkYEWHtZ3IPnmx023BO dfasR40ZFLw8+p0EVeXhdRu7/qLvNKsE9HzypY0SCjp1DNWqsRRbyY8cuQ1xfuXCh7Wv a0xA== X-Gm-Message-State: AOJu0YxEsO2BzeIkZTUYhiP8MYoR5INHz2oxRm5upk1U8PMeHZJ7YxJT 9vM8hc7AfBZEBpMlRuMF2HzksJKcnUvHT90OweU= X-Google-Smtp-Source: AGHT+IHfkk4dzmgswnlGlg1MhPFcErkDWrfWCfwNgpuFsthTWGKTbOZYdoZ/lqdl8DIo6mSYjJb3Lw== X-Received: by 2002:a05:6830:1259:b0:6bd:789:908f with SMTP id s25-20020a056830125900b006bd0789908fmr17611129otp.18.1693991825399; Wed, 06 Sep 2023 02:17:05 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 03/19] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c Date: Wed, 6 Sep 2023 06:16:30 -0300 Message-ID: <20230906091647.1667171-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com> References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1693992189976100001 Content-Type: text/plain; charset="utf-8" This function is the core of the RISC-V validations for TCG CPUs, and it has a lot going on. Functions in cpu.c were made public to allow them to be used by the KVM accelerator class later on. 'cpu_cfg_ext_get_min_version()' is notably hard to move it to another file due to its dependency with isa_edata_arr[] array, thus make it public and use it as is for now. riscv_cpu_validate_set_extensions() is kept public because it's used by csr.c in write_misa(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 361 +------------------------------------ target/riscv/cpu.h | 8 +- target/riscv/csr.c | 1 + target/riscv/tcg/tcg-cpu.c | 356 ++++++++++++++++++++++++++++++++++++ target/riscv/tcg/tcg-cpu.h | 28 +++ 5 files changed, 397 insertions(+), 357 deletions(-) create mode 100644 target/riscv/tcg/tcg-cpu.h diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 59785f5d9a..e186c026c9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -163,22 +163,21 @@ static const struct isa_ext_data isa_edata_arr[] =3D { /* Hash that stores user set extensions */ static GHashTable *multi_ext_user_opts; =20 -static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) +bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) { bool *ext_enabled =3D (void *)&cpu->cfg + ext_offset; =20 return *ext_enabled; } =20 -static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, - bool en) +void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en) { bool *ext_enabled =3D (void *)&cpu->cfg + ext_offset; =20 *ext_enabled =3D en; } =20 -static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) +int cpu_cfg_ext_get_min_version(uint32_t ext_offset) { int i; =20 @@ -193,38 +192,12 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_o= ffset) g_assert_not_reached(); } =20 -static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) +bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) { return g_hash_table_contains(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset)); } =20 -static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, - bool value) -{ - CPURISCVState *env =3D &cpu->env; - bool prev_val =3D isa_ext_is_enabled(cpu, ext_offset); - int min_version; - - if (prev_val =3D=3D value) { - return; - } - - if (cpu_cfg_ext_is_user_set(ext_offset)) { - return; - } - - if (value && env->priv_ver !=3D PRIV_VERSION_LATEST) { - /* Do not enable it if priv_ver is older than min_version */ - min_version =3D cpu_cfg_ext_get_min_version(ext_offset); - if (env->priv_ver < min_version) { - return; - } - } - - isa_ext_update_enabled(cpu, ext_offset, value); -} - const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -1023,46 +996,7 @@ static void riscv_cpu_disas_set_info(CPUState *s, dis= assemble_info *info) } } =20 -static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, - Error **errp) -{ - if (!is_power_of_2(cfg->vlen)) { - error_setg(errp, "Vector extension VLEN must be power of 2"); - return; - } - if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { - error_setg(errp, - "Vector extension implementation only supports VLEN " - "in the range [128, %d]", RV_VLEN_MAX); - return; - } - if (!is_power_of_2(cfg->elen)) { - error_setg(errp, "Vector extension ELEN must be power of 2"); - return; - } - if (cfg->elen > 64 || cfg->elen < 8) { - error_setg(errp, - "Vector extension implementation only supports ELEN " - "in the range [8, 64]"); - return; - } - if (cfg->vext_spec) { - if (!g_strcmp0(cfg->vext_spec, "v1.0")) { - env->vext_ver =3D VEXT_VERSION_1_00_0; - } else { - error_setg(errp, "Unsupported vector spec version '%s'", - cfg->vext_spec); - return; - } - } else if (env->vext_ver =3D=3D 0) { - qemu_log("vector version is not specified, " - "use the default value v1.0\n"); - - env->vext_ver =3D VEXT_VERSION_1_00_0; - } -} - -static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) +void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) { CPURISCVState *env =3D &cpu->env; int i; @@ -1086,291 +1020,6 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RI= SCVCPU *cpu) } } =20 -/* - * Check consistency between chosen extensions while setting - * cpu->cfg accordingly. - */ -void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) -{ - CPURISCVState *env =3D &cpu->env; - Error *local_err =3D NULL; - - /* Do some ISA extension error checking */ - if (riscv_has_ext(env, RVG) && - !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && - riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && - riscv_has_ext(env, RVD) && - cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { - - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) && - !cpu->cfg.ext_icsr) { - error_setg(errp, "RVG requires Zicsr but user set Zicsr to fal= se"); - return; - } - - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) && - !cpu->cfg.ext_ifencei) { - error_setg(errp, "RVG requires Zifencei but user set " - "Zifencei to false"); - return; - } - - warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true); - - env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; - env->misa_ext_mask |=3D RVI | RVM | RVA | RVF | RVD; - } - - if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { - error_setg(errp, - "I and E extensions are incompatible"); - return; - } - - if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { - error_setg(errp, - "Either I or E extension must be set"); - return; - } - - if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { - error_setg(errp, - "Setting S extension without U extension is illegal"); - return; - } - - if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { - error_setg(errp, - "H depends on an I base integer ISA with 32 x registers= "); - return; - } - - if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { - error_setg(errp, "H extension implicitly requires S-mode"); - return; - } - - if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) { - error_setg(errp, "F extension requires Zicsr"); - return; - } - - if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { - error_setg(errp, "Zawrs extension requires A extension"); - return; - } - - if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { - error_setg(errp, "Zfa extension requires F extension"); - return; - } - - if (cpu->cfg.ext_zfh) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true); - } - - if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { - error_setg(errp, "Zfh/Zfhmin extensions require F extension"); - return; - } - - if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { - error_setg(errp, "Zfbfmin extension depends on F extension"); - return; - } - - if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { - error_setg(errp, "D extension requires F extension"); - return; - } - - if (riscv_has_ext(env, RVV)) { - riscv_cpu_validate_v(env, &cpu->cfg, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - - /* The V vector extension depends on the Zve64d extension */ - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true); - } - - /* The Zve64d extension depends on the Zve64f extension */ - if (cpu->cfg.ext_zve64d) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true); - } - - /* The Zve64f extension depends on the Zve32f extension */ - if (cpu->cfg.ext_zve64f) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true); - } - - if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { - error_setg(errp, "Zve64d/V extensions require D extension"); - return; - } - - if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { - error_setg(errp, "Zve32f/Zve64f extensions require F extension"); - return; - } - - if (cpu->cfg.ext_zvfh) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true); - } - - if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { - error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension= "); - return; - } - - if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { - error_setg(errp, "Zvfh extensions requires Zfhmin extension"); - return; - } - - if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) { - error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension"= ); - return; - } - - if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { - error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); - return; - } - - if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { - error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension= "); - return; - } - - /* Set the ISA extensions, checks should have happened above */ - if (cpu->cfg.ext_zhinx) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); - } - - if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfi= nx) { - error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); - return; - } - - if (cpu->cfg.ext_zfinx) { - if (!cpu->cfg.ext_icsr) { - error_setg(errp, "Zfinx extension requires Zicsr"); - return; - } - if (riscv_has_ext(env, RVF)) { - error_setg(errp, - "Zfinx cannot be supported together with F extensio= n"); - return; - } - } - - if (cpu->cfg.ext_zce) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); - if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); - } - } - - /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ - if (riscv_has_ext(env, RVC) && env->priv_ver >=3D PRIV_VERSION_1_12_0)= { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); - if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); - } - if (riscv_has_ext(env, RVD)) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); - } - } - - if (env->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { - error_setg(errp, "Zcf extension is only relevant to RV32"); - return; - } - - if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { - error_setg(errp, "Zcf extension requires F extension"); - return; - } - - if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { - error_setg(errp, "Zcd extension requires D extension"); - return; - } - - if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || - cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { - error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " - "extension"); - return; - } - - if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { - error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " - "Zcd extension"); - return; - } - - if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { - error_setg(errp, "Zcmt extension requires Zicsr extension"); - return; - } - - /* - * In principle Zve*x would also suffice here, were they supported - * in qemu - */ - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || - cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh)= && - !cpu->cfg.ext_zve32f) { - error_setg(errp, - "Vector crypto extensions require V or Zve* extensions"= ); - return; - } - - if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f= ) { - error_setg( - errp, - "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions= "); - return; - } - - if (cpu->cfg.ext_zk) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true); - } - - if (cpu->cfg.ext_zkn) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true); - } - - if (cpu->cfg.ext_zks) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true); - } - - /* - * Disable isa extensions based on priv spec after we - * validated and set everything we need. - */ - riscv_cpu_disable_priv_spec_isa_exts(cpu); -} - #ifndef CONFIG_USER_ONLY static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b84b62f84e..721bd0b119 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -445,7 +445,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); -void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); =20 #define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index @@ -711,6 +710,13 @@ enum riscv_pmu_event_idx { #include "hw/core/tcg-cpu-ops.h" extern const struct TCGCPUOps riscv_tcg_ops; =20 +/* used by tcg/tcg-cpu.c*/ +void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); +bool cpu_cfg_ext_is_user_set(uint32_t ext_offset); +bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); +int cpu_cfg_ext_get_min_version(uint32_t ext_offset); +void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu); + /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6145039832..65473b257f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "qemu/timer.h" #include "cpu.h" +#include "tcg/tcg-cpu.h" #include "pmu.h" #include "time_helper.h" #include "qemu/main-loop.h" diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 84ad6f1daf..da18851ed4 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -18,14 +18,42 @@ */ =20 #include "qemu/osdep.h" +#include "tcg-cpu.h" #include "cpu.h" #include "pmu.h" #include "time_helper.h" #include "qapi/error.h" #include "qemu/accel.h" +#include "qemu/error-report.h" #include "hw/core/accel-cpu.h" =20 =20 +static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, + bool value) +{ + CPURISCVState *env =3D &cpu->env; + bool prev_val =3D isa_ext_is_enabled(cpu, ext_offset); + int min_version; + + if (prev_val =3D=3D value) { + return; + } + + if (cpu_cfg_ext_is_user_set(ext_offset)) { + return; + } + + if (value && env->priv_ver !=3D PRIV_VERSION_LATEST) { + /* Do not enable it if priv_ver is older than min_version */ + min_version =3D cpu_cfg_ext_get_min_version(ext_offset); + if (env->priv_ver < min_version) { + return; + } + } + + isa_ext_update_enabled(cpu, ext_offset, value); +} + static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) { if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { @@ -84,6 +112,334 @@ static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu= , Error **errp) } } =20 +static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, + Error **errp) +{ + if (!is_power_of_2(cfg->vlen)) { + error_setg(errp, "Vector extension VLEN must be power of 2"); + return; + } + + if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { + error_setg(errp, + "Vector extension implementation only supports VLEN " + "in the range [128, %d]", RV_VLEN_MAX); + return; + } + + if (!is_power_of_2(cfg->elen)) { + error_setg(errp, "Vector extension ELEN must be power of 2"); + return; + } + + if (cfg->elen > 64 || cfg->elen < 8) { + error_setg(errp, + "Vector extension implementation only supports ELEN " + "in the range [8, 64]"); + return; + } + + if (cfg->vext_spec) { + if (!g_strcmp0(cfg->vext_spec, "v1.0")) { + env->vext_ver =3D VEXT_VERSION_1_00_0; + } else { + error_setg(errp, "Unsupported vector spec version '%s'", + cfg->vext_spec); + return; + } + } else if (env->vext_ver =3D=3D 0) { + qemu_log("vector version is not specified, " + "use the default value v1.0\n"); + + env->vext_ver =3D VEXT_VERSION_1_00_0; + } +} + +/* + * Check consistency between chosen extensions while setting + * cpu->cfg accordingly. + */ +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env =3D &cpu->env; + Error *local_err =3D NULL; + + /* Do some ISA extension error checking */ + if (riscv_has_ext(env, RVG) && + !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && + riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && + riscv_has_ext(env, RVD) && + cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { + + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) && + !cpu->cfg.ext_icsr) { + error_setg(errp, "RVG requires Zicsr but user set Zicsr to fal= se"); + return; + } + + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) && + !cpu->cfg.ext_ifencei) { + error_setg(errp, "RVG requires Zifencei but user set " + "Zifencei to false"); + return; + } + + warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true); + + env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; + env->misa_ext_mask |=3D RVI | RVM | RVA | RVF | RVD; + } + + if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { + error_setg(errp, + "I and E extensions are incompatible"); + return; + } + + if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { + error_setg(errp, + "Either I or E extension must be set"); + return; + } + + if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { + error_setg(errp, + "Setting S extension without U extension is illegal"); + return; + } + + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { + error_setg(errp, + "H depends on an I base integer ISA with 32 x registers= "); + return; + } + + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { + error_setg(errp, "H extension implicitly requires S-mode"); + return; + } + + if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) { + error_setg(errp, "F extension requires Zicsr"); + return; + } + + if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { + error_setg(errp, "Zawrs extension requires A extension"); + return; + } + + if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { + error_setg(errp, "Zfa extension requires F extension"); + return; + } + + if (cpu->cfg.ext_zfh) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true); + } + + if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { + error_setg(errp, "Zfh/Zfhmin extensions require F extension"); + return; + } + + if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { + error_setg(errp, "Zfbfmin extension depends on F extension"); + return; + } + + if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { + error_setg(errp, "D extension requires F extension"); + return; + } + + if (riscv_has_ext(env, RVV)) { + riscv_cpu_validate_v(env, &cpu->cfg, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + + /* The V vector extension depends on the Zve64d extension */ + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true); + } + + /* The Zve64d extension depends on the Zve64f extension */ + if (cpu->cfg.ext_zve64d) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true); + } + + /* The Zve64f extension depends on the Zve32f extension */ + if (cpu->cfg.ext_zve64f) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true); + } + + if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { + error_setg(errp, "Zve64d/V extensions require D extension"); + return; + } + + if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { + error_setg(errp, "Zve32f/Zve64f extensions require F extension"); + return; + } + + if (cpu->cfg.ext_zvfh) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true); + } + + if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { + error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension= "); + return; + } + + if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { + error_setg(errp, "Zvfh extensions requires Zfhmin extension"); + return; + } + + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) { + error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension"= ); + return; + } + + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { + error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); + return; + } + + if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { + error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension= "); + return; + } + + /* Set the ISA extensions, checks should have happened above */ + if (cpu->cfg.ext_zhinx) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); + } + + if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfi= nx) { + error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); + return; + } + + if (cpu->cfg.ext_zfinx) { + if (!cpu->cfg.ext_icsr) { + error_setg(errp, "Zfinx extension requires Zicsr"); + return; + } + if (riscv_has_ext(env, RVF)) { + error_setg(errp, + "Zfinx cannot be supported together with F extensio= n"); + return; + } + } + + if (cpu->cfg.ext_zce) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); + if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); + } + } + + /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ + if (riscv_has_ext(env, RVC) && env->priv_ver >=3D PRIV_VERSION_1_12_0)= { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); + if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); + } + if (riscv_has_ext(env, RVD)) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); + } + } + + if (env->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { + error_setg(errp, "Zcf extension is only relevant to RV32"); + return; + } + + if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { + error_setg(errp, "Zcf extension requires F extension"); + return; + } + + if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { + error_setg(errp, "Zcd extension requires D extension"); + return; + } + + if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || + cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { + error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " + "extension"); + return; + } + + if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { + error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " + "Zcd extension"); + return; + } + + if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { + error_setg(errp, "Zcmt extension requires Zicsr extension"); + return; + } + + /* + * In principle Zve*x would also suffice here, were they supported + * in qemu + */ + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || + cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh)= && + !cpu->cfg.ext_zve32f) { + error_setg(errp, + "Vector crypto extensions require V or Zve* extensions"= ); + return; + } + + if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f= ) { + error_setg( + errp, + "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions= "); + return; + } + + if (cpu->cfg.ext_zk) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true); + } + + if (cpu->cfg.ext_zkn) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true); + } + + if (cpu->cfg.ext_zks) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true); + } + + /* + * Disable isa extensions based on priv spec after we + * validated and set everything we need. + */ + riscv_cpu_disable_priv_spec_isa_exts(cpu); +} + /* * We'll get here via the following path: * diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h new file mode 100644 index 0000000000..4cf35a8015 --- /dev/null +++ b/target/riscv/tcg/tcg-cpu.h @@ -0,0 +1,28 @@ +/* + * riscv TCG cpu class initialization + * + * Copyright (c) 2023 Ventana Micro Systems Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef RISCV_TCG_CPU_H +#define RISCV_TCG_CPU_H + +#include "cpu.h" + +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); + +#endif + --=20 2.41.0 From nobody Thu Nov 28 08:03:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1693992193; cv=none; d=zohomail.com; s=zohoarc; b=LeoM1C5g0Wslxw8i2bfz7gP1kwVFlyx7C1SeeR5/fTJnmmfwMmIzEtjK3AScbM/NGQdTKRCclu26/6Uxus0igtx2bNatkuJDcX1y8Q+ghmom8J3rA3NmAFOVgxSp8Jo/Vjv0Vc15jxrf5cQ4wIW8xVS85Iv7QXa4geJxt6HxJUc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693992193; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=r/XqMqmkjBuQ7igNtla2QSukBWkpojMJT/hIbQ2/MtA=; b=Vf2RMk3pFTCVnZfv+NExasCyTVQHf9IvpRr0/ylLvU9xiu/ppPBK6cZ4L9NweMlsjaxHccNnngbpoHtg9m3oQaLW8JZf8nDwraRu6CjcrKeV9m2SBmhtdnp5a2ZPRZAQJf9ccRlehOYwH1ahzPSCL3XmlyBgfA6MfCQ/xwe9pZg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693992193707650.8074571681753; Wed, 6 Sep 2023 02:23:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qdof1-0003EI-Ku; Wed, 06 Sep 2023 05:17:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qdoev-0002s9-9p for qemu-devel@nongnu.org; Wed, 06 Sep 2023 05:17:13 -0400 Received: from mail-ot1-x333.google.com ([2607:f8b0:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qdoes-0005fF-Ed for qemu-devel@nongnu.org; Wed, 06 Sep 2023 05:17:13 -0400 Received: by mail-ot1-x333.google.com with SMTP id 46e09a7af769-6bf04263dc8so2491440a34.3 for ; Wed, 06 Sep 2023 02:17:10 -0700 (PDT) Received: from grind.. ([177.94.15.194]) by smtp.gmail.com with ESMTPSA id n21-20020a9d6f15000000b006b75242d6c3sm6229228otq.38.2023.09.06.02.17.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 02:17:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693991829; x=1694596629; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r/XqMqmkjBuQ7igNtla2QSukBWkpojMJT/hIbQ2/MtA=; b=eeHEsQyl9oLS0IrABP1+RkP4KJoZlpL5u4ar8as5rGCzMFQQeZrthjOglYscrWdozE yKvJW2EdZhcxn40F7pkCUhDK5YvveDY6i3OgjCnEC7bL1YcUn7NdSSHtqRWdRkWbWNxf /hWqcS5qwacdP1cGLW4Miq5LGA4DHwzbTYGGl2tsZvEPEyt19o+zIwMCBkthD9fOyjp2 JSMClbKxlMTh4ZeewtJhVHnnjd50rNpyZ8KxGbV8Jiq0S7u5UYW4lsLdfFudNGcFMVNd 6eh9b/X7a27prEVI1jPcJmuFgzudxKSnJXGY1d/GAGLkmD2cwLJpRrIoITIaHhf9CCoW 6z9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693991829; x=1694596629; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r/XqMqmkjBuQ7igNtla2QSukBWkpojMJT/hIbQ2/MtA=; b=TMMKhoFLemk31ZfndvJcFDa02tlTouAczWiMA4TxF/7hBt/e/WSRWEQr1/2B9oEl5T yAm5IOFU6VU2hjNJl+21b3zErmhWBQPO+ojj7qQQ85LftWxqbj6zTI0gbBRZkIKgj9ij fpzVpMS1P3O+c1BvD4v9N4ySHH4zbYgg3QZAmVm0BACZ6wU/ZmjwSNvQzrCftUaomfaT MOpHJw5P57xaGPRAD7Tj8rOCgIIhBtCb8YzYSEMff3sCDhZXRVwHEOxajgFhKap767lp mpUXleBOmsV9QCUp1xPABoRlLXSDCsbUxszIXR2AADuMMZWZD3RYWlmTGFKO3FqwvgEl M5cg== X-Gm-Message-State: AOJu0Yyj4j9UPlkQ9RZZ5V0woYalRb8L+GkyySheDy+tIMOTDB+Jcq0o q/IuB1ORBzYsBGDildPhZu92LP7AOGS5Pm8L0TQ= X-Google-Smtp-Source: AGHT+IGau6LiA8T8MXMCbAYg/F8SpUrSMpBRwF6LG34ZEe6yjdO6G0aS3onGa59kyqyYrLyQXC6rsg== X-Received: by 2002:a05:6830:1350:b0:6b9:14bf:7097 with SMTP id r16-20020a056830135000b006b914bf7097mr17213354otq.9.1693991828989; Wed, 06 Sep 2023 02:17:08 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 04/19] target/riscv: move riscv_tcg_ops to tcg-cpu.c Date: Wed, 6 Sep 2023 06:16:31 -0300 Message-ID: <20230906091647.1667171-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com> References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1693992195273100003 Move the remaining of riscv_tcg_ops now that we have a working realize() implementation. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 58 ------------------------------------ target/riscv/cpu.h | 4 --- target/riscv/tcg/tcg-cpu.c | 60 +++++++++++++++++++++++++++++++++++++- 3 files changed, 59 insertions(+), 63 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e186c026c9..7569955c7e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -838,24 +838,6 @@ static vaddr riscv_cpu_get_pc(CPUState *cs) return env->pc; } =20 -static void riscv_cpu_synchronize_from_tb(CPUState *cs, - const TranslationBlock *tb) -{ - if (!(tb_cflags(tb) & CF_PCREL)) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); - - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); - - if (xl =3D=3D MXL_RV32) { - env->pc =3D (int32_t) tb->pc; - } else { - env->pc =3D tb->pc; - } - } -} - static bool riscv_cpu_has_work(CPUState *cs) { #ifndef CONFIG_USER_ONLY @@ -871,29 +853,6 @@ static bool riscv_cpu_has_work(CPUState *cs) #endif } =20 -static void riscv_restore_state_to_opc(CPUState *cs, - const TranslationBlock *tb, - const uint64_t *data) -{ - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); - target_ulong pc; - - if (tb_cflags(tb) & CF_PCREL) { - pc =3D (env->pc & TARGET_PAGE_MASK) | data[0]; - } else { - pc =3D data[0]; - } - - if (xl =3D=3D MXL_RV32) { - env->pc =3D (int32_t)pc; - } else { - env->pc =3D pc; - } - env->bins =3D data[1]; -} - static void riscv_cpu_reset_hold(Object *obj) { #ifndef CONFIG_USER_ONLY @@ -1811,23 +1770,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = =3D { }; #endif =20 -const struct TCGCPUOps riscv_tcg_ops =3D { - .initialize =3D riscv_translate_init, - .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, - .restore_state_to_opc =3D riscv_restore_state_to_opc, - -#ifndef CONFIG_USER_ONLY - .tlb_fill =3D riscv_cpu_tlb_fill, - .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, - .do_interrupt =3D riscv_cpu_do_interrupt, - .do_transaction_failed =3D riscv_cpu_do_transaction_failed, - .do_unaligned_access =3D riscv_cpu_do_unaligned_access, - .debug_excp_handler =3D riscv_cpu_debug_excp_handler, - .debug_check_breakpoint =3D riscv_cpu_debug_check_breakpoint, - .debug_check_watchpoint =3D riscv_cpu_debug_check_watchpoint, -#endif /* !CONFIG_USER_ONLY */ -}; - static bool riscv_cpu_is_dynamic(Object *cpu_obj) { return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 721bd0b119..2ac00a0304 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -706,10 +706,6 @@ enum riscv_pmu_event_idx { RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS =3D 0x10021, }; =20 -/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */ -#include "hw/core/tcg-cpu-ops.h" -extern const struct TCGCPUOps riscv_tcg_ops; - /* used by tcg/tcg-cpu.c*/ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); bool cpu_cfg_ext_is_user_set(uint32_t ext_offset); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index da18851ed4..8698ce4765 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -26,7 +26,66 @@ #include "qemu/accel.h" #include "qemu/error-report.h" #include "hw/core/accel-cpu.h" +#include "hw/core/tcg-cpu-ops.h" +#include "tcg/tcg.h" =20 +static void riscv_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) +{ + if (!(tb_cflags(tb) & CF_PCREL)) { + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); + + tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); + + if (xl =3D=3D MXL_RV32) { + env->pc =3D (int32_t) tb->pc; + } else { + env->pc =3D tb->pc; + } + } +} + +static void riscv_restore_state_to_opc(CPUState *cs, + const TranslationBlock *tb, + const uint64_t *data) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); + target_ulong pc; + + if (tb_cflags(tb) & CF_PCREL) { + pc =3D (env->pc & TARGET_PAGE_MASK) | data[0]; + } else { + pc =3D data[0]; + } + + if (xl =3D=3D MXL_RV32) { + env->pc =3D (int32_t)pc; + } else { + env->pc =3D pc; + } + env->bins =3D data[1]; +} + +static const struct TCGCPUOps riscv_tcg_ops =3D { + .initialize =3D riscv_translate_init, + .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, + .restore_state_to_opc =3D riscv_restore_state_to_opc, + +#ifndef CONFIG_USER_ONLY + .tlb_fill =3D riscv_cpu_tlb_fill, + .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, + .do_interrupt =3D riscv_cpu_do_interrupt, + .do_transaction_failed =3D riscv_cpu_do_transaction_failed, + .do_unaligned_access =3D riscv_cpu_do_unaligned_access, + .debug_excp_handler =3D riscv_cpu_debug_excp_handler, + .debug_check_breakpoint =3D riscv_cpu_debug_check_breakpoint, + .debug_check_watchpoint =3D riscv_cpu_debug_check_watchpoint, +#endif /* !CONFIG_USER_ONLY */ +}; =20 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, bool value) @@ -513,7 +572,6 @@ static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, = CPUClass *cc) { /* * All cpus use the same set of operations. - * riscv_tcg_ops is being imported from cpu.c for now. */ cc->tcg_ops =3D &riscv_tcg_ops; } --=20 2.41.0 From nobody Thu Nov 28 08:03:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1693992041; cv=none; d=zohomail.com; s=zohoarc; b=iNhuohggqgjJcZ4v2zWbu1MiFR1WTF8zncvh+rqwDS1TEgTi6n4NFWJuXJuw1yQDUGv8kT3OrKjryoF5W4qDtZQ4JP0fh8/TUfFFZx4hC/dChkhu8FQ65VKCn5RRgKjPpFIswett7kAjGX1rFbEUDu0J0SqW5fHlNXxWDZfawL8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693992041; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([177.94.15.194]) by smtp.gmail.com with ESMTPSA id n21-20020a9d6f15000000b006b75242d6c3sm6229228otq.38.2023.09.06.02.17.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 02:17:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693991832; x=1694596632; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/Aph7QVhozHi4LSu/mXzyfv/k3iUkG4CIBstH4LTFwg=; b=n9wCXa9UCLMfixHfBakVD7KBaIQnFcbM2MblZJiFcUQvl+ojYYgT6o+ChtQjfOVOKD DCXV1qcGKaJUF819B1HfFIbQhRJM/N5zICxBrEP2Wh9p0A45oHA1gxjRvkKeaBJT81eY gcgVxprWI2YBeFiO1SW951EWRzqM518gmwdC7y+PUDdyLAPcczWaGZDIKsZaBibU/52i Y5m68NWiHzTqDO0xaYk+nrTMwfOimUN7YcXptu+a/aY18Ecl1qiVbuW2udOzFUsQV1db rDct+NmBbkiYO1A52Qzgjq340ZBHaGj0ofO/fR3BnotsjRk0E3AYK377ymCQlkYNHeIS L+UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693991832; x=1694596632; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/Aph7QVhozHi4LSu/mXzyfv/k3iUkG4CIBstH4LTFwg=; b=GLYbHaV8kuUhe4TmIRU0YDz7PlnYfhNUPFvlidibfGL9GRw1LrGJqGwRiipia8FNZm ZzYxHSY2N54H6avF77PFC2Kmm6l1ifh/WY0lGh/PNl26+jij7Xn8T/2852UkmMuKkpr5 yidieZiOA9EH9l3SdB4wp6rKDCwEGEKkn2tBEazzDF50UM98/IsJ3HgOyX60JMOdhDP+ RCI/fKwSyN9eL9qgxqyKlhZLYH+w3yOLcM6cD/epdYNE9IvMM628MPCcFggUhC5EK9tp QOxBn6aSo3H/PF5kvwsKd+/Y4ZGXtDwwI1lYRnUl0z+x8262dYOE7y9Ym0mDNfrI+oER 2Miw== X-Gm-Message-State: AOJu0YyjH90bJg0pVEnAqB5sTULv0AljdhuhVHjxoECm01l/rkxqx3pp Dm0ZSZtYOvUGvvNv+bPJRualt/E6h18I4tbzRa0= X-Google-Smtp-Source: AGHT+IHKxmgrNfmpepUmySox/c9ApSJFaMlwm/EFoaLiGDxSRSLxkE/xFvSjzIP9ff3Sk0ZzDO77EQ== X-Received: by 2002:a9d:7d94:0:b0:6bd:9fa:34ff with SMTP id j20-20020a9d7d94000000b006bd09fa34ffmr16249958otn.9.1693991832251; Wed, 06 Sep 2023 02:17:12 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 05/19] target/riscv/cpu.c: add .instance_post_init() Date: Wed, 6 Sep 2023 06:16:32 -0300 Message-ID: <20230906091647.1667171-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com> References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1693992043976100003 Content-Type: text/plain; charset="utf-8" All generic CPUs call riscv_cpu_add_user_properties(). The 'max' CPU calls riscv_init_max_cpu_extensions(). Both can be moved to a common instance_post_init() callback, implemented in riscv_cpu_post_init(), called by all CPUs. The call order then becomes: riscv_cpu_init() -> cpu_init() of each CPU -> .instance_post_init() In the near future riscv_cpu_post_init() will call the init() function of the current accelerator, providing a hook for KVM and TCG accel classes to change the init() process of the CPU. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 42 ++++++++++++++++++++++++++++++++---------- 1 file changed, 32 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7569955c7e..4c6d595067 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -427,8 +427,6 @@ static void riscv_max_cpu_init(Object *obj) mlx =3D MXL_RV32; #endif set_misa(env, mlx, 0); - riscv_cpu_add_user_properties(obj); - riscv_init_max_cpu_extensions(obj); env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), mlx =3D=3D MXL_RV32 ? @@ -442,7 +440,6 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); - riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -566,7 +563,6 @@ static void rv128_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); - riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -579,7 +575,6 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); - riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -1215,6 +1210,37 @@ static void riscv_cpu_set_irq(void *opaque, int irq,= int level) } #endif /* CONFIG_USER_ONLY */ =20 +static bool riscv_cpu_is_dynamic(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; +} + +static bool riscv_cpu_has_max_extensions(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) !=3D NULL; +} + +static bool riscv_cpu_has_user_properties(Object *cpu_obj) +{ + if (kvm_enabled() && + object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) !=3D NULL) { + return true; + } + + return riscv_cpu_is_dynamic(cpu_obj); +} + +static void riscv_cpu_post_init(Object *obj) +{ + if (riscv_cpu_has_user_properties(obj)) { + riscv_cpu_add_user_properties(obj); + } + + if (riscv_cpu_has_max_extensions(obj)) { + riscv_init_max_cpu_extensions(obj); + } +} + static void riscv_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); @@ -1770,11 +1796,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = =3D { }; #endif =20 -static bool riscv_cpu_is_dynamic(Object *cpu_obj) -{ - return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; -} - static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -2011,6 +2032,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .instance_size =3D sizeof(RISCVCPU), .instance_align =3D __alignof__(RISCVCPU), .instance_init =3D riscv_cpu_init, + .instance_post_init =3D riscv_cpu_post_init, .abstract =3D true, .class_size =3D sizeof(RISCVCPUClass), .class_init =3D riscv_cpu_class_init, --=20 2.41.0 From nobody Thu Nov 28 08:03:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([177.94.15.194]) by smtp.gmail.com with ESMTPSA id n21-20020a9d6f15000000b006b75242d6c3sm6229228otq.38.2023.09.06.02.17.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 02:17:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693991835; x=1694596635; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RSr2lSljPMfDziUB5b/tWMJTQP/2QzYe7O9nDpyZRtU=; b=oRHZQ3fmkGYPfeYLulL5CnZW7CFbc9JVsg2iuP+ZCnXZCUR5qscDa/vhZT7oSoibFx 7JX9JyvcGX3hZTAiJc25pIVV5lAWA1vBHA7NLUNrqOvCv1GvH0ivrQpHs64wLimkRH79 FN9wyt4kNKLhhx55PUYbqTJezhVzvosQRNIez43r8Ov42uTLadRxVsWmaUoulX4vJK63 XtOeqDx2QWpo9KYrAYKOkd9Om4enegL6A+JB1uDsMC+R6FwPFsc+uuRiPsGIrk6PUked /lbFAdISVnLWNrC/Ui+XlfGQR3y2rU9RrpPewnoRx1nNPXLZtaZ+l/1Z6LFMnFEP9LYF HoUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693991835; x=1694596635; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RSr2lSljPMfDziUB5b/tWMJTQP/2QzYe7O9nDpyZRtU=; b=Xk8kjJf2FuUgajrJZuMJyuX38Tv9MTaQ8eYGZGJGmsybiIFzXZNEo2XocrF7KAbcOD nDFrX/+A4DbGE7wWghEVGHViGZF3byRrXzDF5nulMNO082QnrXtuCoHMMHFZujT7NMRU 76ZfyeTUpFYJ4cyBPNfoKQ2ofFTgN9L0327WAPAjuMw3AomSpO25N6rwyRtmMljgXM+C SEVJEBfgVLiwAk4Zkf2clFXEWCmx8mcDQXk4+IzBm41BxdRyC/1bFH26+OjhuLzj49ZJ 1FxpE/H6UzJywV0h8FuwJN+u7BpslKW+OkGX3MmNXCpvOlfD9QPIe0FkMwY2pwy4xM3u MNAQ== X-Gm-Message-State: AOJu0YxaF5sbdkHqr6WDleaSGc/qR5E3K00gzQpMEshr+jhMDHwYTAuf Jf5gOI2DiSEMYrilC9vM90HugMb+8tJbajSpcS0= X-Google-Smtp-Source: AGHT+IEc3UVuOWwi6UevtE9BUV3xWuFIi/w55uPIiZyLtNBdudRVKAiKVFWnFXsdC5hlnWDha57CDA== X-Received: by 2002:a9d:618a:0:b0:6bc:9c9b:e787 with SMTP id g10-20020a9d618a000000b006bc9c9be787mr15379151otk.8.1693991835354; Wed, 06 Sep 2023 02:17:15 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 06/19] target/riscv: move 'host' CPU declaration to kvm.c Date: Wed, 6 Sep 2023 06:16:33 -0300 Message-ID: <20230906091647.1667171-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com> References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1693992046114100007 This CPU only exists if we're compiling with KVM so move it to the kvm specific file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 16 ---------------- target/riscv/kvm.c | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4c6d595067..c15bb572d4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -652,19 +652,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) } #endif =20 -#if defined(CONFIG_KVM) -static void riscv_host_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; -#if defined(TARGET_RISCV32) - set_misa(env, MXL_RV32, 0); -#elif defined(TARGET_RISCV64) - set_misa(env, MXL_RV64, 0); -#endif - riscv_cpu_add_user_properties(obj); -} -#endif /* CONFIG_KVM */ - static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; @@ -2044,9 +2031,6 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { }, DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), -#if defined(CONFIG_KVM) - DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), -#endif #if defined(TARGET_RISCV32) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 14763ec0cd..b4d8d7a46c 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -1227,3 +1227,24 @@ void kvm_riscv_aia_create(MachineState *machine, uin= t64_t group_shift, =20 kvm_msi_via_irqfd_allowed =3D kvm_irqfds_enabled(); } + +static void riscv_host_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + +#if defined(TARGET_RISCV32) + env->misa_mxl_max =3D env->misa_mxl =3D MXL_RV32; +#elif defined(TARGET_RISCV64) + env->misa_mxl_max =3D env->misa_mxl =3D MXL_RV64; +#endif +} + +static const TypeInfo riscv_kvm_cpu_type_infos[] =3D { + { + .name =3D TYPE_RISCV_CPU_HOST, + .parent =3D TYPE_RISCV_CPU, + .instance_init =3D riscv_host_cpu_init, + } +}; + +DEFINE_TYPES(riscv_kvm_cpu_type_infos) --=20 2.41.0 From nobody Thu Nov 28 08:03:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1693992120; cv=none; d=zohomail.com; s=zohoarc; b=KTVWnd6kCghSUN9+TIk9GFJcYhsy700ieFza4z+f2EmQPD0IjEuy6NBP0jCxTnkSEe9fC1qZT6GaJfcWBakbIijcNIzhuRbCGa/d1nVgBH+X/QTj+1+9VB5vd6XnyRz4KCI2tEtXcxk0y26QKSpmlMIpnMqb7THPcTsXLuiAFCc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693992120; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KUviRQA1sK0A4rpWZqbYotX2RmzhgK7a82GEIjW761U=; b=V97qBQag6+baTSHO5rL1HoZ2L3y/fewWCQ7pu+D1jud8rrTn5lZiOT5gyqPmTQynuSEl3KpKfSerZrH/UfLpm5AeLfdEFqwdjrc5JcEsz8bKf660/Hm4sVgALQXUlhTGzs/KOIn09ctxwxZDGVWpeTuFMbtlawqQ3tkcK6fvWpk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693992120210860.7947537416348; Wed, 6 Sep 2023 02:22:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qdof6-0003KI-0a; Wed, 06 Sep 2023 05:17:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qdof4-0003Iz-Ii for qemu-devel@nongnu.org; Wed, 06 Sep 2023 05:17:22 -0400 Received: from mail-ot1-x32c.google.com ([2607:f8b0:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qdof1-0005l2-MM for qemu-devel@nongnu.org; Wed, 06 Sep 2023 05:17:22 -0400 Received: by mail-ot1-x32c.google.com with SMTP id 46e09a7af769-6c09f1f4610so559782a34.0 for ; Wed, 06 Sep 2023 02:17:19 -0700 (PDT) Received: from grind.. ([177.94.15.194]) by smtp.gmail.com with ESMTPSA id n21-20020a9d6f15000000b006b75242d6c3sm6229228otq.38.2023.09.06.02.17.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 02:17:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693991838; x=1694596638; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KUviRQA1sK0A4rpWZqbYotX2RmzhgK7a82GEIjW761U=; b=M7+PgIYuD+BCk23bG5nx0uw/syESxzQjyJoEtLrQkH3/Bpl3pntsNxWTHC4/nDQBYo ZY+D6Ju9CngFHEY13E6hMgG4bd3ph7dvJNTPiOY27BM3jTf7fgquesz1o/qiW5w5tzMz ZZr1TiQa8v1uAx9fm7Wa5H6iq7Hg1VvZSNmdNTPtmn+skqDoqXd7meMDSdFd1SQDQic1 ozb7LMkKskMYVvFlF/iRyxw2lIOpTF/FAp3VtA/B18GgEygU0olF00hJwihvlQmRG8yy mgLpvqw1L32m0/VxK51p9fiFpmHiwBaDDo5AN3Bnhsma7C5kkNCR8N6YsGMEKRBrqRP1 rX2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693991838; x=1694596638; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KUviRQA1sK0A4rpWZqbYotX2RmzhgK7a82GEIjW761U=; b=Qk1Tpa3vco4Cpm9VDL5uwWHZVFuAiY/NvhZMG9zM7p06Odmjorb3FGdVJElyd0yJ3C rNhoEGnANWz7vyXcDqSDmBK8LgK18I4hYxoCVg4BAdG5C45tgjPsgYwee3b52VQG8U+C UoVZ4Pg+ZwdjVEzNmpiBT10vUy/gL2yKhH85s5PUCuGWzvJuAcqd/w+qRIMH4psPFSBQ DO/eRVdtj2sNOux7/ihe8HMFCB93/CWgytmGJfvHo6QPqqIYUvsDhlxY8hGX6M0KXdyl 9lz8ZdrSutSlLFgeIR52imDhePmY8H1UG9OWUknxr2bRu8tHqeXjH1IW8V6UFZ7+LSS1 CQHQ== X-Gm-Message-State: AOJu0YyWsMfXKX9EnFc6qhhMe0tvfWkKVrJW0qCDTc+S2fMycFv+D+v5 h/4Jstm8zJ/0Xt7ksCns8zdwEfaiOh9z0OW7l4k= X-Google-Smtp-Source: AGHT+IHHJ4BakLsSqcRaLPSHIpoQ31GrNdvqrjrOmsExPupkuwYYwuDhiUUjzvqTcsZxux1nz2b6+A== X-Received: by 2002:a05:6830:1510:b0:6bd:bcd:43f8 with SMTP id k16-20020a056830151000b006bd0bcd43f8mr15413569otp.21.1693991838455; Wed, 06 Sep 2023 02:17:18 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 07/19] target/riscv/cpu.c: mark extensions arrays as 'const' Date: Wed, 6 Sep 2023 06:16:34 -0300 Message-ID: <20230906091647.1667171-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com> References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1693992121340100001 Content-Type: text/plain; charset="utf-8" We'll need to export these arrays to the accelerator classes in the next patches. Mark them as 'const' now because they should not be modified at runtime. Note that 'riscv_cpu_options' will also be exported, but can't be marked as 'const', because the properties are changed via qdev_property_add_static(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c15bb572d4..50c2819d68 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1407,7 +1407,7 @@ typedef struct RISCVCPUMultiExtConfig { {.name =3D _name, .offset =3D CPU_CFG_OFFSET(_prop), \ .enabled =3D _defval} =20 -static RISCVCPUMultiExtConfig riscv_cpu_extensions[] =3D { +static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true), @@ -1469,7 +1469,7 @@ static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { DEFINE_PROP_END_OF_LIST(), }; =20 -static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] =3D { +static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] =3D { MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false), MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false), MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false), @@ -1487,7 +1487,7 @@ static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]= =3D { }; =20 /* These are experimental so mark with 'x-' */ -static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] =3D { +static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] =3D { /* ePMP 0.9.3 */ MULTI_EXT_CFG_BOOL("x-epmp", epmp, false), MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false), @@ -1558,7 +1558,7 @@ static void cpu_get_multi_ext_cfg(Object *obj, Visito= r *v, const char *name, } =20 static void cpu_add_multi_ext_prop(Object *cpu_obj, - RISCVCPUMultiExtConfig *multi_cfg) + const RISCVCPUMultiExtConfig *multi_cfg) { object_property_add(cpu_obj, multi_cfg->name, "bool", cpu_get_multi_ext_cfg, @@ -1594,11 +1594,13 @@ static void cpu_set_cfg_unavailable(Object *obj, Vi= sitor *v, #endif =20 static void riscv_cpu_add_multiext_prop_array(Object *obj, - RISCVCPUMultiExtConfig *arra= y) + const RISCVCPUMultiExtConfig *arra= y) { + const RISCVCPUMultiExtConfig *prop; + g_assert(array); =20 - for (RISCVCPUMultiExtConfig *prop =3D array; prop && prop->name; prop+= +) { + for (prop =3D array; prop && prop->name; prop++) { cpu_add_multi_ext_prop(obj, prop); } } @@ -1622,11 +1624,13 @@ static void riscv_cpu_add_kvm_unavail_prop(Object *= obj, const char *prop_name) } =20 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, - RISCVCPUMultiExtConfig *a= rray) + const RISCVCPUMultiExtConfig *arra= y) { + const RISCVCPUMultiExtConfig *prop; + g_assert(array); =20 - for (RISCVCPUMultiExtConfig *prop =3D array; prop && prop->name; prop+= +) { + for (prop =3D array; prop && prop->name; prop++) { riscv_cpu_add_kvm_unavail_prop(obj, prop->name); } } @@ -1689,7 +1693,7 @@ static void riscv_init_max_cpu_extensions(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - RISCVCPUMultiExtConfig *prop; + const RISCVCPUMultiExtConfig *prop; =20 /* Enable RVG, RVJ and RVV that are disabled by default */ set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); --=20 2.41.0 From nobody Thu Nov 28 08:03:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([177.94.15.194]) by smtp.gmail.com with ESMTPSA id n21-20020a9d6f15000000b006b75242d6c3sm6229228otq.38.2023.09.06.02.17.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 02:17:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693991841; x=1694596641; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6rHDFPJrf0c/Fy4Rb2+8QulPbw+iTlttcjHCMhybzn0=; b=jaJh1KZMndURe6meY7jarsE0HXCBwc2yfkENJVg4vQ31PUFPH9M2/EeDd95EDoaA0q D5nqcNZN4Y4bBxm6hsH6kzbSfskXS/njl02dnmR/Le26oE/U1/d8aIf7Vu2EjhBsDJjG 5Ke7dHRTfTb+3vu+b/JXs2rMzHD2CxVVDkVlwft7pw9a2/pQRACjrWgnG09S+uZoZVdr VV5qXYeLnG+Kz8WmbVzIzBC4lk+hktL2LxRxP1KtzjafMCu0aFaQJlgBYa06Vl1f3fXb IVlVQoHovI4nbxLcU67QUx3vFN1CseSreuuXvfUkrGU+9rOHxA0Q3nXdE5a7+ARcd4/E sXxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693991841; x=1694596641; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6rHDFPJrf0c/Fy4Rb2+8QulPbw+iTlttcjHCMhybzn0=; b=MQT7PbvfrTPC/mJvFavfzOm+IMxB2p1e1EfWq0ak0IFmhutE7pUqxDDcC2sdAz9yBs G2qyq2e+gcynPlhsBV93zp85r7B6U9InTShClASAcof0iSbJFy0Tlu27gDp2JRfymVi1 8Jj5pBIy6ektLBk8C+VecODFxQvTSlDlZbGbTNRIuhxR+tEft08//nSiY5FTiRVevGRo fo1ZUzmB2DGJTbCACjKEBHFR/wz4kPhRy4zbmGGdFxI1bJ8/0auPn2M6wU06TUKYZQa/ JND+gWdrWPgi/NZaW1ll3FgZJjzIJ69UayUGW+rbH/CXgRBko8+U+YJxWnNuFiAVIHXV KKOw== X-Gm-Message-State: AOJu0YxO9yKYE6SfcVIhXBiXc59vH8oXurD77p57dD4McQrvsFtzUjEb 9GZNtsoSY656s0sX5sylQIzAQ94whYMMiHudaTQ= X-Google-Smtp-Source: AGHT+IHDs3Rft6MgHJKttgMv1cELc+8yxkXMcr+pvNPWEPfk7QiAKaNL9L4I7IT85b8Yo3CKJW24TQ== X-Received: by 2002:a05:6870:e2d4:b0:1bf:4a66:d54f with SMTP id w20-20020a056870e2d400b001bf4a66d54fmr18433900oad.56.1693991841546; Wed, 06 Sep 2023 02:17:21 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 08/19] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c Date: Wed, 6 Sep 2023 06:16:35 -0300 Message-ID: <20230906091647.1667171-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com> References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1693991905404100001 Content-Type: text/plain; charset="utf-8" We'll introduce the KVM accelerator class with a 'cpu_instance_init' implementation that is going to be invoked during the common riscv_cpu_post_init() (via accel_cpu_instance_init()). This instance_init will execute KVM exclusive code that TCG doesn't care about, such as adding KVM specific properties, initing registers using a KVM scratch CPU and so on. The core of the forementioned cpu_instance_init impl is the current riscv_cpu_add_kvm_properties() that is being used by the common code via riscv_cpu_add_user_properties() in cpu.c. Move it to kvm.c, together will all the relevant artifacts, exporting and renaming it to kvm_riscv_cpu_add_kvm_properties() so cpu.c can keep using it for now. To make this work we'll need to export riscv_cpu_extensions, riscv_cpu_vendor_exts and riscv_cpu_experimental_exts from cpu.c as well. The TCG accelerator will also need to access those in the near future so this export will benefit us in the long run. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 89 +++------------------------------------- target/riscv/cpu.h | 14 +++++++ target/riscv/kvm.c | 68 +++++++++++++++++++++++++++++- target/riscv/kvm_riscv.h | 2 +- 4 files changed, 88 insertions(+), 85 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 50c2819d68..0dc9b3201d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1370,7 +1370,7 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { * change MISA bits during realize() (RVG enables MISA * bits but the user is warned about it). */ -static void riscv_cpu_add_misa_properties(Object *cpu_obj) +void riscv_cpu_add_misa_properties(Object *cpu_obj) { int i; =20 @@ -1397,17 +1397,11 @@ static void riscv_cpu_add_misa_properties(Object *c= pu_obj) } } =20 -typedef struct RISCVCPUMultiExtConfig { - const char *name; - uint32_t offset; - bool enabled; -} RISCVCPUMultiExtConfig; - #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \ {.name =3D _name, .offset =3D CPU_CFG_OFFSET(_prop), \ .enabled =3D _defval} =20 -static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] =3D { +const RISCVCPUMultiExtConfig riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true), @@ -1469,7 +1463,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_extensi= ons[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 -static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] =3D { +const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] =3D { MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false), MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false), MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false), @@ -1487,7 +1481,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_vendor_= exts[] =3D { }; =20 /* These are experimental so mark with 'x-' */ -static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] =3D { +const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] =3D { /* ePMP 0.9.3 */ MULTI_EXT_CFG_BOOL("x-epmp", epmp, false), MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false), @@ -1513,7 +1507,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_experim= ental_exts[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 -static Property riscv_cpu_options[] =3D { +Property riscv_cpu_options[] =3D { DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), =20 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), @@ -1574,25 +1568,6 @@ static void cpu_add_multi_ext_prop(Object *cpu_obj, multi_cfg->enabled); } =20 -#ifndef CONFIG_USER_ONLY -static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, - const char *name, - void *opaque, Error **errp) -{ - const char *propname =3D opaque; - bool value; - - if (!visit_type_bool(v, name, &value, errp)) { - return; - } - - if (value) { - error_setg(errp, "extension %s is not available with KVM", - propname); - } -} -#endif - static void riscv_cpu_add_multiext_prop_array(Object *obj, const RISCVCPUMultiExtConfig *arra= y) { @@ -1605,58 +1580,6 @@ static void riscv_cpu_add_multiext_prop_array(Object= *obj, } } =20 -#ifndef CONFIG_USER_ONLY -static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_n= ame) -{ - /* Check if KVM created the property already */ - if (object_property_find(obj, prop_name)) { - return; - } - - /* - * Set the default to disabled for every extension - * unknown to KVM and error out if the user attempts - * to enable any of them. - */ - object_property_add(obj, prop_name, "bool", - NULL, cpu_set_cfg_unavailable, - NULL, (void *)prop_name); -} - -static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, - const RISCVCPUMultiExtConfig *arra= y) -{ - const RISCVCPUMultiExtConfig *prop; - - g_assert(array); - - for (prop =3D array; prop && prop->name; prop++) { - riscv_cpu_add_kvm_unavail_prop(obj, prop->name); - } -} - -static void riscv_cpu_add_kvm_properties(Object *obj) -{ - Property *prop; - DeviceState *dev =3D DEVICE(obj); - - kvm_riscv_init_user_properties(obj); - riscv_cpu_add_misa_properties(obj); - - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts); - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts); - - for (prop =3D riscv_cpu_options; prop && prop->name; prop++) { - /* Check if KVM created the property already */ - if (object_property_find(obj, prop->name)) { - continue; - } - qdev_property_add_static(dev, prop); - } -} -#endif - /* * Add CPU properties with user-facing flags. * @@ -1669,7 +1592,7 @@ static void riscv_cpu_add_user_properties(Object *obj) riscv_add_satp_mode_properties(obj); =20 if (kvm_enabled()) { - riscv_cpu_add_kvm_properties(obj); + kvm_riscv_cpu_add_kvm_properties(obj); return; } #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2ac00a0304..b9c4bea3f7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -22,6 +22,7 @@ =20 #include "hw/core/cpu.h" #include "hw/registerfields.h" +#include "hw/qdev-properties.h" #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" #include "qom/object.h" @@ -713,6 +714,19 @@ bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_of= fset); int cpu_cfg_ext_get_min_version(uint32_t ext_offset); void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu); =20 +typedef struct RISCVCPUMultiExtConfig { + const char *name; + uint32_t offset; + bool enabled; +} RISCVCPUMultiExtConfig; + +extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; +extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; +extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; +extern Property riscv_cpu_options[]; + +void riscv_cpu_add_misa_properties(Object *cpu_obj); + /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; =20 diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index b4d8d7a46c..7dac01374f 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -343,6 +343,52 @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU = *cpu, CPUState *cs) } } =20 +static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, + const char *name, + void *opaque, Error **errp) +{ + const char *propname =3D opaque; + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + if (value) { + error_setg(errp, "extension %s is not available with KVM", + propname); + } +} + +static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_n= ame) +{ + /* Check if KVM created the property already */ + if (object_property_find(obj, prop_name)) { + return; + } + + /* + * Set the default to disabled for every extension + * unknown to KVM and error out if the user attempts + * to enable any of them. + */ + object_property_add(obj, prop_name, "bool", + NULL, cpu_set_cfg_unavailable, + NULL, (void *)prop_name); +} + +static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, + const RISCVCPUMultiExtConfig *arra= y) +{ + const RISCVCPUMultiExtConfig *prop; + + g_assert(array); + + for (prop =3D array; prop && prop->name; prop++) { + riscv_cpu_add_kvm_unavail_prop(obj, prop->name); + } +} + static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) { int i; @@ -752,7 +798,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, = KVMScratchCPU *kvmcpu) } } =20 -void kvm_riscv_init_user_properties(Object *cpu_obj) +static void riscv_init_user_properties(Object *cpu_obj) { RISCVCPU *cpu =3D RISCV_CPU(cpu_obj); KVMScratchCPU kvmcpu; @@ -1228,6 +1274,26 @@ void kvm_riscv_aia_create(MachineState *machine, uin= t64_t group_shift, kvm_msi_via_irqfd_allowed =3D kvm_irqfds_enabled(); } =20 +void kvm_riscv_cpu_add_kvm_properties(Object *obj) +{ + DeviceState *dev =3D DEVICE(obj); + + riscv_init_user_properties(obj); + riscv_cpu_add_misa_properties(obj); + + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts); + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts); + + for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { + /* Check if KVM created the property already */ + if (object_property_find(obj, prop->name)) { + continue; + } + qdev_property_add_static(dev, prop); + } +} + static void riscv_host_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index de8c209ebc..f6501e68e2 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -19,7 +19,7 @@ #ifndef QEMU_KVM_RISCV_H #define QEMU_KVM_RISCV_H =20 -void kvm_riscv_init_user_properties(Object *cpu_obj); +void kvm_riscv_cpu_add_kvm_properties(Object *obj); void kvm_riscv_reset_vcpu(RISCVCPU *cpu); void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, --=20 2.41.0 From nobody Thu Nov 28 08:03:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([177.94.15.194]) by smtp.gmail.com with ESMTPSA id n21-20020a9d6f15000000b006b75242d6c3sm6229228otq.38.2023.09.06.02.17.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 02:17:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693991845; x=1694596645; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g5E9LLyNurxOieuuNS1GPdHvFJKI2dYtdPNFC2nvFyI=; b=R4O3hV5e95MoiAbVvsuiMVN/srlM6xvM+cPRAtZnXbtT/lGwGVf+r/L+gxyCrYYBx8 NFjo0EdnSgNmoCDNcawAusvfVsBjapi4ZqSCGqtD2TtCRpzhvqRJI6M6wk819URR3nPI 8zZvespzo4CQONFPcsvi8so74ReTJlhNbiN7Yiz3e+ITnWFXtcxNRTVBQbxQBMeGUgyn Fq9DlhyOyCbNzQB9NmES8QfF5Zpf+XdvRxLEIiibjonaadQr8vGZGTdZrjlyGQKbVwhj oy9OY2mgtRFoNsscGgkO61eWRrBzOFl1y5Fd1XBiqh9xSwXoLfWPj4dJnXkjJ+y9wNj6 KfJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693991845; x=1694596645; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g5E9LLyNurxOieuuNS1GPdHvFJKI2dYtdPNFC2nvFyI=; b=HoMdBWt0eYYd4weNytiYKoB+2E5mo/3CZN3HT2CPa7+Z0+60ky7YMK6fP9Z/KsxvHu urDIeyT+EoTwQmeQHsMFfjpIgn6KzfDvtx0saEYOkiAEfPq48QPS+Qt3Z/5fvW5f/kVD bNgbpeo/lQn8zp3S4HwaAsqQ4bSJzgZNqYYCir0lU3XU3oOaocWw8+5tkXRJjfoTDSez mj6PI+aosD8YmG/c/Z0/toW/H/CDi+gtjOBb54VeJYXwjxOZ7RfTv1GmeYa7uyCuyOtp dA3NTAjgNVK7asWFMps3wwTdB/ZCJHmqsGytnIGN3duMCjCe2yYXwi5/E2/NJZtHr6ed NMAA== X-Gm-Message-State: AOJu0YzVfC8y/GnTmwsx30c2Tv976IhsJ0/R54b4a6MURmgDYRRn8Ht3 NI7R30fATIPLeqBxqlhhO/PSze6V8ZFOKdncwXc= X-Google-Smtp-Source: AGHT+IHVrzotwCtpzjDsNAyJ6JLgNxIpWI6aqaoPIk8jUysidX88bHXc325peq9uvaWtwqeEoPeIJA== X-Received: by 2002:a9d:6659:0:b0:6bd:7252:9db1 with SMTP id q25-20020a9d6659000000b006bd72529db1mr16592617otm.11.1693991844801; Wed, 06 Sep 2023 02:17:24 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 09/19] target/riscv: make riscv_add_satp_mode_properties() public Date: Wed, 6 Sep 2023 06:16:36 -0300 Message-ID: <20230906091647.1667171-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com> References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1693991898915100001 Content-Type: text/plain; charset="utf-8" This function is used for both accelerators. Make it public, and call it from kvm_riscv_cpu_add_kvm_properties(). This will make it easier to split KVM specific code for the KVM accelerator class in the next patch. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 5 ++--- target/riscv/cpu.h | 1 + target/riscv/kvm.c | 1 + 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0dc9b3201d..50be127f36 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1115,7 +1115,7 @@ static void cpu_riscv_set_satp(Object *obj, Visitor *= v, const char *name, satp_map->init |=3D 1 << satp; } =20 -static void riscv_add_satp_mode_properties(Object *obj) +void riscv_add_satp_mode_properties(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); =20 @@ -1589,12 +1589,11 @@ static void riscv_cpu_add_multiext_prop_array(Objec= t *obj, static void riscv_cpu_add_user_properties(Object *obj) { #ifndef CONFIG_USER_ONLY - riscv_add_satp_mode_properties(obj); - if (kvm_enabled()) { kvm_riscv_cpu_add_kvm_properties(obj); return; } + riscv_add_satp_mode_properties(obj); #endif =20 riscv_cpu_add_misa_properties(obj); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b9c4bea3f7..950c2301f2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -726,6 +726,7 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_experimen= tal_exts[]; extern Property riscv_cpu_options[]; =20 void riscv_cpu_add_misa_properties(Object *cpu_obj); +void riscv_add_satp_mode_properties(Object *obj); =20 /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 7dac01374f..ef6b2cfffe 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -1279,6 +1279,7 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj) DeviceState *dev =3D DEVICE(obj); =20 riscv_init_user_properties(obj); + riscv_add_satp_mode_properties(obj); riscv_cpu_add_misa_properties(obj); =20 riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); --=20 2.41.0 From nobody Thu Nov 28 08:03:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1693992107; cv=none; d=zohomail.com; s=zohoarc; b=elzzTMo9OijSerua8CrOuBJRu5UyvFB9O6t560SdTOnueNqihEGI3t7l1kL71nZoX+cCRyAUNMTjtOedYgnbadiwgxrjVziOQScfjhC65NZxz2qGJy17Z+EBsPDJu83rMqK7M9HYAvfVlbx3tjB6E6tAr5SLu6tLj5FwapxsL/c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693992107; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GNwYRcF/ah5M2Lkpnd1nk5/sQynl6I3tpewm61MeLZQ=; b=g3Il+uG1V/RLXHRDbmbShGbvtrdku7sty4eeJiwEs/UO5D3YSVtNq9H3cgBubd1XkySo1d/zFwiYAL/MuOWMwSffkxvx6oCL8v4m0URka+wGw3NUcDQnRpkxMZhrkFgIPz3Qye9qnSqOn3TNV7UU/4XWrL8m71HhT5CwMYa/NhE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693992107265815.5374381122294; Wed, 6 Sep 2023 02:21:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qdofG-0003bz-FN; Wed, 06 Sep 2023 05:17:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qdofF-0003YV-AO for qemu-devel@nongnu.org; Wed, 06 Sep 2023 05:17:33 -0400 Received: from mail-oa1-x2d.google.com ([2001:4860:4864:20::2d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qdofB-0005mb-LC for qemu-devel@nongnu.org; Wed, 06 Sep 2023 05:17:32 -0400 Received: by mail-oa1-x2d.google.com with SMTP id 586e51a60fabf-1c0fcbf7ae4so2863382fac.0 for ; Wed, 06 Sep 2023 02:17:29 -0700 (PDT) Received: from grind.. ([177.94.15.194]) by smtp.gmail.com with ESMTPSA id n21-20020a9d6f15000000b006b75242d6c3sm6229228otq.38.2023.09.06.02.17.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 02:17:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693991848; x=1694596648; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GNwYRcF/ah5M2Lkpnd1nk5/sQynl6I3tpewm61MeLZQ=; b=o6wL7xJ8RjxOvcIWRf1OTfKJtc6uorbwRZcvxOC5BiqomUwLhuxmKzxCmsX+1KENVb atRg5fYlH0ldpkM2O94ZvP5vlixZN8WZHnjmTRU5w7sQy0OpuPrHXTxpRqDjYdmZG0yG vJE25PypzLFVSBqlcELTN+KaBWDSJHoG1fLMCgqqrDzSXXVEqFEyJLl2/on8ynfs6j5O G0TkhIH36ambIIgS/OQWj6L7QYYBfWFOMWHEhEXf8YiGtWFOOUSx03jgnk7kLoCbwcpJ aKFEE/nNXQCdEWAHPOYx+gDWm8nK3HQ3dS6O1sjsnFRz3pF8ae3T7kr2AvDJ4e+ygvyQ eOJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693991848; x=1694596648; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GNwYRcF/ah5M2Lkpnd1nk5/sQynl6I3tpewm61MeLZQ=; b=dnUhDp7pzRG2CmBP9vj4IXgK/wQN2w71JmpPXxCraeThMoOqyJFMLkb2leMGgw1Odp aiyPJasKi8HIeyLFsSmfMw5dWtFA0brkPHpM7kyuQOKGHiVrkh3I5htodSRs+dGTRJUN Oz+IkOm641q9jkaRXFAYoY+imTg1ZVA8zgwWPhJZM/niJKZho7cxceCWndu6l4RD9cnK /9tKhCD08aVo3gNCrdU91oCs8uN1LORLO+AiIfyQfDEjOC7qlO+UuW8liRyTGZYKWNVU K7L+c8z//rgY/GnHasolyyZv9eg3ZV8Z8sa+foRXI2ZIBBexnvyt5vWe/BuzbAruSBzQ ScTw== X-Gm-Message-State: AOJu0YzdllmYctmmRf3pFmFDuhlu6zrIcZYYUZpprkMSFnFSGWvq+7iS R6e6XP/HuHqHx9/XwB1JtMw8SJSvH91/BVi+0nQ= X-Google-Smtp-Source: AGHT+IHFQ4EkSxqGoIHbB3RTkajHV65iDPmkwyK8//RmWZ/Es18IkKBG7rDeZKso01u/y6Hc30fE8Q== X-Received: by 2002:a05:6870:c21e:b0:1bb:7d24:eabb with SMTP id z30-20020a056870c21e00b001bb7d24eabbmr18856215oae.0.1693991847936; Wed, 06 Sep 2023 02:17:27 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 10/19] target/riscv: remove kvm-stub.c Date: Wed, 6 Sep 2023 06:16:37 -0300 Message-ID: <20230906091647.1667171-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com> References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1693992109487100003 Content-Type: text/plain; charset="utf-8" This file is not needed for some time now. All the stubs implemented in it (kvm_riscv_reset_vcpu() and kvm_riscv_set_irq()) are wrapped in 'if kvm_enabled()' blocks that the compiler will rip it out in non-KVM builds. We'll also add non-KVM stubs for all functions declared in kvm_riscv.h. All stubs are implemented as g_asserted_not_reached(), meaning that we won't support them in non-KVM builds. This is done by other kvm headers like kvm_arm.h and kvm_ppc.h. Signed-off-by: Daniel Henrique Barboza --- target/riscv/kvm-stub.c | 30 ------------------------------ target/riscv/kvm_riscv.h | 31 +++++++++++++++++++++++++++++++ target/riscv/meson.build | 2 +- 3 files changed, 32 insertions(+), 31 deletions(-) delete mode 100644 target/riscv/kvm-stub.c diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c deleted file mode 100644 index 4e8fc31a21..0000000000 --- a/target/riscv/kvm-stub.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * QEMU KVM RISC-V specific function stubs - * - * Copyright (c) 2020 Huawei Technologies Co., Ltd - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or - * more details. - * - * You should have received a copy of the GNU General Public License along= with - * this program. If not, see . - */ -#include "qemu/osdep.h" -#include "cpu.h" -#include "kvm_riscv.h" - -void kvm_riscv_reset_vcpu(RISCVCPU *cpu) -{ - abort(); -} - -void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) -{ - abort(); -} diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index f6501e68e2..c9ecd9a967 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -19,6 +19,7 @@ #ifndef QEMU_KVM_RISCV_H #define QEMU_KVM_RISCV_H =20 +#ifdef CONFIG_KVM void kvm_riscv_cpu_add_kvm_properties(Object *obj); void kvm_riscv_reset_vcpu(RISCVCPU *cpu); void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); @@ -27,5 +28,35 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_= t group_shift, uint64_t aplic_base, uint64_t imsic_base, uint64_t guest_num); void riscv_kvm_aplic_request(void *opaque, int irq, int level); +#else +static inline void kvm_riscv_cpu_add_kvm_properties(Object *obj) +{ + g_assert_not_reached(); +} + +static inline void kvm_riscv_reset_vcpu(RISCVCPU *cpu) +{ + g_assert_not_reached(); +} + +static inline void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) +{ + g_assert_not_reached(); +} + +static inline void kvm_riscv_aia_create(MachineState *machine, + uint64_t group_shift, uint64_t aia_irq_num, + uint64_t aia_msi_num, uint64_t aplic_base, + uint64_t imsic_base, uint64_t guest_num) +{ + g_assert_not_reached(); +} + +static inline void riscv_kvm_aplic_request(void *opaque, int irq, int leve= l) +{ + g_assert_not_reached(); +} + +#endif /* CONFIG_KVM */ =20 #endif diff --git a/target/riscv/meson.build b/target/riscv/meson.build index f0486183fa..3323b78b84 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -24,7 +24,7 @@ riscv_ss.add(files( 'zce_helper.c', 'vcrypto_helper.c' )) -riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files(= 'kvm-stub.c')) +riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 riscv_system_ss =3D ss.source_set() riscv_system_ss.add(files( --=20 2.41.0 From nobody Thu Nov 28 08:03:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1693991938; cv=none; d=zohomail.com; s=zohoarc; b=SIH2TItKkN2lFuEkvBxsB+aFsuyzPdhuXNMr1JwKr5o8Cn2CRKjp3BRsguqpGCqN6Khrd9feiGP0OMe3Pfgk7Kck2d0y31eFLI0XXvbNSY7rSl6G2QRQWrA6u6HHTguLgW6xpC9lI3TQkNyroqtnAIBMdeM3zFC2O5G/e0WVCjw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693991938; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jLPE27ME7kWpCXfsPyKF7wz0o35+x23NqPSSrbggfyU=; b=JKh5LIIaNl+ywR1KHbmsEy7liBr2zoSysCYV4Q8RkpKXhQZF0gvNqdL/x+EuURpUuWBHrNVqqTANNyFv6Tn8ZV3uzic7fCUffW/lzgENNC7bXG+uri+9iK47ftFifvjzzci2Q5TpVdsQ670aG72roKM6Hs4g/s6fk35POwUfdvg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693991938862502.911507949951; Wed, 6 Sep 2023 02:18:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qdofc-0003lZ-Tl; Wed, 06 Sep 2023 05:17:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qdofH-0003du-EN for qemu-devel@nongnu.org; Wed, 06 Sep 2023 05:17:35 -0400 Received: from mail-oa1-x2b.google.com ([2001:4860:4864:20::2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qdofE-0005na-KW for qemu-devel@nongnu.org; Wed, 06 Sep 2023 05:17:35 -0400 Received: by mail-oa1-x2b.google.com with SMTP id 586e51a60fabf-1c4b4c40281so378290fac.1 for ; Wed, 06 Sep 2023 02:17:32 -0700 (PDT) Received: from grind.. ([177.94.15.194]) by smtp.gmail.com with ESMTPSA id n21-20020a9d6f15000000b006b75242d6c3sm6229228otq.38.2023.09.06.02.17.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 02:17:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693991851; x=1694596651; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jLPE27ME7kWpCXfsPyKF7wz0o35+x23NqPSSrbggfyU=; b=jW40NtBKA8aNhJBjf64WWanX7dV/aD8xXYrsqkTloR4vnr+mlpqKLdjy42olAQ/scZ 7mtEHW7UNIC6r28G7gQmEvpnUfE4M7wJruVg7PqHGpZ0SnLMch77dRMLHxQiJRYfx1Jk qyDFvgn3AJfJanE4iqfw0h80uJVkjZrAcvB2+TEFhi0AJPNr6p4e0nxMjVpqmszeGKRy yAWlauXpD5Wa6hr5wYo8YosdD3Le9K6bnfNyFcVcthQ6Ub69y7OBe/TOlGJYHax098et ppBxpkTQ5L388240IYgGy3BfohROo5EH5Aez8jG5Hi5WE9pahsK8XhA8TqCVbVAEmrZo 7rWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693991851; x=1694596651; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jLPE27ME7kWpCXfsPyKF7wz0o35+x23NqPSSrbggfyU=; b=Y0ZimC5VHnUkQDUEebtSeHexdu6aEA/XbIOWPt+qUgqvuzBZRgsHLSw7TBVX3m6KS2 bsFUnBPUC0c3g7rtUOAsIJKbygB5FL2mv2ffb/Wxg07AQ4zJYe8EyBwxnVw8VJXV5nxG GDT0DId7p7j20+m8HbO+Jw/ez2wu9SY5NKkVm87ATVC6eZMOYELJf8EMkKscv4AbZ2v3 MuMLN8KyS08Pu7o2V9O+akt1Il5rLYWIs3RIc6feqX0+uqccDJfU7lhameJoeY/LR4fX SO66NyJ6/brLI+RUc2pEK28bTEVmaveUyIFN671oW6oeq+4ZVDab+/t8Bk2BJ60QQ/C3 5XcQ== X-Gm-Message-State: AOJu0YyjIEetRdYPfmPmH3Jo9innwXbvpjpOKMqVj+xKVlnnOebkVSGE ZBfVYYr64F0tVEQe/7l7m731HrEn7e7gRKzX2ng= X-Google-Smtp-Source: AGHT+IHMqI9UTvHtjSHNfoacaPQ7vCVbWE6k4UGrV3y/BtW/ry5nK7eIB7mwd0ajawvKvWq5r+hxVA== X-Received: by 2002:a05:6870:391e:b0:1bf:ca72:ce0c with SMTP id b30-20020a056870391e00b001bfca72ce0cmr10412449oap.4.1693991851189; Wed, 06 Sep 2023 02:17:31 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 11/19] target/riscv: introduce KVM AccelCPUClass Date: Wed, 6 Sep 2023 06:16:38 -0300 Message-ID: <20230906091647.1667171-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com> References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1693991939598100001 Content-Type: text/plain; charset="utf-8" Add a KVM accelerator class like we did with TCG. The difference is that, at least for now, we won't be using a realize() implementation for this accelerator. We'll start by assiging kvm_riscv_cpu_add_kvm_properties(), renamed to kvm_cpu_instance_init(), as a 'cpu_instance_init' implementation. Change riscv_cpu_post_init() to invoke accel_cpu_instance_init(), which will go through the 'cpu_instance_init' impl of the current acceleration (if available) and execute it. The end result is that the KVM initial setup, i.e. starting registers and adding its specific properties, will be done via this hook. Add a 'tcg_enabled()' condition in riscv_cpu_post_init() to avoid calling riscv_cpu_add_user_properties() when running KVM. We'll remove this condition when the TCG accel class get its own 'cpu_instance_init' implementation. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 8 +++----- target/riscv/kvm.c | 26 ++++++++++++++++++++++++-- target/riscv/kvm_riscv.h | 6 ------ 3 files changed, 27 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 50be127f36..c8a19be1af 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1219,7 +1219,9 @@ static bool riscv_cpu_has_user_properties(Object *cpu= _obj) =20 static void riscv_cpu_post_init(Object *obj) { - if (riscv_cpu_has_user_properties(obj)) { + accel_cpu_instance_init(CPU(obj)); + + if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) { riscv_cpu_add_user_properties(obj); } =20 @@ -1589,10 +1591,6 @@ static void riscv_cpu_add_multiext_prop_array(Object= *obj, static void riscv_cpu_add_user_properties(Object *obj) { #ifndef CONFIG_USER_ONLY - if (kvm_enabled()) { - kvm_riscv_cpu_add_kvm_properties(obj); - return; - } riscv_add_satp_mode_properties(obj); #endif =20 diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index ef6b2cfffe..492b97d19b 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -31,6 +31,7 @@ #include "sysemu/kvm_int.h" #include "cpu.h" #include "trace.h" +#include "hw/core/accel-cpu.h" #include "hw/pci/pci.h" #include "exec/memattrs.h" #include "exec/address-spaces.h" @@ -1274,8 +1275,9 @@ void kvm_riscv_aia_create(MachineState *machine, uint= 64_t group_shift, kvm_msi_via_irqfd_allowed =3D kvm_irqfds_enabled(); } =20 -void kvm_riscv_cpu_add_kvm_properties(Object *obj) +static void kvm_cpu_instance_init(CPUState *cs) { + Object *obj =3D OBJECT(RISCV_CPU(cs)); DeviceState *dev =3D DEVICE(obj); =20 riscv_init_user_properties(obj); @@ -1287,7 +1289,7 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj) riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts); =20 for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { - /* Check if KVM created the property already */ + /* Check if we have a specific KVM handler for the option */ if (object_property_find(obj, prop->name)) { continue; } @@ -1295,6 +1297,26 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj) } } =20 +static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_instance_init =3D kvm_cpu_instance_init; +} + +static const TypeInfo kvm_cpu_accel_type_info =3D { + .name =3D ACCEL_CPU_NAME("kvm"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D kvm_cpu_accel_class_init, + .abstract =3D true, +}; +static void kvm_cpu_accel_register_types(void) +{ + type_register_static(&kvm_cpu_accel_type_info); +} +type_init(kvm_cpu_accel_register_types); + static void riscv_host_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index c9ecd9a967..8fe6e3e6fb 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -20,7 +20,6 @@ #define QEMU_KVM_RISCV_H =20 #ifdef CONFIG_KVM -void kvm_riscv_cpu_add_kvm_properties(Object *obj); void kvm_riscv_reset_vcpu(RISCVCPU *cpu); void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, @@ -29,11 +28,6 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_= t group_shift, uint64_t guest_num); void riscv_kvm_aplic_request(void *opaque, int irq, int level); #else -static inline void kvm_riscv_cpu_add_kvm_properties(Object *obj) -{ - g_assert_not_reached(); -} - static inline void kvm_riscv_reset_vcpu(RISCVCPU *cpu) { g_assert_not_reached(); --=20 2.41.0 From nobody Thu Nov 28 08:03:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1693992211; cv=none; d=zohomail.com; s=zohoarc; b=Qx11Gr8KZnAXo313HxQnq6TL9gyG8pfo4fPrO4IP3KhVVz0sOT5fhxL+TWye7tMLZJucexSC8Xlt03/XpD9itPoiNQtFloOMoJ2I2aEk+/tCcWCNT1COZhAIC9nutDGK7TTYyKcyDBMyJ8oeycJ1TboXMwgkVBZkgEdiKz4vCrw= ARC-Message-Signature: i=1; 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([177.94.15.194]) by smtp.gmail.com with ESMTPSA id n21-20020a9d6f15000000b006b75242d6c3sm6229228otq.38.2023.09.06.02.17.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 02:17:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693991854; x=1694596654; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6NNHPAb3IB56FNbWTDGypgBzW5eAMUGFB8t2hQ5DMHo=; b=GGm5vp2xfllx1sj/XE/yQycQm87TKhxX+SiCZKCcIqYk3/TET3cxJTN3pWlN2IwpF6 DeZ3cwWsVegO4LZgTbU00U9mbvdnqel4AiuBu5e1tVWhsCtEC0r5FwiD2zJ926OZcUJ/ 1JqX7k6efH20fJ705pixhJvMXDQTyFe9OjeZ8Kjr1z5/QTzNB2KEA7hGRNQNL5XpHf5u K+G+DmYG+MfZmpCkhI/XsPFH4RTXduvM9wTrG4KRlU0BlpyqndvJh9Kjqug+R/phPIlq KVrkVJiGxXG/QFRoVAPcqfu7qmwgujiSBxkjFbcBnkfSXLfR07GTMG+1ZGQ9s7sOazn7 AYEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693991854; x=1694596654; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6NNHPAb3IB56FNbWTDGypgBzW5eAMUGFB8t2hQ5DMHo=; b=JQEqJAtFeiNl3/JR7dwffpAD8MqfrfejiwnicgiU0rwFB1MgDmMXLln60uQ/NHc4Et Nh9vGA8h1GSAsrumuKh+rdRyNU9mJ9knCWMEBi42KgJjNMQy7b1caPKEBHZmyz/8PiLs 5umz0ZQDJy2cgF/uwaBrSWRwKo/jMpXIlsbXx3ozbr/3c9mGamur5DD3faaX/s+qOMTp TCSq/wfAobvYKRrYguSasOa/Lte6t/GDv+1ks3tlcPhn7tyHi7x0yfZ+q3b6i6qMI26Y 5pTlWnqow3O0HELcjOkAzR3xDvCVdibPxpA/NzBu2VffVeU+flkZIoqspGcMjEsmiezb +4yA== X-Gm-Message-State: AOJu0YxKrT2oRJlVJQ0nlQ1O+NGrSJmHR+E/2WEXfGZyW8b24SVWHakH I9FGwNGIQy4Zl5Mp3atIQzYXyfOfyLvIzSA0I54= X-Google-Smtp-Source: AGHT+IGitieUBxwymMohfinobpxVBN8WHs6MZgskInBOsZMAesggv3WsjlIKwpeH3niLu/kp4hrXDQ== X-Received: by 2002:a9d:73ce:0:b0:6bf:ef0:c69 with SMTP id m14-20020a9d73ce000000b006bf0ef00c69mr16099691otk.34.1693991854421; Wed, 06 Sep 2023 02:17:34 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 12/19] target/riscv: move KVM only files to kvm subdir Date: Wed, 6 Sep 2023 06:16:39 -0300 Message-ID: <20230906091647.1667171-13-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com> References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1693992213413100003 Content-Type: text/plain; charset="utf-8" Move the files to a 'kvm' dir to promote more code separation between accelerators and making our lives easier supporting build options such as --disable-tcg. Rename kvm.c to kvm-cpu.c to keep it in line with its TCG counterpart. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei --- hw/intc/riscv_aplic.c | 2 +- hw/riscv/virt.c | 2 +- target/riscv/cpu.c | 2 +- target/riscv/{kvm.c =3D> kvm/kvm-cpu.c} | 0 target/riscv/{ =3D> kvm}/kvm_riscv.h | 0 target/riscv/kvm/meson.build | 1 + target/riscv/meson.build | 2 +- 7 files changed, 5 insertions(+), 4 deletions(-) rename target/riscv/{kvm.c =3D> kvm/kvm-cpu.c} (100%) rename target/riscv/{ =3D> kvm}/kvm_riscv.h (100%) create mode 100644 target/riscv/kvm/meson.build diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 99aae8ccbe..c677b5cfbb 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -32,7 +32,7 @@ #include "target/riscv/cpu.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" -#include "kvm_riscv.h" +#include "kvm/kvm_riscv.h" #include "migration/vmstate.h" =20 #define APLIC_MAX_IDC (1UL << 14) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 3b259b9305..6d9542f0a2 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -35,7 +35,7 @@ #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" -#include "kvm_riscv.h" +#include "kvm/kvm_riscv.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/riscv_aplic.h" #include "hw/intc/riscv_imsic.h" diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c8a19be1af..51567c2f12 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -33,7 +33,7 @@ #include "fpu/softfloat-helpers.h" #include "sysemu/kvm.h" #include "sysemu/tcg.h" -#include "kvm_riscv.h" +#include "kvm/kvm_riscv.h" #include "tcg/tcg.h" =20 /* RISC-V CPU definitions */ diff --git a/target/riscv/kvm.c b/target/riscv/kvm/kvm-cpu.c similarity index 100% rename from target/riscv/kvm.c rename to target/riscv/kvm/kvm-cpu.c diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h similarity index 100% rename from target/riscv/kvm_riscv.h rename to target/riscv/kvm/kvm_riscv.h diff --git a/target/riscv/kvm/meson.build b/target/riscv/kvm/meson.build new file mode 100644 index 0000000000..7e92415091 --- /dev/null +++ b/target/riscv/kvm/meson.build @@ -0,0 +1 @@ +riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm-cpu.c')) diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 3323b78b84..c53962215f 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -24,7 +24,6 @@ riscv_ss.add(files( 'zce_helper.c', 'vcrypto_helper.c' )) -riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 riscv_system_ss =3D ss.source_set() riscv_system_ss.add(files( @@ -39,6 +38,7 @@ riscv_system_ss.add(files( )) =20 subdir('tcg') +subdir('kvm') =20 target_arch +=3D {'riscv': riscv_ss} target_softmmu_arch +=3D {'riscv': riscv_system_ss} --=20 2.41.0 From nobody Thu Nov 28 08:03:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1693991923; cv=none; d=zohomail.com; s=zohoarc; b=NaUPEZxjYC4WNUhfPdfNUJTDh8byAzCx6FREb1RiublbV06zVZQ7V8e4wTcq+LG7LQY9zUuJudG6xNN5B1tZ5q7ozpOX08m91gYRXhHzWj/PdrzabwZy3CpPu2FepNKmxcMHKr6xc6WARLAXk5+2ZczL9pyLPAte4dcLRoENOQ0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693991923; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YpZa0iWCJ6Q3Y42umjT0f9ZHtNXPSNR12/TkaEKqKow=; b=ZE2nKGAsmW+3fKOmaFrVvyVYqTGfwL183IBA1M1v5Vk2LjM8++eLjpif+qyW3VCPqdudaOc4ky0lLRFvw021pHQAZUZJ/aBreWRKynHbh07KwwUP5hcnpPPEryx1Wl0A6lJgN6qNiEiLM64l97XOXucFcGMgx6RElwVAO1X9NpU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693991923225638.1262053075146; Wed, 6 Sep 2023 02:18:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qdofk-0004Hb-25; Wed, 06 Sep 2023 05:18:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qdofP-0003lp-TX for qemu-devel@nongnu.org; Wed, 06 Sep 2023 05:17:54 -0400 Received: from mail-oa1-x2b.google.com ([2001:4860:4864:20::2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qdofL-0005pl-PX for qemu-devel@nongnu.org; Wed, 06 Sep 2023 05:17:41 -0400 Received: by mail-oa1-x2b.google.com with SMTP id 586e51a60fabf-1c4de3b9072so2616087fac.3 for ; Wed, 06 Sep 2023 02:17:39 -0700 (PDT) Received: from grind.. ([177.94.15.194]) by smtp.gmail.com with ESMTPSA id n21-20020a9d6f15000000b006b75242d6c3sm6229228otq.38.2023.09.06.02.17.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 02:17:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693991858; x=1694596658; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YpZa0iWCJ6Q3Y42umjT0f9ZHtNXPSNR12/TkaEKqKow=; b=ILvA0U/8Nc7bMgPFZLahyM2zoKCdSG6YDTQHRc4+uJ3bvLJ1zQeFO/x62R/sc0gafh fBnemxDQou56YehX5hrN04lD3B905p6EG1CZD7UKiVp1fa3TvXUE6AcRy4fqJlHDKKRv LWVHThJsMgAD2ppwDuokVvaVuBKxelDrIAgumXmGGV+Oj0QakjXOEmaOTbd1B3iI+WMN MC/ZmKnrKwlO1D0lYCHjl8i/iyNvadkRiWxQKywfR05g3LgC2bTs/VJJG+gSVPXkmZoM fk596ONNtkK4RqNmyFU3Zh99eUcBg4hf7WQnRyF84nqy0VhXHAXltaIekFQAe8cb+Sh0 Ajlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693991858; x=1694596658; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YpZa0iWCJ6Q3Y42umjT0f9ZHtNXPSNR12/TkaEKqKow=; b=KHbf3ijF05uLdWMwlWvtGlSz70Z9i2tZb1oERENC8qqjDEna4ahh4u674F7schFLH/ RdYDCydmljeCDoYN8mO5/NLsyipTBHSX8/EmSOhf487D6vtY76J4zOTuPydw4WIuNMTw C7aeTJndsT6nBR7WhTBzfyB+XWSLzZsff9DUNL4RTXxXA65q3Wf0PPlsamCoLGAmiI9k kGZCv2QUjAmL+7XKvMz08wYHvVKyuMAR1vTjX82shFdN1yik283nthsBY8lmmG72H2hE OHNadD/LBFQD68NPskXhoix30fbNEWXQfwltCMlP0EeGQOGTJp5a4qLRcqkiFC3dW0r1 9MRQ== X-Gm-Message-State: AOJu0YwQ6YPXES+Jt89mr6rwp80JpcvmSBAUquqJ/tFxQoEi72pN+WrI JDZM2uRTqpVdkV4ydWvjUWycZCbPvnLhC4/GNEA= X-Google-Smtp-Source: AGHT+IGHthC/FNruDYmwhtA3VWtemvpQlUJp6+ZdMThpsvOy+eASv/fzqR5p6qNaENpDwj22GrtzCg== X-Received: by 2002:a05:6870:b48c:b0:1c8:cb3c:8866 with SMTP id y12-20020a056870b48c00b001c8cb3c8866mr18087379oap.46.1693991857528; Wed, 06 Sep 2023 02:17:37 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 13/19] target/riscv/kvm: do not use riscv_cpu_add_misa_properties() Date: Wed, 6 Sep 2023 06:16:40 -0300 Message-ID: <20230906091647.1667171-14-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com> References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1693991924836100007 Content-Type: text/plain; charset="utf-8" riscv_cpu_add_misa_properties() is being used to fill the missing KVM MISA properties but it is a TCG helper that was adapted to do so. We'll move it to tcg-cpu.c in the next patches, meaning that KVM needs to fill the remaining MISA properties on its own. Do not use riscv_cpu_add_misa_properties(). Let's create a new array with all available MISA bits we support that can be read by KVM. The array is zero terminate to allow us to iterate through it without knowing its size. Then, inside kvm_riscv_add_cpu_user_properties(), we'll create all KVM MISA properties as usual and then use this array to add any missing MISA properties with the riscv_cpu_add_kvm_unavail_prop() helper. Note that we're creating misa_bits[], and not using the existing 'riscv_single_letter_exts[]', because the latter is tuned for riscv,isa related functions and it doesn't have all MISA bits we support. Commit 0e2c377023 ("target/riscv: misa to ISA string conversion fix") has the full context. While we're at it, move both satp and the multi-letter extension properties to kvm_riscv_add_cpu_user_properties() as well. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 3 ++- target/riscv/kvm/kvm-cpu.c | 22 ++++++++++++++-------- 3 files changed, 18 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 51567c2f12..665c21af6a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -38,6 +38,8 @@ =20 /* RISC-V CPU definitions */ static const char riscv_single_letter_exts[] =3D "IEMAFDQCPVH"; +const uint32_t misa_bits[] =3D {RVI, RVE, RVM, RVA, RVF, RVD, RVV, + RVC, RVS, RVU, RVH, RVJ, RVG, 0}; =20 struct isa_ext_data { const char *name; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 950c2301f2..24d12a9503 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -43,7 +43,7 @@ #define RV(x) ((target_ulong)1 << (x - 'A')) =20 /* - * Consider updating misa_ext_info_arr[] and misa_ext_cfgs[] + * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] * when adding new MISA bits here. */ #define RVI RV('I') @@ -60,6 +60,7 @@ #define RVJ RV('J') #define RVG RV('G') =20 +extern const uint32_t misa_bits[]; const char *riscv_get_misa_ext_name(uint32_t bit); const char *riscv_get_misa_ext_description(uint32_t bit); =20 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 492b97d19b..44eff1e544 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -394,6 +394,8 @@ static void kvm_riscv_add_cpu_user_properties(Object *c= pu_obj) { int i; =20 + riscv_add_satp_mode_properties(cpu_obj); + for (i =3D 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { KVMCPUConfig *misa_cfg =3D &kvm_misa_ext_cfgs[i]; int bit =3D misa_cfg->offset; @@ -409,6 +411,11 @@ static void kvm_riscv_add_cpu_user_properties(Object *= cpu_obj) misa_cfg->description); } =20 + for (i =3D 0; misa_bits[i] !=3D 0; i++) { + const char *ext_name =3D riscv_get_misa_ext_name(misa_bits[i]); + riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); + } + for (i =3D 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { KVMCPUConfig *multi_cfg =3D &kvm_multi_ext_cfgs[i]; =20 @@ -425,6 +432,10 @@ static void kvm_riscv_add_cpu_user_properties(Object *= cpu_obj) object_property_add(cpu_obj, "cboz_blocksize", "uint16", NULL, kvm_cpu_set_cbomz_blksize, NULL, &kvm_cboz_blocksize); + + riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); + riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); + riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_e= xts); } =20 static int kvm_riscv_get_regs_core(CPUState *cs) @@ -799,7 +810,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, = KVMScratchCPU *kvmcpu) } } =20 -static void riscv_init_user_properties(Object *cpu_obj) +static void riscv_init_kvm_registers(Object *cpu_obj) { RISCVCPU *cpu =3D RISCV_CPU(cpu_obj); KVMScratchCPU kvmcpu; @@ -808,7 +819,6 @@ static void riscv_init_user_properties(Object *cpu_obj) return; } =20 - kvm_riscv_add_cpu_user_properties(cpu_obj); kvm_riscv_init_machine_ids(cpu, &kvmcpu); kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); @@ -1280,13 +1290,9 @@ static void kvm_cpu_instance_init(CPUState *cs) Object *obj =3D OBJECT(RISCV_CPU(cs)); DeviceState *dev =3D DEVICE(obj); =20 - riscv_init_user_properties(obj); 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Rename it to riscv_cpu_set_misa() and make it public. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.c | 34 ++++++++++++++++++---------------- target/riscv/cpu.h | 1 + 2 files changed, 19 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 665c21af6a..cf191d576e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -294,7 +294,7 @@ const char *riscv_cpu_get_trap_name(target_ulong cause,= bool async) } } =20 -static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) +void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) { env->misa_mxl_max =3D env->misa_mxl =3D mxl; env->misa_ext_mask =3D env->misa_ext =3D ext; @@ -399,9 +399,9 @@ static void riscv_any_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; #if defined(TARGET_RISCV32) - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); + riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | = RVU); #elif defined(TARGET_RISCV64) - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); + riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | = RVU); #endif =20 #ifndef CONFIG_USER_ONLY @@ -428,7 +428,7 @@ static void riscv_max_cpu_init(Object *obj) #ifdef TARGET_RISCV32 mlx =3D MXL_RV32; #endif - set_misa(env, mlx, 0); + riscv_cpu_set_misa(env, mlx, 0); env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), mlx =3D=3D MXL_RV32 ? @@ -441,7 +441,7 @@ static void rv64_base_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ - set_misa(env, MXL_RV64, 0); + riscv_cpu_set_misa(env, MXL_RV64, 0); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -453,7 +453,8 @@ static void rv64_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + riscv_cpu_set_misa(env, MXL_RV64, + RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); @@ -471,7 +472,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); + riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -488,7 +489,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); + riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); env->priv_ver =3D PRIV_VERSION_1_11_0; =20 cpu->cfg.ext_zfa =3D true; @@ -519,7 +520,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); + riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); env->priv_ver =3D PRIV_VERSION_1_12_0; =20 /* Enable ISA extensions */ @@ -564,7 +565,7 @@ static void rv128_base_cpu_init(Object *obj) } CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ - set_misa(env, MXL_RV128, 0); + riscv_cpu_set_misa(env, MXL_RV128, 0); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -576,7 +577,7 @@ static void rv32_base_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ - set_misa(env, MXL_RV32, 0); + riscv_cpu_set_misa(env, MXL_RV32, 0); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -588,7 +589,8 @@ static void rv32_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + riscv_cpu_set_misa(env, MXL_RV32, + RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); @@ -606,7 +608,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); + riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -623,7 +625,7 @@ static void rv32_ibex_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); + riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_11_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -641,7 +643,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); + riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -1618,7 +1620,7 @@ static void riscv_init_max_cpu_extensions(Object *obj) const RISCVCPUMultiExtConfig *prop; =20 /* Enable RVG, RVJ and RVV that are disabled by default */ - set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); + riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV= ); =20 for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { isa_ext_update_enabled(cpu, prop->offset, true); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 24d12a9503..cb6372e6e7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -713,6 +713,7 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext= _offset, bool en); bool cpu_cfg_ext_is_user_set(uint32_t ext_offset); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); int cpu_cfg_ext_get_min_version(uint32_t ext_offset); +void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu); =20 typedef struct RISCVCPUMultiExtConfig { --=20 2.41.0 From nobody Thu Nov 28 08:03:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1693991931; cv=none; d=zohomail.com; s=zohoarc; b=aHuZKXBf1tNF09rNiQshAg611WcTfV/jE7mFfzi/pziOmP3Rr/HnmYs/a5/FN7/YCRMe3crRzMfqOg9nru+5SmUdk8MIJiCvN1Iv71B/Ni6D/Fnl9tanJCC2pXYXGeIJo0d4qfVm/ur5Db7WLRo/Pn4J7E2ojATo4bnZYEGQVkk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693991931; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([177.94.15.194]) by smtp.gmail.com with ESMTPSA id n21-20020a9d6f15000000b006b75242d6c3sm6229228otq.38.2023.09.06.02.17.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 02:17:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693991864; x=1694596664; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1QR2Xs+JmPgDNS/3fYGhVtvnBOuhauFZUc4QxGGtjOc=; b=g/xVTTLwL1zu0wqHx3r7RKqt4UdIswCCwN3Islf5r9g7DFLVLPq0jZwEdojiD+7xc3 dcjUHtHljFt/zmow2z317OnWAQG+MhFAJCBYahcR57T6w5bWujT7oRyN3wLQ0Yaj13iY 46/9VmEBySUTaWViSniCZdP/NWoHjZ+vkQCVSTEDgJWEoccbYNqePqHMNmYzguGp3Ycn BWSc55UpKbn9Wbmvm4SJuwVMMph8rhlBdm9xH0nfSmW2Nd0CKLNywAWJfOrEX+f20yi8 X0UHu9/FEYrx+6X4ykr/i9zCDmuTWUhYPzlNEv/XrbgxVfi7+sdn1YJ5VRGe1/XD/LKZ cwzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693991864; x=1694596664; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1QR2Xs+JmPgDNS/3fYGhVtvnBOuhauFZUc4QxGGtjOc=; b=ETxuHxbSRXg2uWEHFiEcudzRksERv+Re9OyK880zMpm4yROB4ksAk+CfqnUSSA0ZbE daHH+/Dyn8GdRqO/uA0GdwzNfySNhJ1y2/6SWeYtouPmGDREOonRsUruvPFsBKPQWpgh 4TU/jI0rBqdbxCdQDOyH+AYJSuIEZgRuz2VbJ+H2mxhJ6IKzN6PItXrm6BDJfzf/EqS8 ubvTDhbZlxmXNu4HXK0RtyvGKEqOShT+foLDehPLnV5F2h41I1WozjgLScP6hBchM2Js 9XSRS8uD0GOE5PKuPyPtHD3KD2CUKQ3/Fd84kHCKU5pH/uIwt6cSCJzYcNKU/qH3Ynts 8HRQ== X-Gm-Message-State: AOJu0YxRXL/eyUPIcil/BlKnkaVgW8JSsLFjS11JDBzCkGmxYqX+cfN5 Ky8G59xhl/u6mmAxqP6RDV3hEFxXCvUMEj4E1BA= X-Google-Smtp-Source: AGHT+IElL30IODn4eQip67JQF2Ebb2g67cB09ffNj8/7fvNorNFCuPB5Rxvf/U4UW/JriBjTjd8eUg== X-Received: by 2002:a05:6830:1147:b0:6b0:c67c:96f3 with SMTP id x7-20020a056830114700b006b0c67c96f3mr14623459otq.18.1693991864105; Wed, 06 Sep 2023 02:17:44 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 15/19] target/riscv/tcg: introduce tcg_cpu_instance_init() Date: Wed, 6 Sep 2023 06:16:42 -0300 Message-ID: <20230906091647.1667171-16-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com> References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1693991933666100005 Content-Type: text/plain; charset="utf-8" tcg_cpu_instance_init() will be the 'cpu_instance_init' impl for the TCG accelerator. It'll be called from within riscv_cpu_post_init(), via accel_cpu_instance_init(), similar to what happens with KVM. In fact, to preserve behavior, the implementation will be similar to what riscv_cpu_post_init() already does. In this patch we'll move riscv_cpu_add_user_properties() and riscv_init_max_cpu_extensions() and all their dependencies to tcg-cpu.c. All multi-extension properties code was moved. The 'multi_ext_user_opts' hash table was also moved to tcg-cpu.c since it's a TCG only structure, meaning that we won't have to worry about initializing a TCG hash table when running a KVM CPU anymore. riscv_cpu_add_user_properties() will remain in cpu.c for now due to how much code it requires to be moved at the same time. We'll do that in the next patch. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 150 ------------------------------------- target/riscv/cpu.h | 1 - target/riscv/tcg/tcg-cpu.c | 149 ++++++++++++++++++++++++++++++++++++ 3 files changed, 149 insertions(+), 151 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cf191d576e..8616c9e2f5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -162,9 +162,6 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaC= ondOps), }; =20 -/* Hash that stores user set extensions */ -static GHashTable *multi_ext_user_opts; - bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) { bool *ext_enabled =3D (void *)&cpu->cfg + ext_offset; @@ -194,12 +191,6 @@ int cpu_cfg_ext_get_min_version(uint32_t ext_offset) g_assert_not_reached(); } =20 -bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) -{ - return g_hash_table_contains(multi_ext_user_opts, - GUINT_TO_POINTER(ext_offset)); -} - const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -280,9 +271,6 @@ static const char * const riscv_intr_names[] =3D { "reserved" }; =20 -static void riscv_cpu_add_user_properties(Object *obj); -static void riscv_init_max_cpu_extensions(Object *obj); - const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { if (async) { @@ -1206,32 +1194,9 @@ static bool riscv_cpu_is_dynamic(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; } =20 -static bool riscv_cpu_has_max_extensions(Object *cpu_obj) -{ - return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) !=3D NULL; -} - -static bool riscv_cpu_has_user_properties(Object *cpu_obj) -{ - if (kvm_enabled() && - object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) !=3D NULL) { - return true; - } - - return riscv_cpu_is_dynamic(cpu_obj); -} - static void riscv_cpu_post_init(Object *obj) { accel_cpu_instance_init(CPU(obj)); - - if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) { - riscv_cpu_add_user_properties(obj); - } - - if (riscv_cpu_has_max_extensions(obj)) { - riscv_init_max_cpu_extensions(obj); - } } =20 static void riscv_cpu_init(Object *obj) @@ -1244,8 +1209,6 @@ static void riscv_cpu_init(Object *obj) qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); #endif /* CONFIG_USER_ONLY */ - - multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); } =20 typedef struct RISCVCPUMisaExtConfig { @@ -1531,119 +1494,6 @@ Property riscv_cpu_options[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 -static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *nam= e, - void *opaque, Error **errp) -{ - const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; - bool value; - - if (!visit_type_bool(v, name, &value, errp)) { - return; - } - - isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value); - - g_hash_table_insert(multi_ext_user_opts, - GUINT_TO_POINTER(multi_ext_cfg->offset), - (gpointer)value); -} - -static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *nam= e, - void *opaque, Error **errp) -{ - const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; - bool value =3D isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offse= t); - - visit_type_bool(v, name, &value, errp); -} - -static void cpu_add_multi_ext_prop(Object *cpu_obj, - const RISCVCPUMultiExtConfig *multi_cfg) -{ - object_property_add(cpu_obj, multi_cfg->name, "bool", - cpu_get_multi_ext_cfg, - cpu_set_multi_ext_cfg, - NULL, (void *)multi_cfg); - - /* - * Set def val directly instead of using - * object_property_set_bool() to save the set() - * callback hash for user inputs. - */ - isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, - multi_cfg->enabled); -} - -static void riscv_cpu_add_multiext_prop_array(Object *obj, - const RISCVCPUMultiExtConfig *arra= y) -{ - const RISCVCPUMultiExtConfig *prop; - - g_assert(array); - - for (prop =3D array; prop && prop->name; prop++) { - cpu_add_multi_ext_prop(obj, prop); - } -} - -/* - * Add CPU properties with user-facing flags. - * - * This will overwrite existing env->misa_ext values with the - * defaults set via riscv_cpu_add_misa_properties(). - */ -static void riscv_cpu_add_user_properties(Object *obj) -{ -#ifndef CONFIG_USER_ONLY - riscv_add_satp_mode_properties(obj); -#endif - - riscv_cpu_add_misa_properties(obj); - - riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); - riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); - riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); - - for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { - qdev_property_add_static(DEVICE(obj), prop); - } -} - -/* - * The 'max' type CPU will have all possible ratified - * non-vendor extensions enabled. - */ -static void riscv_init_max_cpu_extensions(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - const RISCVCPUMultiExtConfig *prop; - - /* Enable RVG, RVJ and RVV that are disabled by default */ - riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV= ); - - for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { - isa_ext_update_enabled(cpu, prop->offset, true); - } - - /* set vector version */ - env->vext_ver =3D VEXT_VERSION_1_00_0; - - /* Zfinx is not compatible with F. Disable it */ - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); - - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); - - if (env->misa_mxl !=3D MXL_RV32) { - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); - } -} - static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cb6372e6e7..a7415338d9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -710,7 +710,6 @@ enum riscv_pmu_event_idx { =20 /* used by tcg/tcg-cpu.c*/ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); -bool cpu_cfg_ext_is_user_set(uint32_t ext_offset); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); int cpu_cfg_ext_get_min_version(uint32_t ext_offset); void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 8698ce4765..c9804b53f8 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -23,12 +23,22 @@ #include "pmu.h" #include "time_helper.h" #include "qapi/error.h" +#include "qapi/visitor.h" #include "qemu/accel.h" #include "qemu/error-report.h" #include "hw/core/accel-cpu.h" #include "hw/core/tcg-cpu-ops.h" #include "tcg/tcg.h" =20 +/* Hash that stores user set extensions */ +static GHashTable *multi_ext_user_opts; + +static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) +{ + return g_hash_table_contains(multi_ext_user_opts, + GUINT_TO_POINTER(ext_offset)); +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -568,6 +578,144 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **e= rrp) return true; } =20 +static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value); + + g_hash_table_insert(multi_ext_user_opts, + GUINT_TO_POINTER(multi_ext_cfg->offset), + (gpointer)value); +} + +static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; + bool value =3D isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offse= t); + + visit_type_bool(v, name, &value, errp); +} + +static void cpu_add_multi_ext_prop(Object *cpu_obj, + const RISCVCPUMultiExtConfig *multi_cfg) +{ + object_property_add(cpu_obj, multi_cfg->name, "bool", + cpu_get_multi_ext_cfg, + cpu_set_multi_ext_cfg, + NULL, (void *)multi_cfg); + + /* + * Set def val directly instead of using + * object_property_set_bool() to save the set() + * callback hash for user inputs. + */ + isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, + multi_cfg->enabled); +} + +static void riscv_cpu_add_multiext_prop_array(Object *obj, + const RISCVCPUMultiExtConfig *arra= y) +{ + const RISCVCPUMultiExtConfig *prop; + + g_assert(array); + + for (prop =3D array; prop && prop->name; prop++) { + cpu_add_multi_ext_prop(obj, prop); + } +} + +/* + * Add CPU properties with user-facing flags. + * + * This will overwrite existing env->misa_ext values with the + * defaults set via riscv_cpu_add_misa_properties(). + */ +static void riscv_cpu_add_user_properties(Object *obj) +{ +#ifndef CONFIG_USER_ONLY + riscv_add_satp_mode_properties(obj); +#endif + + riscv_cpu_add_misa_properties(obj); + + riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); + riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); + riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); + + for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { + qdev_property_add_static(DEVICE(obj), prop); + } +} + +/* + * The 'max' type CPU will have all possible ratified + * non-vendor extensions enabled. + */ +static void riscv_init_max_cpu_extensions(Object *obj) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + const RISCVCPUMultiExtConfig *prop; + + /* Enable RVG, RVJ and RVV that are disabled by default */ + riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV= ); + + for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { + isa_ext_update_enabled(cpu, prop->offset, true); + } + + /* set vector version */ + env->vext_ver =3D VEXT_VERSION_1_00_0; + + /* Zfinx is not compatible with F. Disable it */ + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); + + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); + + if (env->misa_mxl !=3D MXL_RV32) { + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); + } +} + +static bool riscv_cpu_has_max_extensions(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) !=3D NULL; +} + +static bool riscv_cpu_has_user_properties(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; +} + +static void tcg_cpu_instance_init(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + Object *obj =3D OBJECT(cpu); + + if (riscv_cpu_has_user_properties(obj)) { + multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); + riscv_cpu_add_user_properties(obj); + } + + if (riscv_cpu_has_max_extensions(obj)) { + riscv_init_max_cpu_extensions(obj); + } +} + static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) { /* @@ -586,6 +734,7 @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, v= oid *data) AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); =20 acc->cpu_class_init =3D tcg_cpu_class_init; + acc->cpu_instance_init =3D tcg_cpu_instance_init; acc->cpu_realizefn =3D tcg_cpu_realizefn; } =20 --=20 2.41.0 From nobody Thu Nov 28 08:03:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1693992078; cv=none; d=zohomail.com; s=zohoarc; b=Sxx1uAifvAtR/g33g5kO123plZGIWD7WK/perFASk012pgNeSH2EE990JuBG/46/XQrPP+ihh0+NG3Nb3d9L1SNOjl9uXBN1VrK6M4NHyRB08H5bo6JRXnrPMAy52E0lhNeBZjFVL8E/cYZfyvhwoX3kwgjs+5n/ZbTY0yn4RvE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693992078; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xYPq6qx4s6ZZjgcoC1MZVsiyv8qTGFaIklxyrZMhrc0=; b=A2iR6KD3H4WQVeU3m8vNEwcFIIX8xbP8u0eK0eP9Dyr1dIt0ol/VwhBDmzR8JQwjxZ85bzeVMeTSDJlVeTpnP6cUJl66vqe4pG5YYVMLwJOAkhFSvZqEZz+7+GlO7WjyaUU0WHmpuW5iBo866z0MNG16yUVj941hiNmEFzRamYc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693992078770985.2990774926568; Wed, 6 Sep 2023 02:21:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qdogX-0005tO-BM; Wed, 06 Sep 2023 05:18:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qdofh-0004CE-IV for qemu-devel@nongnu.org; Wed, 06 Sep 2023 05:18:02 -0400 Received: from mail-ot1-x336.google.com ([2607:f8b0:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qdofW-0005qb-KO for qemu-devel@nongnu.org; Wed, 06 Sep 2023 05:18:00 -0400 Received: by mail-ot1-x336.google.com with SMTP id 46e09a7af769-6c09d760cb9so707868a34.2 for ; Wed, 06 Sep 2023 02:17:48 -0700 (PDT) Received: from grind.. ([177.94.15.194]) by smtp.gmail.com with ESMTPSA id n21-20020a9d6f15000000b006b75242d6c3sm6229228otq.38.2023.09.06.02.17.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 02:17:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693991867; x=1694596667; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xYPq6qx4s6ZZjgcoC1MZVsiyv8qTGFaIklxyrZMhrc0=; b=AS6E5weLSuASRrm5nA21qSRNEurmhLL93PKZlSTW+DQq+Hzfh6sU40MZliOMeGWXJM yjrgKG9WzwDtRrkHGHFQNCgY1W1Og7ychTIZmk6T1f5UQ3z4SVu8cxjVvLRrHotpeDPJ ar7MXS80/B9j34MNU9Vr/H3Avvb7PXP/BU49NRbMcbmDwD6AZcg7rcCw2OLAh2AuTrBX RdQIGh8iAsGjj2gbIGkALnfhrgKXxijWZV3k2MgyN8+6PCNMFE3kwapaRKiYGfkDJIfy d1z0vV0VqVt0eU914EA9FgBSWP+7OJsEyBpcm3V6MflokyAwxtDb0g7TWbvm/ffcRWXX yncA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693991867; x=1694596667; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xYPq6qx4s6ZZjgcoC1MZVsiyv8qTGFaIklxyrZMhrc0=; b=Yxo4jGanaU7PlThxEHnA7bLrmXTDyECbd6qBTeuc5Kfn3gCRpgHdNPtIID8Dj4jlGz /+slueUGPMjN9DYYIBSZ/mOPX91uBhr5rZlCwJEC06SoAB2vzgGLiUfX0Gv9jrUftWft 6Yyd/o56dYeB/oriLzfXJcXyKJ+h8CckKSLWvTi+WgioSCN0/4Yz8YVxakbhT9UYH/4k J942IPwqr7BjDgxaxJ2u6bTTLFUNkKR5mbfcrAPMwrAJiVbRISAfK2KrNE+u215KYAQw 47HNtnHk43gD7ROTuEGuAeNmYXoHTt5eVtJJJ53atSC6dLgjtLlYoficdcPerISAVWsJ 7E1Q== X-Gm-Message-State: AOJu0YzIaB7wYE6/dylpw1FRZFMJm7Z5NpQISqh6y4Jz1YEJ4HzsdlP1 FL/yZ9CEX+NIAIJfsEah0BTVKQHPZzyGKfFhfY8= X-Google-Smtp-Source: AGHT+IFZ0sGQG1die8gLsXN5BAHh3LA0SYSQa2CWTs8T0O+JktlLCdGtoHHuv9pQmHazuw6I+teLCA== X-Received: by 2002:a05:6830:1147:b0:6b0:c67c:96f3 with SMTP id x7-20020a056830114700b006b0c67c96f3mr14623549otq.18.1693991867380; Wed, 06 Sep 2023 02:17:47 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 16/19] target/riscv/cpu.c: make misa_ext_cfgs[] 'const' Date: Wed, 6 Sep 2023 06:16:43 -0300 Message-ID: <20230906091647.1667171-17-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com> References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::336; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1693992080828100005 Content-Type: text/plain; charset="utf-8" The array isn't marked as 'const' because we're initializing their elements in riscv_cpu_add_misa_properties(), 'name' and 'description' fields. In a closer look we can see that we're not using these 2 fields after creating the MISA properties. And we can create the properties by using riscv_get_misa_ext_name() and riscv_get_misa_ext_description() directly. Remove the 'name' and 'description' fields from RISCVCPUMisaExtConfig and make misa_ext_cfgs[] a const array. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8616c9e2f5..4875feded7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1212,8 +1212,6 @@ static void riscv_cpu_init(Object *obj) } =20 typedef struct RISCVCPUMisaExtConfig { - const char *name; - const char *description; target_ulong misa_bit; bool enabled; } RISCVCPUMisaExtConfig; @@ -1317,7 +1315,7 @@ const char *riscv_get_misa_ext_description(uint32_t b= it) #define MISA_CFG(_bit, _enabled) \ {.misa_bit =3D _bit, .enabled =3D _enabled} =20 -static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { MISA_CFG(RVA, true), MISA_CFG(RVC, true), MISA_CFG(RVD, true), @@ -1344,25 +1342,22 @@ void riscv_cpu_add_misa_properties(Object *cpu_obj) int i; =20 for (i =3D 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { - RISCVCPUMisaExtConfig *misa_cfg =3D &misa_ext_cfgs[i]; + const RISCVCPUMisaExtConfig *misa_cfg =3D &misa_ext_cfgs[i]; int bit =3D misa_cfg->misa_bit; - - misa_cfg->name =3D riscv_get_misa_ext_name(bit); - misa_cfg->description =3D riscv_get_misa_ext_description(bit); + const char *name =3D riscv_get_misa_ext_name(bit); + const char *desc =3D riscv_get_misa_ext_description(bit); =20 /* Check if KVM already created the property */ - if (object_property_find(cpu_obj, misa_cfg->name)) { + if (object_property_find(cpu_obj, name)) { continue; } =20 - object_property_add(cpu_obj, misa_cfg->name, "bool", + object_property_add(cpu_obj, name, "bool", cpu_get_misa_ext_cfg, cpu_set_misa_ext_cfg, NULL, (void *)misa_cfg); - object_property_set_description(cpu_obj, misa_cfg->name, - misa_cfg->description); - object_property_set_bool(cpu_obj, misa_cfg->name, - misa_cfg->enabled, NULL); + object_property_set_description(cpu_obj, name, desc); + object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL); } } =20 --=20 2.41.0 From nobody Thu Nov 28 08:03:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1693992251; cv=none; d=zohomail.com; s=zohoarc; b=KbclESW39Er6/K/PMrvnkpk/PYp6Fbbn/nrzWrvofxx5PrStdgeMxLNH2dxqWjeIOxHquAvEzHFatt2EtvDdRQSA21ynUFQ4u5T6L4vm5TV2B1R7MXPgi1+WiK6s9eoxqcrgAcGiWRy55ULu+9ywSdBtJpyNxC6o3FrXCxVRb7E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693992251; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pI0z5n6k8JFj82RwRV6OxDxoS9H9TghdD+8PMG0vQAU=; b=VyUgx8JOJtV0ZAacG/v3s5ugn6p3RCu2xVEPO6HFx2mUs8An3xUVFib+1sFsUmI01rwbDpZHc9Zpyu+ZvxZ8uCs9cXjov/YpFEpuQvV+FA+VvTzt381E+E1fMJRXOSx2hL6eA3POiKJl4av53+uCWukmN/L4gZBVV27eQuBCkpU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693992251034474.6055977995195; Wed, 6 Sep 2023 02:24:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qdogp-0006oC-I2; Wed, 06 Sep 2023 05:19:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qdofv-0004SI-EE for qemu-devel@nongnu.org; Wed, 06 Sep 2023 05:18:16 -0400 Received: from mail-oa1-x2c.google.com ([2001:4860:4864:20::2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qdofZ-0005qm-2L for qemu-devel@nongnu.org; Wed, 06 Sep 2023 05:18:11 -0400 Received: by mail-oa1-x2c.google.com with SMTP id 586e51a60fabf-1cd327d7cc1so2630537fac.3 for ; Wed, 06 Sep 2023 02:17:52 -0700 (PDT) Received: from grind.. ([177.94.15.194]) by smtp.gmail.com with ESMTPSA id n21-20020a9d6f15000000b006b75242d6c3sm6229228otq.38.2023.09.06.02.17.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 02:17:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693991871; x=1694596671; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pI0z5n6k8JFj82RwRV6OxDxoS9H9TghdD+8PMG0vQAU=; b=L0V+udIgMx16g7DOJGPMtYGuoJuUQM+t9K5Xdfg4Va3sr8kI0NeKLsnReql5dc6Poq Tst0939wzfP8iq7QO3UQKnshoGOFOmhEufAbuziptuAsIZ/+fb/te3y7R0O3vZvq2s/D vy0Uxi52kemTSLc2Y9yVaPhqpJURbXjQhrdMPbgH3Qe28dtzOR3SZMX0ZkYSGyITvzac wIkS8UWccKWdDi9HV4Cp1woKWcz10hs+BsECxUruRkrnJcBVzWSxUhDqdw60r6LRJ68Z LlshyAdkePXj+25/lE+YtXmegB865UJjQJlAPl9JSkGAodcgM1LUwDhxeaEkvCwkDoqq mLgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693991871; x=1694596671; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pI0z5n6k8JFj82RwRV6OxDxoS9H9TghdD+8PMG0vQAU=; b=e7fT2kJFTFFelxAfNTL7wdO/VIvnPFCZbWsaCXBhLra2LE0xAiVW396PuKi9yAzXiQ 6feZfc66takMdo5R9x4dqFhDUUQW7hmS1XWaVchmEdTFnE4O0wFOC9amZq8s13oB7Nsp CtMvyQOE65i9VAn7iVmtW9wfv7AzjyZvJQg/50wL/yDMCv6tNbCoXOIFmubG2QTRbrVc iwqxaMVmBu/07eWhVWlOebZD7vEfP5RNf6Bj81A2Ect8VuNB2XqzMQAeS3aNID5/EnN9 jR9QS5FfRXAGTasIQnGlnErxdGhS0FOvCeBZFaV7rwWnuiSJ41LGEmTHltgegD+l29ly y3OQ== X-Gm-Message-State: AOJu0Yzzc6LLjmUQodchncOTO7A2GmCdhuA97juNh0SjNi2kEenPPbT2 86dMWo3dG5MYAlUhSfSxc+kcJKW1TVkTQ1fnUV8= X-Google-Smtp-Source: AGHT+IGABposOUxTcoNCwde/XVmcFHZovcyWEmjj0xMfjxDoAkQlwSXBpIOFRAd76Zt2tWWR534F/Q== X-Received: by 2002:a05:6870:d05:b0:1d5:15cc:cb67 with SMTP id mk5-20020a0568700d0500b001d515cccb67mr3248362oab.49.1693991870951; Wed, 06 Sep 2023 02:17:50 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 17/19] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c Date: Wed, 6 Sep 2023 06:16:44 -0300 Message-ID: <20230906091647.1667171-18-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com> References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2c.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1693992252713100003 Content-Type: text/plain; charset="utf-8" All code related to MISA TCG properties is also moved. At this point, all TCG properties handling is done in tcg-cpu.c, all KVM properties handling is done in kvm-cpu.c. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 90 -------------------------------------- target/riscv/cpu.h | 1 - target/riscv/tcg/tcg-cpu.c | 90 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 90 insertions(+), 91 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4875feded7..46263e55d5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1211,47 +1211,6 @@ static void riscv_cpu_init(Object *obj) #endif /* CONFIG_USER_ONLY */ } =20 -typedef struct RISCVCPUMisaExtConfig { - target_ulong misa_bit; - bool enabled; -} RISCVCPUMisaExtConfig; - -static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - const RISCVCPUMisaExtConfig *misa_ext_cfg =3D opaque; - target_ulong misa_bit =3D misa_ext_cfg->misa_bit; - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - bool value; - - if (!visit_type_bool(v, name, &value, errp)) { - return; - } - - if (value) { - env->misa_ext |=3D misa_bit; - env->misa_ext_mask |=3D misa_bit; - } else { - env->misa_ext &=3D ~misa_bit; - env->misa_ext_mask &=3D ~misa_bit; - } -} - -static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - const RISCVCPUMisaExtConfig *misa_ext_cfg =3D opaque; - target_ulong misa_bit =3D misa_ext_cfg->misa_bit; - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - bool value; - - value =3D env->misa_ext & misa_bit; - - visit_type_bool(v, name, &value, errp); -} - typedef struct misa_ext_info { const char *name; const char *description; @@ -1312,55 +1271,6 @@ const char *riscv_get_misa_ext_description(uint32_t = bit) return val; } =20 -#define MISA_CFG(_bit, _enabled) \ - {.misa_bit =3D _bit, .enabled =3D _enabled} - -static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { - MISA_CFG(RVA, true), - MISA_CFG(RVC, true), - MISA_CFG(RVD, true), - MISA_CFG(RVF, true), - MISA_CFG(RVI, true), - MISA_CFG(RVE, false), - MISA_CFG(RVM, true), - MISA_CFG(RVS, true), - MISA_CFG(RVU, true), - MISA_CFG(RVH, true), - MISA_CFG(RVJ, false), - MISA_CFG(RVV, false), - MISA_CFG(RVG, false), -}; - -/* - * We do not support user choice tracking for MISA - * extensions yet because, so far, we do not silently - * change MISA bits during realize() (RVG enables MISA - * bits but the user is warned about it). - */ -void riscv_cpu_add_misa_properties(Object *cpu_obj) -{ - int i; - - for (i =3D 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { - const RISCVCPUMisaExtConfig *misa_cfg =3D &misa_ext_cfgs[i]; - int bit =3D misa_cfg->misa_bit; - const char *name =3D riscv_get_misa_ext_name(bit); - const char *desc =3D riscv_get_misa_ext_description(bit); - - /* Check if KVM already created the property */ - if (object_property_find(cpu_obj, name)) { - continue; - } - - object_property_add(cpu_obj, name, "bool", - cpu_get_misa_ext_cfg, - cpu_set_misa_ext_cfg, - NULL, (void *)misa_cfg); - object_property_set_description(cpu_obj, name, desc); - object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL); - } -} - #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \ {.name =3D _name, .offset =3D CPU_CFG_OFFSET(_prop), \ .enabled =3D _defval} diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a7415338d9..c5be917d80 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -726,7 +726,6 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_ex= ts[]; extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; extern Property riscv_cpu_options[]; =20 -void riscv_cpu_add_misa_properties(Object *cpu_obj); void riscv_add_satp_mode_properties(Object *obj); =20 /* CSR function table */ diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c9804b53f8..c23bc0c2e1 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -578,6 +578,96 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **er= rp) return true; } =20 +typedef struct RISCVCPUMisaExtConfig { + target_ulong misa_bit; + bool enabled; +} RISCVCPUMisaExtConfig; + +static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + const RISCVCPUMisaExtConfig *misa_ext_cfg =3D opaque; + target_ulong misa_bit =3D misa_ext_cfg->misa_bit; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + if (value) { + env->misa_ext |=3D misa_bit; + env->misa_ext_mask |=3D misa_bit; + } else { + env->misa_ext &=3D ~misa_bit; + env->misa_ext_mask &=3D ~misa_bit; + } +} + +static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + const RISCVCPUMisaExtConfig *misa_ext_cfg =3D opaque; + target_ulong misa_bit =3D misa_ext_cfg->misa_bit; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + bool value; + + value =3D env->misa_ext & misa_bit; + + visit_type_bool(v, name, &value, errp); +} + +#define MISA_CFG(_bit, _enabled) \ + {.misa_bit =3D _bit, .enabled =3D _enabled} + +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { + MISA_CFG(RVA, true), + MISA_CFG(RVC, true), + MISA_CFG(RVD, true), + MISA_CFG(RVF, true), + MISA_CFG(RVI, true), + MISA_CFG(RVE, false), + MISA_CFG(RVM, true), + MISA_CFG(RVS, true), + MISA_CFG(RVU, true), + MISA_CFG(RVH, true), + MISA_CFG(RVJ, false), + MISA_CFG(RVV, false), + MISA_CFG(RVG, false), +}; + +/* + * We do not support user choice tracking for MISA + * extensions yet because, so far, we do not silently + * change MISA bits during realize() (RVG enables MISA + * bits but the user is warned about it). + */ +static void riscv_cpu_add_misa_properties(Object *cpu_obj) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { + const RISCVCPUMisaExtConfig *misa_cfg =3D &misa_ext_cfgs[i]; + int bit =3D misa_cfg->misa_bit; + const char *name =3D riscv_get_misa_ext_name(bit); + const char *desc =3D riscv_get_misa_ext_description(bit); + + /* Check if KVM already created the property */ + if (object_property_find(cpu_obj, name)) { + continue; + } + + object_property_add(cpu_obj, name, "bool", + cpu_get_misa_ext_cfg, + cpu_set_misa_ext_cfg, + NULL, (void *)misa_cfg); + object_property_set_description(cpu_obj, name, desc); + object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL); + } +} + static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *nam= e, void *opaque, Error **errp) { --=20 2.41.0 From nobody Thu Nov 28 08:03:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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([177.94.15.194]) by smtp.gmail.com with ESMTPSA id n21-20020a9d6f15000000b006b75242d6c3sm6229228otq.38.2023.09.06.02.17.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 02:17:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693991874; x=1694596674; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nnhHU10feLbP8gTUOaImK7HRiAbWhMcKFT+HoMGy5KQ=; b=Ej9wr8squ4H/1ZuEn7bxi+CCfflXVkaYwXIA0rGF2mr4158fGyFLTtKT+b4FZgSPyL EPqsyiSTzA/9/PH3kLTRPWweEAJneDhAU2DCw2Qvp24qPRBN03gHJ6zuRwH95MhQWOJx nixjDGq/Fb8fjL6hygjFQiGxhXyztBwsez+kiLVYAok+4/YsjX/jLSNwQXobFvEaLmMD onv/C1yr+OqMfidm0UDgdv//SH8Q7DpTMpddWjI4g45zB5TIWFjK5C4sO1dkSSBP7Beb ugPvYxYlA6BD8K9sKfwpZjQRdBW+VADDwx7uYiwXTXYm/tlfDUN4aaz22o6dU7qDR8PN sHEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693991874; x=1694596674; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nnhHU10feLbP8gTUOaImK7HRiAbWhMcKFT+HoMGy5KQ=; b=h4BfbmtW2JlwVoM4Vkm49upFJmSIquH1P6u0LNicq/5MpzaPhL+MnlUU4CD4gNfnv6 OAiWpupFkh9Vkh3zMCzG06Kj2mUDxMqAGpkY+prEpk5PVLVgnddVnIxiQPBT8K+eLtY1 dvCuZCK0rR6drGIQEnh6ZtPWgUeJ2u3mUZTt9pAM3ft2J8hAJG9HfiQ7j1IBbrT5lVes f/sOLfzznVZP7l0wT/QZwJ47/uun7rUE01Eez1b4Yc5Y9L/oAQVq7i7GfQLmoFCNSBpd McgVwHqePhktBl/9NEPkBm2dPR4AuN4yvMRLlnpMo6NTKn4I+UIERMTO/wFoe5R7XKNC 3VCQ== X-Gm-Message-State: AOJu0YySXKgWuvBDt2ZGKzHMk7ElsT2xxFRcTjnwGuwqCfMOudHTZwjd j+kiFY1tNtNjca+mvDlDHfw7zMfpKu7dOqkgBlg= X-Google-Smtp-Source: AGHT+IF2sFCXj2WbSIrOCN8kuOB/aM5+wdtCJJ1ttLoSZs/fI8BaspemtXd3TAZHnfoMVvqzrLwg2A== X-Received: by 2002:a05:6830:3482:b0:6bc:aec3:6eb1 with SMTP id c2-20020a056830348200b006bcaec36eb1mr13062441otu.1.1693991874062; Wed, 06 Sep 2023 02:17:54 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 18/19] target/riscv/cpu.c: export isa_edata_arr[] Date: Wed, 6 Sep 2023 06:16:45 -0300 Message-ID: <20230906091647.1667171-19-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com> References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1693992228691100001 Content-Type: text/plain; charset="utf-8" This array will be read by the TCG accel class, allowing it to handle priv spec verifications on its own. The array will remain here in cpu.c because it's also used by the riscv,isa string function. To export it we'll finish it with an empty element since ARRAY_SIZE() won't work outside of cpu.c. Get rid of its ARRAY_SIZE() usage now to alleviate the changes for the next patch. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 47 +++++++++++++++++++++------------------------- target/riscv/cpu.h | 7 +++++++ 2 files changed, 28 insertions(+), 26 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 46263e55d5..e97ba3df93 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -41,15 +41,6 @@ static const char riscv_single_letter_exts[] =3D "IEMAFD= QCPVH"; const uint32_t misa_bits[] =3D {RVI, RVE, RVM, RVA, RVF, RVD, RVV, RVC, RVS, RVU, RVH, RVJ, RVG, 0}; =20 -struct isa_ext_data { - const char *name; - int min_version; - int ext_enable_offset; -}; - -#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ - {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} - /* * From vector_helper.c * Note that vector data is stored in host-endian 64-bit chunks, @@ -61,6 +52,9 @@ struct isa_ext_data { #define BYTE(x) (x) #endif =20 +#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ + {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} + /* * Here are the ordering rules of extension naming defined by RISC-V * specification : @@ -81,7 +75,7 @@ struct isa_ext_data { * Single letter extensions are checked in riscv_cpu_validate_misa_priv() * instead. */ -static const struct isa_ext_data isa_edata_arr[] =3D { +const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), @@ -160,6 +154,8 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempa= ir), ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaC= ondOps), + + DEFINE_PROP_END_OF_LIST(), }; =20 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) @@ -178,14 +174,14 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t e= xt_offset, bool en) =20 int cpu_cfg_ext_get_min_version(uint32_t ext_offset) { - int i; + const RISCVIsaExtData *edata; =20 - for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_edata_arr[i].ext_enable_offset !=3D ext_offset) { + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (edata->ext_enable_offset !=3D ext_offset) { continue; } =20 - return isa_edata_arr[i].min_version; + return edata->min_version; } =20 g_assert_not_reached(); @@ -932,22 +928,21 @@ static void riscv_cpu_disas_set_info(CPUState *s, dis= assemble_info *info) void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) { CPURISCVState *env =3D &cpu->env; - int i; + const RISCVIsaExtData *edata; =20 /* Force disable extensions if priv spec version does not match */ - for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) && - (env->priv_ver < isa_edata_arr[i].min_version)) { - isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset, - false); + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && + (env->priv_ver < edata->min_version)) { + isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); #ifndef CONFIG_USER_ONLY warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx " because privilege spec version does not match", - isa_edata_arr[i].name, env->mhartid); + edata->name, env->mhartid); #else warn_report("disabling %s extension because " "privilege spec version does not match", - isa_edata_arr[i].name); + edata->name); #endif } } @@ -1619,13 +1614,13 @@ static void riscv_cpu_class_init(ObjectClass *c, vo= id *data) static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) { + const RISCVIsaExtData *edata; char *old =3D *isa_str; char *new =3D *isa_str; - int i; =20 - for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) { - new =3D g_strconcat(old, "_", isa_edata_arr[i].name, NULL); + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)) { + new =3D g_strconcat(old, "_", edata->name, NULL); g_free(old); old =3D new; } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c5be917d80..8cdac55e47 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -726,6 +726,13 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_e= xts[]; extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; extern Property riscv_cpu_options[]; =20 +typedef struct isa_ext_data { + const char *name; + int min_version; + int ext_enable_offset; +} RISCVIsaExtData; +extern const RISCVIsaExtData isa_edata_arr[]; + void riscv_add_satp_mode_properties(Object *obj); =20 /* CSR function table */ --=20 2.41.0 From nobody Thu Nov 28 08:03:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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([177.94.15.194]) by smtp.gmail.com with ESMTPSA id n21-20020a9d6f15000000b006b75242d6c3sm6229228otq.38.2023.09.06.02.17.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 02:17:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693991877; x=1694596677; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bvAdwjlcWDznYHEURIxez29VoAB5Kd6vvb026334t4s=; b=K9ghU61ShJFaV6+xkhX0dsGXuLvF9rZvn7yHEgT5nx/oFF4twoGe53IZkRtJG4gTNQ S3gPzgPuFQc2UCRS8bw+eC0m3Z9fOHuIJuyDXVSKYwsFmeex7TgIWTxPgNxjo2PmdQiq XItm0isaZQtb1+NHHClKgSPGR56p6fptpScOeyKDy2PSJslyQWnD3lKzoY2s4k7vCMQn FXAjtQTadQQePlEsFRn125IHHqFuU0Y4MytvQ9jHC4/prLLflz88ydxcgQu6MK2n+qXX qYoDGzYGUhQQSkIEZmjB3876FAUM6v3mhoHqNgUTReSS5C4BmApaA/5rlM241JgKpsLJ 0rIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693991877; x=1694596677; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bvAdwjlcWDznYHEURIxez29VoAB5Kd6vvb026334t4s=; b=LBE307mvk1DtrqJnvWjUUM3V0Zu28PTSg57bB/Wh+x5NDSZakMzyH+wFsWyYf8LgsI 1CrHWQyL18fm1hz/aEnzdrlhW1B72PcYlxO6S+wFLUKaMXUTY/WB3U1CTeU48lIVEu7j w8OgVn/7hHkdykgk5URQvaoPpvm7SVxldGjOEr2k5eze/KOAmniLkakvTpJUYhffrbCP 9uGcmasLuTGi4rUGS2zcrhYQ0FDiGjF+JhVh14MGekeXf5FZR+hD7xBchCqv+44BBy1p WgW2ygqURVg8vI6+OZVgNZcPXo1uD5ijoruXxpRHNce2zw03njO4cGd0Mm1TPeCkoUxo e6rw== X-Gm-Message-State: AOJu0YzcEGOlj/8jPSsXOCElZ2St3FFGjYKGq8l0fLgJp6OijFjBX5Vn uyG4Y2G1L4IlIOVLG1TldzxkrFTvbVw5NPEw7w8= X-Google-Smtp-Source: AGHT+IGOGvPObitefywWT3cn2Z52qxDWN2SVl566WqkwWmxZeE4GTfZ6rfU9f///7FbT2VS4a6a5FQ== X-Received: by 2002:a05:6830:32aa:b0:6bc:9833:3e0 with SMTP id m42-20020a05683032aa00b006bc983303e0mr14247483ott.8.1693991877143; Wed, 06 Sep 2023 02:17:57 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c Date: Wed, 6 Sep 2023 06:16:46 -0300 Message-ID: <20230906091647.1667171-20-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com> References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1693992129946100003 Content-Type: text/plain; charset="utf-8" Priv spec validation is TCG specific. Move it to the TCG accel class. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 38 -------------------------------------- target/riscv/cpu.h | 2 -- target/riscv/tcg/tcg-cpu.c | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 38 insertions(+), 40 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e97ba3df93..eeeb08a35a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -172,21 +172,6 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ex= t_offset, bool en) *ext_enabled =3D en; } =20 -int cpu_cfg_ext_get_min_version(uint32_t ext_offset) -{ - const RISCVIsaExtData *edata; - - for (edata =3D isa_edata_arr; edata && edata->name; edata++) { - if (edata->ext_enable_offset !=3D ext_offset) { - continue; - } - - return edata->min_version; - } - - g_assert_not_reached(); -} - const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -925,29 +910,6 @@ static void riscv_cpu_disas_set_info(CPUState *s, disa= ssemble_info *info) } } =20 -void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) -{ - CPURISCVState *env =3D &cpu->env; - const RISCVIsaExtData *edata; - - /* Force disable extensions if priv spec version does not match */ - for (edata =3D isa_edata_arr; edata && edata->name; edata++) { - if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && - (env->priv_ver < edata->min_version)) { - isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); -#ifndef CONFIG_USER_ONLY - warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx - " because privilege spec version does not match", - edata->name, env->mhartid); -#else - warn_report("disabling %s extension because " - "privilege spec version does not match", - edata->name); -#endif - } - } -} - #ifndef CONFIG_USER_ONLY static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8cdac55e47..8d0e12d0c9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -711,9 +711,7 @@ enum riscv_pmu_event_idx { /* used by tcg/tcg-cpu.c*/ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); -int cpu_cfg_ext_get_min_version(uint32_t ext_offset); void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); -void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu); =20 typedef struct RISCVCPUMultiExtConfig { const char *name; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c23bc0c2e1..ab46623092 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -97,6 +97,21 @@ static const struct TCGCPUOps riscv_tcg_ops =3D { #endif /* !CONFIG_USER_ONLY */ }; =20 +static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) +{ + const RISCVIsaExtData *edata; + + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (edata->ext_enable_offset !=3D ext_offset) { + continue; + } + + return edata->min_version; + } + + g_assert_not_reached(); +} + static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, bool value) { @@ -224,6 +239,29 @@ static void riscv_cpu_validate_v(CPURISCVState *env, R= ISCVCPUConfig *cfg, } } =20 +static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) +{ + CPURISCVState *env =3D &cpu->env; + const RISCVIsaExtData *edata; + + /* Force disable extensions if priv spec version does not match */ + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && + (env->priv_ver < edata->min_version)) { + isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); +#ifndef CONFIG_USER_ONLY + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx + " because privilege spec version does not match", + edata->name, env->mhartid); +#else + warn_report("disabling %s extension because " + "privilege spec version does not match", + edata->name); +#endif + } + } +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. --=20 2.41.0