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[81.233.187.21]) by smtp.gmail.com with ESMTPSA id b25-20020ac25e99000000b004ff725d1a27sm2489811lfq.234.2023.09.05.13.14.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Sep 2023 13:14:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1693944879; x=1694549679; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kjHTvwkRQLgWn6AbYXrQiHckpQTTlZrVyb3u0idfryg=; b=a4CY0rZBFebMWHtNzFqNr2XuQ2sAEJsxk4cjCBSgv2OnZrEYeWDj6kvCbRD4xbE5/l zQAJ8iK62HDOx3dH95gLTunKPGiQNPSz2Wi9zSNq0v2P5197kZpQWFRskMxeskGk/QeM DzKJdemBdS0uSlT5cDBo0mRGpSGdi/SANC5+6Z8GsuHNokwsiTTjibs6sN2fiJYiCx+h 3EB/nAk3TqRJ6StaLtqP3psBpUvHMwxddb3Zsrc6tkcfi0Yudvq3tujhvjkCxYw1Nj1e eoForC8WnEgYr7YNRnKteNs2SlOTEdU7FWXIVe8LrUFO5DmzqKVRsHRlB2vS0hppQ0+9 1HcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693944879; x=1694549679; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kjHTvwkRQLgWn6AbYXrQiHckpQTTlZrVyb3u0idfryg=; b=GRl840mThDFLseOC197J+ayisBNk8vj9jnehkj3TtEp1WVHl8dvz6NZ9r6LcxklgaM uzy81Wp3Fo8EcXgXHSE/InqnnxyB8wA7m0XhCTPQ7bi8jIIpOnC7/s5rOq7vTv4F4l8d PuSMnm95AGwRSSSaagFCGgd5gpGwTOZxQ73nD9QKAzLaajCVRZEqPbcfJbYCj+SkvNvt ulPC8wZpkhQCEZ1QztF2RzBI95fmcnVVvWteo38m/axLyC2yvDAmZDPTOQsTS/io7/35 gtf82upXVcWqrxnIZ6M+IxxuKvijNnAhMunNqxOjTVtSKzNc+nJGj3QY9BErT5l8j7wo sUng== X-Gm-Message-State: AOJu0YzW7dtoZxnnuxwx6FL5QG2JJxHRhYGljmpOeEyck84voJaZAFVL hfoIm5zr0X2lqL4tXEDKB8Qkymz/IjplQQ== X-Google-Smtp-Source: AGHT+IFPYc4CXUQPWdkQmdY31rGCFPo1Pln9CgskK0PPxlH/hBaV6GYop6qWloPYcv6Nl4bKRLBefQ== X-Received: by 2002:ac2:4e8b:0:b0:500:77c4:108 with SMTP id o11-20020ac24e8b000000b0050077c40108mr580460lfr.9.1693944878513; Tue, 05 Sep 2023 13:14:38 -0700 (PDT) From: Strahinja Jankovic X-Google-Original-From: Strahinja Jankovic To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Beniamino Galvani , Peter Maydell , Strahinja Jankovic Subject: [RFC Patch 1/5] hw/display: Allwinner A10 HDMI controller emulation Date: Tue, 5 Sep 2023 22:14:21 +0200 Message-Id: <20230905201425.118918-2-strahinja.p.jankovic@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230905201425.118918-1-strahinja.p.jankovic@gmail.com> References: <20230905201425.118918-1-strahinja.p.jankovic@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=strahinjapjankovic@gmail.com; helo=mail-lf1-x134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1693944980400100003 Content-Type: text/plain; charset="utf-8" This patch adds basic Allwinner A10 HDMI controller support. Emulated HDMI component will always show that a display is connected and provide default EDID info. Signed-off-by: Strahinja Jankovic --- hw/arm/allwinner-a10.c | 7 + hw/display/allwinner-a10-hdmi.c | 214 ++++++++++++++++++++++++ hw/display/meson.build | 2 + hw/display/trace-events | 4 + include/hw/arm/allwinner-a10.h | 2 + include/hw/display/allwinner-a10-hdmi.h | 69 ++++++++ 6 files changed, 298 insertions(+) create mode 100644 hw/display/allwinner-a10-hdmi.c create mode 100644 include/hw/display/allwinner-a10-hdmi.h diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index b0ea3f7f66..2351d1a69b 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -41,6 +41,7 @@ #define AW_A10_WDT_BASE 0x01c20c90 #define AW_A10_RTC_BASE 0x01c20d00 #define AW_A10_I2C0_BASE 0x01c2ac00 +#define AW_A10_HDMI_BASE 0x01c16000 =20 void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk) { @@ -95,6 +96,8 @@ static void aw_a10_init(Object *obj) object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN4I); =20 object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN4I); + + object_initialize_child(obj, "hdmi", &s->hdmi, TYPE_AW_A10_HDMI); } =20 static void aw_a10_realize(DeviceState *dev, Error **errp) @@ -210,6 +213,10 @@ static void aw_a10_realize(DeviceState *dev, Error **e= rrp) /* WDT */ sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal); sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0, AW_A10_WDT_BASE, 1= ); + + /* HDMI */ + sysbus_realize(SYS_BUS_DEVICE(&s->hdmi), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->hdmi), 0, AW_A10_HDMI_BASE); } =20 static void aw_a10_class_init(ObjectClass *oc, void *data) diff --git a/hw/display/allwinner-a10-hdmi.c b/hw/display/allwinner-a10-hdm= i.c new file mode 100644 index 0000000000..0f046e3cc7 --- /dev/null +++ b/hw/display/allwinner-a10-hdmi.c @@ -0,0 +1,214 @@ +/* + * Allwinner A10 HDMI Module emulation + * + * Copyright (C) 2023 Strahinja Jankovic + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "hw/qdev-properties.h" +#include "qemu/module.h" +#include "hw/display/allwinner-a10-hdmi.h" +#include "trace.h" + +/* HDMI register offsets */ +enum { + REG_HPD =3D 0x000C, /* HDMI Hotplug detect */ + REG_DDC_CTRL =3D 0x0500, /* DDC Control */ + REG_DDC_SLAVE_ADDRESS =3D 0x0504, /* DDC Slave address */ + REG_DDC_INT_STATUS =3D 0x050C, /* DDC Interrupt status */ + REG_DDC_FIFO_CTRL =3D 0x0510, /* DDC FIFO Control */ + REG_DDC_FIFO_ACCESS =3D 0x0518, /* DDC FIFO access */ + REG_DDC_COMMAND =3D 0x0520, /* DDC Command */ +}; + +/* HPD register fields */ +#define FIELD_HPD_HOTPLUG_DET_HIGH (1 << 0) + +/* DDC_CTRL register fields */ +#define FIELD_DDC_CTRL_SW_RST (1 << 0) +#define FIELD_DDC_CTRL_ACCESS_CMD_START (1 << 30) + +/* FIFO_CTRL register fields */ +#define FIELD_FIFO_CTRL_ADDRESS_CLEAR (1 << 31) + +/* DDC_SLAVE_ADDRESS register fields */ +#define FIELD_DDC_SLAVE_ADDRESS_SEGMENT_SHIFT (24) +#define FIELD_DDC_SLAVE_ADDRESS_OFFSET_SHIFT (8) + +/* DDC_INT_STATUS register fields */ +#define FIELD_DDC_INT_STATUS_TRANSFER_COMPLETE (1 << 0) + +/* DDC access command */ +enum { + DDC_COMMAND_E_DDC_READ =3D 6, +}; + + + +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) + +static uint64_t allwinner_a10_hdmi_read(void *opaque, hwaddr offset, + unsigned size) +{ + AwA10HdmiState *s =3D AW_A10_HDMI(opaque); + const uint32_t idx =3D REG_INDEX(offset); + uint32_t val =3D s->regs[idx]; + + switch (offset) { + case REG_HPD: + val =3D FIELD_HPD_HOTPLUG_DET_HIGH; + break; + case REG_DDC_FIFO_ACCESS: + val =3D s->edid_blob[s->edid_reg % sizeof(s->edid_blob)]; + s->edid_reg++; + break; + case 0x544 ... AW_A10_HDMI_IOSIZE: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + default: + break; + } + + trace_allwinner_a10_hdmi_read(offset, val); + + return val; +} + +static void allwinner_a10_hdmi_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwA10HdmiState *s =3D AW_A10_HDMI(opaque); + const uint32_t idx =3D REG_INDEX(offset); + + switch (offset) { + case REG_DDC_CTRL: + if (val & FIELD_DDC_CTRL_SW_RST) { + val &=3D ~FIELD_DDC_CTRL_SW_RST; + } + if (val & FIELD_DDC_CTRL_ACCESS_CMD_START) { + val &=3D ~FIELD_DDC_CTRL_ACCESS_CMD_START; + if (s->regs[REG_INDEX(REG_DDC_COMMAND)] =3D=3D DDC_COMMAND_E_D= DC_READ) { + uint32_t regval =3D s->regs[REG_INDEX(REG_DDC_SLAVE_ADDRES= S)]; + uint8_t segment =3D 0xFFu & + (regval >> FIELD_DDC_SLAVE_ADDRESS_SEGMENT_SHIFT); + uint8_t offset =3D 0xFFu & + (regval >> FIELD_DDC_SLAVE_ADDRESS_OFFSET_SHIFT); + if (segment =3D=3D 0) { + s->edid_reg =3D offset; + } + } + } + break; + case REG_DDC_INT_STATUS: + /* Clear interrupts */ + val =3D s->regs[REG_INDEX(REG_DDC_INT_STATUS)] & ~(val & 0xFFu); + /* Set transfer complete */ + val |=3D FIELD_DDC_INT_STATUS_TRANSFER_COMPLETE; + break; + case REG_DDC_FIFO_CTRL: + if (val & FIELD_FIFO_CTRL_ADDRESS_CLEAR) { + val &=3D ~FIELD_FIFO_CTRL_ADDRESS_CLEAR; + } + break; + case 0x544 ... AW_A10_HDMI_IOSIZE: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + break; + default: + break; + } + + trace_allwinner_a10_hdmi_write(offset, (uint32_t)val); + + s->regs[idx] =3D (uint32_t) val; +} + +static const MemoryRegionOps allwinner_a10_hdmi_ops =3D { + .read =3D allwinner_a10_hdmi_read, + .write =3D allwinner_a10_hdmi_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, + .impl.min_access_size =3D 1, +}; + +static void allwinner_a10_hdmi_reset_enter(Object *obj, ResetType type) +{ + AwA10HdmiState *s =3D AW_A10_HDMI(obj); + + s->edid_reg =3D 0; +} + +static void allwinner_a10_hdmi_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + AwA10HdmiState *s =3D AW_A10_HDMI(obj); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_a10_hdmi_ops, s, + TYPE_AW_A10_HDMI, AW_A10_HDMI_IOSIZE); + sysbus_init_mmio(sbd, &s->iomem); + + qemu_edid_generate(s->edid_blob, sizeof(s->edid_blob), &s->edid_info); +} + +static const VMStateDescription allwinner_a10_hdmi_vmstate =3D { + .name =3D "allwinner-a10-hdmi", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AwA10HdmiState, AW_A10_HDMI_REGS_NUM), + VMSTATE_END_OF_LIST() + } +}; + +static Property allwinner_a10_hdmi_properties[] =3D { + DEFINE_EDID_PROPERTIES(AwA10HdmiState, edid_info), + DEFINE_PROP_END_OF_LIST(), +}; + +static void allwinner_a10_hdmi_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + device_class_set_props(dc, allwinner_a10_hdmi_properties); + + rc->phases.enter =3D allwinner_a10_hdmi_reset_enter; + dc->vmsd =3D &allwinner_a10_hdmi_vmstate; +} + +static const TypeInfo allwinner_a10_hdmi_info =3D { + .name =3D TYPE_AW_A10_HDMI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_init =3D allwinner_a10_hdmi_init, + .instance_size =3D sizeof(AwA10HdmiState), + .class_init =3D allwinner_a10_hdmi_class_init, +}; + +static void allwinner_a10_hdmi_register(void) +{ + type_register_static(&allwinner_a10_hdmi_info); +} + +type_init(allwinner_a10_hdmi_register) diff --git a/hw/display/meson.build b/hw/display/meson.build index 413ba4ab24..0a36c3ed85 100644 --- a/hw/display/meson.build +++ b/hw/display/meson.build @@ -38,6 +38,8 @@ system_ss.add(when: 'CONFIG_NEXTCUBE', if_true: files('ne= xt-fb.c')) =20 system_ss.add(when: 'CONFIG_VGA', if_true: files('vga.c')) =20 +system_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10-= hdmi.c') + if (config_all_devices.has_key('CONFIG_VGA_CIRRUS') or config_all_devices.has_key('CONFIG_VGA_PCI') or config_all_devices.has_key('CONFIG_VMWARE_VGA') or diff --git a/hw/display/trace-events b/hw/display/trace-events index 2336a0ca15..8d0d33ce4d 100644 --- a/hw/display/trace-events +++ b/hw/display/trace-events @@ -177,3 +177,7 @@ macfb_ctrl_write(uint64_t addr, uint64_t value, unsigne= d int size) "addr 0x%"PRI macfb_sense_read(uint32_t value) "video sense: 0x%"PRIx32 macfb_sense_write(uint32_t value) "video sense: 0x%"PRIx32 macfb_update_mode(uint32_t width, uint32_t height, uint8_t depth) "setting= mode to width %"PRId32 " height %"PRId32 " size %d" + +# allwinner-a10-hdmi.c +allwinner_a10_hdmi_read(uint64_t offset, uint64_t data) "Read: offset 0x%"= PRIx64 " data 0x%" PRIx64 +allwinner_a10_hdmi_write(uint64_t offset, uint64_t data) "Write: offset 0x= %" PRIx64 " data 0x%" PRIx64 diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index cd1465c613..db8cbeecfa 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -12,6 +12,7 @@ #include "hw/rtc/allwinner-rtc.h" #include "hw/misc/allwinner-a10-ccm.h" #include "hw/misc/allwinner-a10-dramc.h" +#include "hw/display/allwinner-a10-hdmi.h" #include "hw/i2c/allwinner-i2c.h" #include "hw/watchdog/allwinner-wdt.h" #include "sysemu/block-backend.h" @@ -43,6 +44,7 @@ struct AwA10State { AWI2CState i2c0; AwRtcState rtc; AwWdtState wdt; + AwA10HdmiState hdmi; MemoryRegion sram_a; EHCISysBusState ehci[AW_A10_NUM_USB]; OHCISysBusState ohci[AW_A10_NUM_USB]; diff --git a/include/hw/display/allwinner-a10-hdmi.h b/include/hw/display/a= llwinner-a10-hdmi.h new file mode 100644 index 0000000000..1065dca2f7 --- /dev/null +++ b/include/hw/display/allwinner-a10-hdmi.h @@ -0,0 +1,69 @@ +/* + * Allwinner A10 HDMI Module emulation + * + * Copyright (C) 2023 Strahinja Jankovic + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef HW_DISPLAY_ALLWINNER_A10_HDMI_H +#define HW_DISPLAY_ALLWINNER_A10_HDMI_H + +#include "hw/display/edid.h" +#include "qom/object.h" +#include "hw/sysbus.h" + +/** + * @name Constants + * @{ + */ + +/** Size of register I/O address space used by HDMI device */ +#define AW_A10_HDMI_IOSIZE (0x1000) + +/** Total number of known registers */ +#define AW_A10_HDMI_REGS_NUM (AW_A10_HDMI_IOSIZE / sizeof(uint32_t)) + +/** @} */ + +/** + * @name Object model + * @{ + */ + +#define TYPE_AW_A10_HDMI "allwinner-a10-hdmi" +OBJECT_DECLARE_SIMPLE_TYPE(AwA10HdmiState, AW_A10_HDMI) + +/** @} */ + +/** + * Allwinner A10 HDMI object instance state. + */ +struct AwA10HdmiState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + /** Maps I/O registers in physical memory */ + MemoryRegion iomem; + + uint8_t edid_reg; + qemu_edid_info edid_info; + uint8_t edid_blob[128]; + + /** Array of hardware registers */ + uint32_t regs[AW_A10_HDMI_REGS_NUM]; +}; + +#endif /* HW_DISPLAY_ALLWINNER_A10_HDMI_H */ --=20 2.34.1 From nobody Thu Nov 28 08:03:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1693944949; cv=none; d=zohomail.com; s=zohoarc; b=E5/fb1uT37KDvqfTT9TfjKAvq96H+rITXMetujxD42jfL+MLH6c4puQeAfS/+AbnBpkmREwsFmY3F25nQHw+LUhAjy4r5yWOZyOJxkrUmux1TwolbWDxVgqy0X+ZS9rSXZ0jROLR0FQMe1Tzkz0+ixcjK6Rwq/UTUjivd7gC9bk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693944949; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=p+55zTL8qzmfnSZPGRsQ3XdBdwCldHenVE5r+lCRo7g=; b=hVrfdbf3cWFyZBV5tBpcdr87aGf5KPPh+H9h6hT2u5GzgCv08ssYu983a7FnS1yzKLtxVLTeg0wObQCOGwzWXi03o5W1r7BLYwFYZDIIU2H2SUG/KTv+2f/eOUJnkj336qvwhUDJn9pawi+Wh0bFSf1KW/FqzQuoRkxng8pjntg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693944949789367.685330777034; Tue, 5 Sep 2023 13:15:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qdcRk-0004uf-4x; Tue, 05 Sep 2023 16:14:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qdcRi-0004tt-9T; Tue, 05 Sep 2023 16:14:46 -0400 Received: from mail-lf1-x129.google.com ([2a00:1450:4864:20::129]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qdcRf-00037l-51; Tue, 05 Sep 2023 16:14:46 -0400 Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-501bd6f7d11so1943792e87.1; Tue, 05 Sep 2023 13:14:42 -0700 (PDT) Received: from localhost.localdomain (81-233-187-21-no600.tbcn.telia.com. [81.233.187.21]) by smtp.gmail.com with ESMTPSA id b25-20020ac25e99000000b004ff725d1a27sm2489811lfq.234.2023.09.05.13.14.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Sep 2023 13:14:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1693944881; x=1694549681; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p+55zTL8qzmfnSZPGRsQ3XdBdwCldHenVE5r+lCRo7g=; b=IaFoo8w5PlV8ggaMt2HoZrkK8XLGziaAkkTRY1kQmAITzwmqgCiM5nojtNUHx3MZnZ RoiYg7uMIknqrUSd+RcZnSFLdSa4YMrKcOjCpMEzPOJjSzoEi13cMlztBCoC1Td6jAZw IF5HSk+FdYXAZq05v2aC0yn7SFgngZGo1/jDJRU5nkXXd6V2b7P+MF3TQyzkVip7jUH9 1TJLaoNDAe4yM6UXEbdxIbXpcTJZdLpUSakUZ7D6K+wbBr2XYSyx7w41TkLXWkmLgHJu rmDWlyLxAhZJ4rIx3pzchsydwfjWYYhiHwGxuQ6wApEOd2/xMRpLxsqDRbAk7pIcVs3l uCbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693944881; x=1694549681; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p+55zTL8qzmfnSZPGRsQ3XdBdwCldHenVE5r+lCRo7g=; b=ihrwfekdpqExdPsuC4AmLwQ9AsWJ6hmFgdbzgCFTv6wDjng9H8riDiuzgQTzsEuRg6 k4rrE3R6LCJAOIpTaIZ6/kQ5DlPZYMu725g5rtpCzhzsPhg4ig8Y7sD1Uzbd3pGTFJC/ LiZztCN4XzuRQo14a54ehBaHYYMKsT5x02W6ta9fHm5dcvj7/ihy0ezUtqyHBL7M0AdX 17GgxZokLHtTto1xsE7uvLqfr2nGZrdWXGnu96wQ1oOJ89XkBkqEAhosN0UuALOd6wm8 +g9ZLoSviBXaRqbVJfMGX4+OZjBmIJdNq0HKnSnrlIORQGkjQYnx2NjBADn5Ye1kcSey XizQ== X-Gm-Message-State: AOJu0YwZqEsBrcudWdOqR52aiez1b/IPFbcwdmvTpajum914eMyZ4kWQ F8KkLnsPvpSXyPjkyTcRK/06nqbLJknSFw== X-Google-Smtp-Source: AGHT+IGsfnhF+2An7DeEX0tuRDL48WiFGufrq5El999eXOq3boZtzSLuyNmHbbi+LnEsup4O/9tYxA== X-Received: by 2002:ac2:518d:0:b0:501:bc0b:6118 with SMTP id u13-20020ac2518d000000b00501bc0b6118mr672917lfi.50.1693944880641; Tue, 05 Sep 2023 13:14:40 -0700 (PDT) From: Strahinja Jankovic X-Google-Original-From: Strahinja Jankovic To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Beniamino Galvani , Peter Maydell , Strahinja Jankovic Subject: [RFC Patch 2/5] hw/display: Allwinner basic MALI GPU emulation Date: Tue, 5 Sep 2023 22:14:22 +0200 Message-Id: <20230905201425.118918-3-strahinja.p.jankovic@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230905201425.118918-1-strahinja.p.jankovic@gmail.com> References: <20230905201425.118918-1-strahinja.p.jankovic@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=strahinjapjankovic@gmail.com; helo=mail-lf1-x129.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1693944952086100010 Content-Type: text/plain; charset="utf-8" This patch adds minimal MALI GPU emulation needed so emulated system thinks GPU is working. Signed-off-by: Strahinja Jankovic --- hw/arm/allwinner-a10.c | 7 + hw/display/allwinner-gpu.c | 212 +++++++++++++++++++++++++++++ hw/display/meson.build | 3 +- hw/display/trace-events | 4 + include/hw/arm/allwinner-a10.h | 2 + include/hw/display/allwinner-gpu.h | 64 +++++++++ 6 files changed, 291 insertions(+), 1 deletion(-) create mode 100644 hw/display/allwinner-gpu.c create mode 100644 include/hw/display/allwinner-gpu.h diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index 2351d1a69b..75cd879d24 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -42,6 +42,7 @@ #define AW_A10_RTC_BASE 0x01c20d00 #define AW_A10_I2C0_BASE 0x01c2ac00 #define AW_A10_HDMI_BASE 0x01c16000 +#define AW_A10_GPU_BASE 0x01c40000 =20 void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk) { @@ -98,6 +99,8 @@ static void aw_a10_init(Object *obj) object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN4I); =20 object_initialize_child(obj, "hdmi", &s->hdmi, TYPE_AW_A10_HDMI); + + object_initialize_child(obj, "mali400", &s->gpu, TYPE_AW_GPU); } =20 static void aw_a10_realize(DeviceState *dev, Error **errp) @@ -217,6 +220,10 @@ static void aw_a10_realize(DeviceState *dev, Error **e= rrp) /* HDMI */ sysbus_realize(SYS_BUS_DEVICE(&s->hdmi), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(&s->hdmi), 0, AW_A10_HDMI_BASE); + + /* MALI GPU */ + sysbus_realize(SYS_BUS_DEVICE(&s->gpu), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpu), 0, AW_A10_GPU_BASE); } =20 static void aw_a10_class_init(ObjectClass *oc, void *data) diff --git a/hw/display/allwinner-gpu.c b/hw/display/allwinner-gpu.c new file mode 100644 index 0000000000..735976d206 --- /dev/null +++ b/hw/display/allwinner-gpu.c @@ -0,0 +1,212 @@ +/* + * Allwinner GPU Module emulation + * + * Copyright (C) 2023 Strahinja Jankovic + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/display/allwinner-gpu.h" +#include "trace.h" + +/* GPU register offsets - only the important ones. */ +enum { + REG_MALI_GP_CMD =3D 0x0020, + REG_MALI_GP_INT_RAWSTAT =3D 0x0024, + REG_MALI_GP_VERSION =3D 0x006C, + REG_MALI_GP_MMU_DTE =3D 0x3000, + REG_MALI_GP_MMU_STATUS =3D 0x3004, + REG_MALI_GP_MMU_COMMAND =3D 0x3008, + REG_MALI_PP0_MMU_DTE =3D 0x4000, + REG_MALI_PP0_MMU_STATUS =3D 0x4004, + REG_MALI_PP0_MMU_COMMAND =3D 0x4008, + REG_MALI_PP0_VERSION =3D 0x9000, + REG_MALI_PP0_CTRL =3D 0x900C, + REG_MALI_PP0_INT_RAWSTAT =3D 0x9020, +}; + +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) + +#define MALI_GP_VERSION_READ_VAL (0x0B07u << 16) +#define MALI_PP0_VERSION_READ_VAL (0xCD07u << 16) +#define MALI_MMU_DTE_MASK (0x0FFF) + +/* MALI_GP_CMD register fields */ +#define MALI_GP_CMD_SOFT_RESET (1 << 10) + +/* MALI_GP_INT_RAWSTAT register fields */ +#define MALI_GP_INT_RAWSTAT_RESET_COMPLETED (1 << 19) + +/* MALI_MMU_COMMAND values */ +enum { + MALI_MMU_COMMAND_ENABLE_PAGING =3D 0, + MALI_MMU_COMMAND_HARD_RESET =3D 6, +}; + +/* MALI_MMU_STATUS register fields */ +#define MALI_MMU_STATUS_PAGING_ENABLED (1 << 0) + +/* MALI_PP_CTRL register fields */ +#define MALI_PP_CTRL_SOFT_RESET (1 << 7) + +/* MALI_PP_INT_RAWSTAT register fields */ +#define MALI_PP_INT_RAWSTAT_RESET_COMPLETED (1 << 12) + +static uint64_t allwinner_gpu_read(void *opaque, hwaddr offset, + unsigned size) +{ + const AwGpuState *s =3D AW_GPU(opaque); + const uint32_t idx =3D REG_INDEX(offset); + uint32_t val =3D s->regs[idx]; + + switch (offset) { + case REG_MALI_GP_VERSION: + val =3D MALI_GP_VERSION_READ_VAL; + break; + case REG_MALI_GP_MMU_DTE: + case REG_MALI_PP0_MMU_DTE: + val &=3D ~MALI_MMU_DTE_MASK; + break; + case REG_MALI_PP0_VERSION: + val =3D MALI_PP0_VERSION_READ_VAL; + break; + case 0xF0B8 ... AW_GPU_IOSIZE: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + default: + break; + } + + trace_allwinner_gpu_read(offset, val); + + return val; +} + +static void allwinner_gpu_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwGpuState *s =3D AW_GPU(opaque); + const uint32_t idx =3D REG_INDEX(offset); + + trace_allwinner_gpu_write(offset, (uint32_t)val); + + switch (offset) { + case REG_MALI_GP_CMD: + if (val =3D=3D MALI_GP_CMD_SOFT_RESET) { + s->regs[REG_INDEX(REG_MALI_GP_INT_RAWSTAT)] |=3D + MALI_GP_INT_RAWSTAT_RESET_COMPLETED; + } + break; + case REG_MALI_GP_MMU_COMMAND: + if (val =3D=3D MALI_MMU_COMMAND_ENABLE_PAGING) { + s->regs[REG_INDEX(REG_MALI_GP_MMU_STATUS)] |=3D + MALI_MMU_STATUS_PAGING_ENABLED; + } else if (val =3D=3D MALI_MMU_COMMAND_HARD_RESET) { + s->regs[REG_INDEX(REG_MALI_GP_MMU_DTE)] =3D 0; + } + break; + case REG_MALI_PP0_MMU_COMMAND: + if (val =3D=3D MALI_MMU_COMMAND_ENABLE_PAGING) { + s->regs[REG_INDEX(REG_MALI_PP0_MMU_STATUS)] |=3D + MALI_MMU_STATUS_PAGING_ENABLED; + } else if (val =3D=3D MALI_MMU_COMMAND_HARD_RESET) { + s->regs[REG_INDEX(REG_MALI_PP0_MMU_DTE)] =3D 0; + } + break; + case REG_MALI_PP0_CTRL: + if (val =3D=3D MALI_PP_CTRL_SOFT_RESET) { + s->regs[REG_INDEX(REG_MALI_PP0_INT_RAWSTAT)] =3D + MALI_PP_INT_RAWSTAT_RESET_COMPLETED; + } + break; + case 0xF0B8 ... AW_GPU_IOSIZE: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + break; + default: + break; + } + + s->regs[idx] =3D (uint32_t) val; +} + +static const MemoryRegionOps allwinner_gpu_ops =3D { + .read =3D allwinner_gpu_read, + .write =3D allwinner_gpu_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .impl.min_access_size =3D 4, +}; + +static void allwinner_gpu_reset_enter(Object *obj, ResetType type) +{ + AwGpuState *s =3D AW_GPU(obj); + + memset(&s->regs[0], 0, AW_GPU_IOSIZE); +} + +static void allwinner_gpu_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + AwGpuState *s =3D AW_GPU(obj); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_gpu_ops, s, + TYPE_AW_GPU, AW_GPU_IOSIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription allwinner_gpu_vmstate =3D { + .name =3D "allwinner-gpu", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AwGpuState, AW_GPU_REGS_NUM), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_gpu_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.enter =3D allwinner_gpu_reset_enter; + dc->vmsd =3D &allwinner_gpu_vmstate; +} + +static const TypeInfo allwinner_gpu_info =3D { + .name =3D TYPE_AW_GPU, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_init =3D allwinner_gpu_init, + .instance_size =3D sizeof(AwGpuState), + .class_init =3D allwinner_gpu_class_init, +}; + +static void allwinner_gpu_register(void) +{ + type_register_static(&allwinner_gpu_info); +} + +type_init(allwinner_gpu_register) diff --git a/hw/display/meson.build b/hw/display/meson.build index 0a36c3ed85..a5eb01fe2b 100644 --- a/hw/display/meson.build +++ b/hw/display/meson.build @@ -38,7 +38,8 @@ system_ss.add(when: 'CONFIG_NEXTCUBE', if_true: files('ne= xt-fb.c')) =20 system_ss.add(when: 'CONFIG_VGA', if_true: files('vga.c')) =20 -system_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10-= hdmi.c') +system_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10-= hdmi.c', + 'allwinner-gpu.= c')) =20 if (config_all_devices.has_key('CONFIG_VGA_CIRRUS') or config_all_devices.has_key('CONFIG_VGA_PCI') or diff --git a/hw/display/trace-events b/hw/display/trace-events index 8d0d33ce4d..d1c0f05e52 100644 --- a/hw/display/trace-events +++ b/hw/display/trace-events @@ -181,3 +181,7 @@ macfb_update_mode(uint32_t width, uint32_t height, uint= 8_t depth) "setting mode # allwinner-a10-hdmi.c allwinner_a10_hdmi_read(uint64_t offset, uint64_t data) "Read: offset 0x%"= PRIx64 " data 0x%" PRIx64 allwinner_a10_hdmi_write(uint64_t offset, uint64_t data) "Write: offset 0x= %" PRIx64 " data 0x%" PRIx64 + +# allwinner-gpu.c +allwinner_gpu_read(uint64_t offset, uint64_t data) "Read: offset 0x%" PRIx= 64 " data 0x%" PRIx64 +allwinner_gpu_write(uint64_t offset, uint64_t data) "Write: offset 0x%" PR= Ix64 " data 0x%" PRIx64 diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index db8cbeecfa..8109656421 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -13,6 +13,7 @@ #include "hw/misc/allwinner-a10-ccm.h" #include "hw/misc/allwinner-a10-dramc.h" #include "hw/display/allwinner-a10-hdmi.h" +#include "hw/display/allwinner-gpu.h" #include "hw/i2c/allwinner-i2c.h" #include "hw/watchdog/allwinner-wdt.h" #include "sysemu/block-backend.h" @@ -44,6 +45,7 @@ struct AwA10State { AWI2CState i2c0; AwRtcState rtc; AwWdtState wdt; + AwGpuState gpu; AwA10HdmiState hdmi; MemoryRegion sram_a; EHCISysBusState ehci[AW_A10_NUM_USB]; diff --git a/include/hw/display/allwinner-gpu.h b/include/hw/display/allwin= ner-gpu.h new file mode 100644 index 0000000000..6800a58dde --- /dev/null +++ b/include/hw/display/allwinner-gpu.h @@ -0,0 +1,64 @@ +/* + * Allwinner A10 GPU Module emulation + * + * Copyright (C) 2023 Strahinja Jankovic + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef HW_DISPLAY_ALLWINNER_GPU_H +#define HW_DISPLAY_ALLWINNER_GPU_H + +#include "qom/object.h" +#include "hw/sysbus.h" + +/** + * @name Constants + * @{ + */ + +/** Size of register I/O address space used by GPU device */ +#define AW_GPU_IOSIZE (0x10000) + +/** Total number of known registers */ +#define AW_GPU_REGS_NUM (AW_GPU_IOSIZE / sizeof(uint32_t)) + +/** @} */ + +/** + * @name Object model + * @{ + */ + +#define TYPE_AW_GPU "allwinner-gpu" +OBJECT_DECLARE_SIMPLE_TYPE(AwGpuState, AW_GPU) + +/** @} */ + +/** + * Allwinner GPU object instance state. + */ +struct AwGpuState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + /** Maps I/O registers in physical memory */ + MemoryRegion iomem; + + /** Array of hardware registers */ + uint32_t regs[AW_GPU_REGS_NUM]; +}; + +#endif /* HW_DISPLAY_ALLWINNER_GPU_H */ --=20 2.34.1 From nobody Thu Nov 28 08:03:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1693944949; cv=none; d=zohomail.com; s=zohoarc; b=HkoQz4iIURDZU8/nzEG0sz/MJtdgi+ekQU/Ie928AGHPLQwkqLN0tS0x9cgXk+tFdPgE5wHCkUirdjXIBcOePKGb92JAt6PUnKLbvKKqTXhe+9lc16Mv2TPYkCTixJfrUk1gzvDamKBiFyCDTs22QLOHtSblR9870HvHcRatpFo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693944949; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ijoIYgSSx9pGR8q+BMlkWx4itHcBAMoynk9IpUxxSWM=; b=CSviJ81wSlE+EUThnCAl8MFdhUiGpoRoHZ5nUqCxiifUi2MWxXm4ErZstjT6SXtZNbYO4Jfxx4VoezMBV++5fka8gYqnwuU7JGT9CvCQopcCbrp7TSAaRJtxZbu6d2ZL3kAjxOtNMEBUs9lnGPhEUVyVcjQIIaRRd5v+ixKI4EY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693944949616585.3765260598318; Tue, 5 Sep 2023 13:15:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qdcRl-0004uu-7T; Tue, 05 Sep 2023 16:14:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qdcRj-0004u5-Lt; Tue, 05 Sep 2023 16:14:47 -0400 Received: from mail-lf1-x12d.google.com ([2a00:1450:4864:20::12d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qdcRg-00037q-BL; Tue, 05 Sep 2023 16:14:47 -0400 Received: by mail-lf1-x12d.google.com with SMTP id 2adb3069b0e04-500a398cda5so5083330e87.0; Tue, 05 Sep 2023 13:14:43 -0700 (PDT) Received: from localhost.localdomain (81-233-187-21-no600.tbcn.telia.com. [81.233.187.21]) by smtp.gmail.com with ESMTPSA id b25-20020ac25e99000000b004ff725d1a27sm2489811lfq.234.2023.09.05.13.14.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Sep 2023 13:14:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1693944882; x=1694549682; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ijoIYgSSx9pGR8q+BMlkWx4itHcBAMoynk9IpUxxSWM=; b=m4if5gEm8dZWhckuj5VJqTVhv9tbT52pCBwd6KNg9nRb32xZoLuB6+TPUo4iTfj51L 550xspiJ3gI5rSNbmS2i9rvi83ODDyIcDRoeoKN0e06NcT1KUrBscFyGlnuNbLMaGkXK 4ECXc86R10zyWWkRebgXvlFmRRApAXUEoO2i7ZR9uzCskkREwpqx3dH6Isr93ooZrBgT LM3N1WHdgolu0+fvSHI81vN2ITYHIBox2ru15xh8GmBpFX0rnMLV5nY68z1CT3TZgQI7 Vd54HeXunn5VnELvrodyWPGpSaZ4KCD8VsO3A364vsSojDl/xKDTBU6UkVgr+zocvSWv J4aA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693944882; x=1694549682; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ijoIYgSSx9pGR8q+BMlkWx4itHcBAMoynk9IpUxxSWM=; b=ka7CXfFf4nhyWJUOV5Ko9OdMNAC8IR8MS0eL104ZYnhavDRn4Bld/SG0+KudhH7Vys gZgNcGx0QsXY+4UtW542aP4vOizSnzwl5BxJzQL3UItQ8i3p5uyv0x0+G5I9S5PDCQHH BXkpeafpZW8bTkl0W5Cx0f9TosIawaKXkvHOkscMCnC2hRaU2K+f6TuvxkueYLvo+i63 n3N8N3+JGiiaKCL883SY3/IXvy8bUrB2hijkYr348iIrd/YdGWih9h5SGm4XOdKf0jJi 8pIqkrFBNDuhujflgnNspmBfofAnfQ3GzqY09FI48RwyOpwXGFYm6Konqmudgn3bE1hV QW+g== X-Gm-Message-State: AOJu0YwY5aEzgVzgrWVRER5QinYhTXlU1v7uvabi8EJlyX8PsF3RjRS/ hRgBSyzDWMUNEMRlAlIGMfbtVhyAG6UDog== X-Google-Smtp-Source: AGHT+IG3m70JhPs0KKyNuJE0VQcmiUDtjb6klWZGsPi4WDPxK/eAFxYLYTSgcfH0+zA7EWdLM6orCA== X-Received: by 2002:a19:4f52:0:b0:500:9d4a:89ff with SMTP id a18-20020a194f52000000b005009d4a89ffmr662827lfk.62.1693944881804; Tue, 05 Sep 2023 13:14:41 -0700 (PDT) From: Strahinja Jankovic X-Google-Original-From: Strahinja Jankovic To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Beniamino Galvani , Peter Maydell , Strahinja Jankovic Subject: [RFC Patch 3/5] hw/display: Allwinner A10 Display Engine Backend emulation Date: Tue, 5 Sep 2023 22:14:23 +0200 Message-Id: <20230905201425.118918-4-strahinja.p.jankovic@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230905201425.118918-1-strahinja.p.jankovic@gmail.com> References: <20230905201425.118918-1-strahinja.p.jankovic@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=strahinjapjankovic@gmail.com; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1693944951965100006 Content-Type: text/plain; charset="utf-8" This patch adds Display Engine Backend 0 (DEBE0) support. This peripheral will hold runtime configuration for the display size and framebuffer offset which will be used by other components. Signed-off-by: Strahinja Jankovic --- hw/arm/allwinner-a10.c | 9 + hw/display/allwinner-a10-debe.c | 229 ++++++++++++++++++++++++ hw/display/meson.build | 3 +- hw/display/trace-events | 4 + include/hw/arm/allwinner-a10.h | 2 + include/hw/display/allwinner-a10-debe.h | 71 ++++++++ 6 files changed, 317 insertions(+), 1 deletion(-) create mode 100644 hw/display/allwinner-a10-debe.c create mode 100644 include/hw/display/allwinner-a10-debe.h diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index 75cd879d24..624e95af46 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -43,6 +43,7 @@ #define AW_A10_I2C0_BASE 0x01c2ac00 #define AW_A10_HDMI_BASE 0x01c16000 #define AW_A10_GPU_BASE 0x01c40000 +#define AW_A10_DE_BE0_BASE 0x01e60000 =20 void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk) { @@ -100,6 +101,8 @@ static void aw_a10_init(Object *obj) =20 object_initialize_child(obj, "hdmi", &s->hdmi, TYPE_AW_A10_HDMI); =20 + object_initialize_child(obj, "de_be0", &s->de_be0, TYPE_AW_A10_DEBE); + object_initialize_child(obj, "mali400", &s->gpu, TYPE_AW_GPU); } =20 @@ -221,6 +224,12 @@ static void aw_a10_realize(DeviceState *dev, Error **e= rrp) sysbus_realize(SYS_BUS_DEVICE(&s->hdmi), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(&s->hdmi), 0, AW_A10_HDMI_BASE); =20 + /* Display Engine Backend */ + object_property_set_uint(OBJECT(&s->de_be0), "ram-base", + AW_A10_SDRAM_BASE, &error_fatal); + sysbus_realize(SYS_BUS_DEVICE(&s->de_be0), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->de_be0), 0, AW_A10_DE_BE0_BASE); + /* MALI GPU */ sysbus_realize(SYS_BUS_DEVICE(&s->gpu), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpu), 0, AW_A10_GPU_BASE); diff --git a/hw/display/allwinner-a10-debe.c b/hw/display/allwinner-a10-deb= e.c new file mode 100644 index 0000000000..3760728eab --- /dev/null +++ b/hw/display/allwinner-a10-debe.c @@ -0,0 +1,229 @@ +/* + * Allwinner A10 Display Engine Backend emulation + * + * Copyright (C) 2023 Strahinja Jankovic + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/qdev-properties.h" +#include "hw/display/allwinner-a10-debe.h" +#include "trace.h" + +/* DEBE register offsets - only important ones */ +enum { + REG_DEBE_MODCTL =3D 0x0800, /* DE mode control */ + REG_DEBE_DISSIZE =3D 0x0808, /* DE display size */ + REG_DEBE_LAY0FB_L32ADD =3D 0x0850, /* DE Layer 0 lower 32-bit address= */ + REG_DEBE_REGBUFFCTL =3D 0x0870, /* DE buffer control register */ + REG_DEBE_ATTCTL_REG1_L0 =3D 0x08A0, /* DE Layer 0 attribute ctrl reg 1= */ +}; + +/* DEBE_DISSIZE fields */ +#define FIELD_DEBE_DISSIZE_DIS_HEIGHT (16) +#define FIELD_DEBE_DISSIZE_DIS_WIDTH (0) +#define DEBE_DISSIZE_DIS_MASK (0xFFFFu) + +/* DEBE_REGBUFFCTL fields */ +#define FIELD_DEBE_REGBUFFCTL_REGLOADCTL (1) +#define FIELD_DEBE_REGBUFFCTL_REGAUTOLOAD_DIS (2) + +/* DEBE_ATTCTL_REG1_L0 fields */ +#define FIELD_DEBE_ATTCTL_REG1_L0_LAY_FBFMT (8) +#define DEBE_ATTCTL_REG1_L0_LAY_FBFMT_MASK (0xFu) +enum { + ATTCTL_REG1_LAY_FBFMT_MONO_1BPP =3D 0, + ATTCTL_REG1_LAY_FBFMT_MONO_2BPP, + ATTCTL_REG1_LAY_FBFMT_MONO_4BPP, + ATTCTL_REG1_LAY_FBFMT_MONO_8BPP, + ATTCTL_REG1_LAY_FBFMT_COLOR_16BPP_655, + ATTCTL_REG1_LAY_FBFMT_COLOR_16BPP_565, + ATTCTL_REG1_LAY_FBFMT_COLOR_16BPP_556, + ATTCTL_REG1_LAY_FBFMT_COLOR_16BPP_1555, + ATTCTL_REG1_LAY_FBFMT_COLOR_16BPP_5551, + ATTCTL_REG1_LAY_FBFMT_COLOR_32BPP_P888, + ATTCTL_REG1_LAY_FBFMT_COLOR_32BPP_8888, + ATTCTL_REG1_LAY_FBFMT_COLOR_24BPP_888, + ATTCTL_REG1_LAY_FBFMT_COLOR_16BPP_4444, +}; + +static uint8_t debe_lay_fbfmt_bpp[] =3D { + 1, + 2, + 4, + 8, + 16, + 16, + 16, + 16, + 16, + 32, + 32, + 24, + 16 +}; + +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) + +static uint64_t allwinner_a10_debe_read(void *opaque, hwaddr offset, + unsigned size) +{ + const AwA10DEBEState *s =3D AW_A10_DEBE(opaque); + const uint32_t idx =3D REG_INDEX(offset); + uint32_t val =3D 0; + + switch (offset) { + case REG_DEBE_DISSIZE: + case REG_DEBE_LAY0FB_L32ADD: + case REG_DEBE_REGBUFFCTL: + break; + case 0x5800 ... AW_A10_DEBE_IOSIZE: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + default: + break; + } + + val =3D s->regs[idx]; + + trace_allwinner_a10_debe_read(offset, val); + + return val; +} + +static void allwinner_a10_debe_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwA10DEBEState *s =3D AW_A10_DEBE(opaque); + const uint32_t idx =3D REG_INDEX(offset); + + trace_allwinner_a10_debe_write(offset, (uint32_t)val); + + switch (offset) { + case REG_DEBE_DISSIZE: + /* Store display width and height */ + s->height =3D 1 + + ((val >> FIELD_DEBE_DISSIZE_DIS_HEIGHT) & DEBE_DISSIZE_DIS_MAS= K); + s->width =3D 1 + + ((val >> FIELD_DEBE_DISSIZE_DIS_WIDTH) & DEBE_DISSIZE_DIS_MASK= ); + s->invalidate =3D true; + break; + case REG_DEBE_LAY0FB_L32ADD: + /* Store framebuffer offset */ + s->framebuffer_offset =3D s->ram_base + (val >> 3); + if (val !=3D 0) { + s->ready =3D true; + } + break; + case REG_DEBE_REGBUFFCTL: + if (val =3D=3D + (FIELD_DEBE_REGBUFFCTL_REGLOADCTL | + FIELD_DEBE_REGBUFFCTL_REGAUTOLOAD_DIS)) { + /* Clear to indicate that register loading is done. */ + val &=3D ~FIELD_DEBE_REGBUFFCTL_REGLOADCTL; + } + break; + case REG_DEBE_ATTCTL_REG1_L0: + { + uint8_t bpp =3D (val >> FIELD_DEBE_ATTCTL_REG1_L0_LAY_FBFMT) & + DEBE_ATTCTL_REG1_L0_LAY_FBFMT_MASK; + s->bpp =3D debe_lay_fbfmt_bpp[bpp]; + } + break; + case 0x5800 ... AW_A10_DEBE_IOSIZE: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + break; + default: + break; + } + + s->regs[idx] =3D (uint32_t) val; +} + +static const MemoryRegionOps allwinner_a10_debe_ops =3D { + .read =3D allwinner_a10_debe_read, + .write =3D allwinner_a10_debe_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .impl.min_access_size =3D 4, +}; + +static void allwinner_a10_debe_reset_enter(Object *obj, ResetType type) +{ + AwA10DEBEState *s =3D AW_A10_DEBE(obj); + + memset(&s->regs[0], 0, AW_A10_DEBE_IOSIZE); +} + +static void allwinner_a10_debe_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + AwA10DEBEState *s =3D AW_A10_DEBE(obj); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_a10_debe_ops, s, + TYPE_AW_A10_DEBE, AW_A10_DEBE_IOSIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription allwinner_a10_debe_vmstate =3D { + .name =3D "allwinner-a10-debe", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AwA10DEBEState, AW_A10_DEBE_REGS_NUM), + VMSTATE_END_OF_LIST() + } +}; + +static Property allwinner_a10_debe_properties[] =3D { + DEFINE_PROP_UINT64("ram-base", AwA10DEBEState, ram_base, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void allwinner_a10_debe_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.enter =3D allwinner_a10_debe_reset_enter; + dc->vmsd =3D &allwinner_a10_debe_vmstate; + device_class_set_props(dc, allwinner_a10_debe_properties); +} + +static const TypeInfo allwinner_a10_debe_info =3D { + .name =3D TYPE_AW_A10_DEBE, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_init =3D allwinner_a10_debe_init, + .instance_size =3D sizeof(AwA10DEBEState), + .class_init =3D allwinner_a10_debe_class_init, +}; + +static void allwinner_a10_debe_register(void) +{ + type_register_static(&allwinner_a10_debe_info); +} + +type_init(allwinner_a10_debe_register) diff --git a/hw/display/meson.build b/hw/display/meson.build index a5eb01fe2b..a3ef580b1c 100644 --- a/hw/display/meson.build +++ b/hw/display/meson.build @@ -38,7 +38,8 @@ system_ss.add(when: 'CONFIG_NEXTCUBE', if_true: files('ne= xt-fb.c')) =20 system_ss.add(when: 'CONFIG_VGA', if_true: files('vga.c')) =20 -system_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10-= hdmi.c', +system_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10-= debe.c', + 'allwinner-a10-= hdmi.c', 'allwinner-gpu.= c')) =20 if (config_all_devices.has_key('CONFIG_VGA_CIRRUS') or diff --git a/hw/display/trace-events b/hw/display/trace-events index d1c0f05e52..132b66fc81 100644 --- a/hw/display/trace-events +++ b/hw/display/trace-events @@ -178,6 +178,10 @@ macfb_sense_read(uint32_t value) "video sense: 0x%"PRI= x32 macfb_sense_write(uint32_t value) "video sense: 0x%"PRIx32 macfb_update_mode(uint32_t width, uint32_t height, uint8_t depth) "setting= mode to width %"PRId32 " height %"PRId32 " size %d" =20 +# allwinner-a10-debe.c +allwinner_a10_debe_read(uint64_t offset, uint64_t data) "Read: offset 0x%"= PRIx64 " data 0x%" PRIx64 +allwinner_a10_debe_write(uint64_t offset, uint64_t data) "Write: offset 0x= %" PRIx64 " data 0x%" PRIx64 + # allwinner-a10-hdmi.c allwinner_a10_hdmi_read(uint64_t offset, uint64_t data) "Read: offset 0x%"= PRIx64 " data 0x%" PRIx64 allwinner_a10_hdmi_write(uint64_t offset, uint64_t data) "Write: offset 0x= %" PRIx64 " data 0x%" PRIx64 diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index 8109656421..2de7e402b2 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -12,6 +12,7 @@ #include "hw/rtc/allwinner-rtc.h" #include "hw/misc/allwinner-a10-ccm.h" #include "hw/misc/allwinner-a10-dramc.h" +#include "hw/display/allwinner-a10-debe.h" #include "hw/display/allwinner-a10-hdmi.h" #include "hw/display/allwinner-gpu.h" #include "hw/i2c/allwinner-i2c.h" @@ -45,6 +46,7 @@ struct AwA10State { AWI2CState i2c0; AwRtcState rtc; AwWdtState wdt; + AwA10DEBEState de_be0; AwGpuState gpu; AwA10HdmiState hdmi; MemoryRegion sram_a; diff --git a/include/hw/display/allwinner-a10-debe.h b/include/hw/display/a= llwinner-a10-debe.h new file mode 100644 index 0000000000..30727516bc --- /dev/null +++ b/include/hw/display/allwinner-a10-debe.h @@ -0,0 +1,71 @@ +/* + * Allwinner A10 Display engine Backend emulation + * + * Copyright (C) 2023 Strahinja Jankovic + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef HW_DISPLAY_ALLWINNER_A10_DEBE_H +#define HW_DISPLAY_ALLWINNER_A10_DEBE_H + +#include "qom/object.h" +#include "hw/sysbus.h" + +/** + * @name Constants + * @{ + */ + +/** Size of register I/O address space used by DEBE device */ +#define AW_A10_DEBE_IOSIZE (0x20000) + +/** Total number of known registers for DEBE */ +#define AW_A10_DEBE_REGS_NUM (AW_A10_DEBE_IOSIZE / sizeof(uint32_t)) + +/** @} */ + +/** + * @name Object model + * @{ + */ + +#define TYPE_AW_A10_DEBE "allwinner-a10-debe" +OBJECT_DECLARE_SIMPLE_TYPE(AwA10DEBEState, AW_A10_DEBE) + +/** @} */ + +/** + * Allwinner A10 DEBE object instance state. + */ +struct AwA10DEBEState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + uint32_t width; + uint32_t height; + hwaddr framebuffer_offset; + hwaddr ram_base; + uint8_t bpp; + bool ready; + bool invalidate; + + /** Maps I/O registers in physical memory */ + MemoryRegion iomem; + + /** Array of hardware registers */ + uint32_t regs[AW_A10_DEBE_REGS_NUM]; +}; + +#endif /* HW_DISPLAY_ALLWINNER_A10_DEBE_H */ --=20 2.34.1 From nobody Thu Nov 28 08:03:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1693944992; cv=none; d=zohomail.com; s=zohoarc; b=dm+M+tmZkUVL7KHDoScA4CugMqth9urwOgPy47X/qXLSMWTbxHZJIArc+4/CW+cqmZUfnABFnGaVt2c74e2D+7jNJvHs9396wHVoXChAwaRJhrC/ly7HQSvRPPS7QYhtiz8qhP6nPinLLO6nwIQo6lmdGa8/7YsPVK+1f4tnWGA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693944992; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=foOqzdGL/WyOe8+wQYwqhAt/YwvOYCJgK4mxkX6LADc=; b=J6MqG4RYmb1kHr9eY2HhEWM0r4HzqL7lEhYm2jSAZVSNirbQqSPHtQ1BMAl/Y80foR9qd8cJxGA+FqMpsL7VblCltltYlyQJPvPnscI8/QH28pqTUL/EKry1OfisJzkUT+p46QQfHdpcfm/9Uvs4lDy6WLfHBVhusc1suEjjRPI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693944992296502.10889835060595; Tue, 5 Sep 2023 13:16:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qdcRn-0004wC-Iu; Tue, 05 Sep 2023 16:14:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qdcRm-0004vL-8P; Tue, 05 Sep 2023 16:14:50 -0400 Received: from mail-lf1-x12d.google.com ([2a00:1450:4864:20::12d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qdcRh-000381-GI; Tue, 05 Sep 2023 16:14:49 -0400 Received: by mail-lf1-x12d.google.com with SMTP id 2adb3069b0e04-50079d148aeso4929304e87.3; Tue, 05 Sep 2023 13:14:44 -0700 (PDT) Received: from localhost.localdomain (81-233-187-21-no600.tbcn.telia.com. [81.233.187.21]) by smtp.gmail.com with ESMTPSA id b25-20020ac25e99000000b004ff725d1a27sm2489811lfq.234.2023.09.05.13.14.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Sep 2023 13:14:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1693944883; x=1694549683; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=foOqzdGL/WyOe8+wQYwqhAt/YwvOYCJgK4mxkX6LADc=; b=K1G3T/NhIYc6yLCS/lGzjapygPTIf3u/bwqc/51XGEJhh6zw5RxX4UNhB7mn9o7Uog Yls1bmn2B2gE2euw0xJ5V/nLYlB380cwZsZxaSuvrbPL83ZTgdON9dWQuWxWYCJ5NZ5U jQSsBLMClfOMU1xVCG90Z1tjkld0N4Bl6X9291l6wb67D91jM5jbqynvFgOOGnN7mY27 AjAlFOk993CL3V0cXDvvjrv7mxhFchVcZpUngnHrOhcNvE4KHYTH0LX0SpRUERH3x7uc bsAUdaZ3EwygRnhHtCeA9wDF4DwIHdEOpa8/W6fYNjJVnLPLnjHLBOyxZSaVnZPhZkLF BA+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693944883; x=1694549683; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=foOqzdGL/WyOe8+wQYwqhAt/YwvOYCJgK4mxkX6LADc=; b=BMA0kIlXWsKCGJNNegriipP2rGDyZuYXzn1pHh9F6GBCFony6OYwtVLc89TgbktkIN yuzVGcYB7AID7AkBfTM/vkDjcxCfan+qSCovN6IecWsBvT1U2scFgq5fjhkUVDxPvDKd 0j+sl0qlcbtJq4i2W/tZaxYMUvk0SbYwVVAHM1E4mWstzRbCnfy7x1ITgnWizfkVIgqJ jtf6pRcy49pgP5krEYaWlSVh1o2/Ar/JHln5xRFbZ8oLCjrOvQw+jIRYoDD+uKZZ/kgX VOaJpV9MeN10iLYiVAQnOK94Za/0xgGqizrh7eB+fh7T4IHL06h4LhTNraHcyW6ab019 cgxQ== X-Gm-Message-State: AOJu0YxGqABaTjqw/fq5VX/KhAQzVP3gTUrqRK5qiW5ztwPy/QRzpQnB 2JEWxuPswuMvflbk5owXJ7CpUYF3yTdCRw== X-Google-Smtp-Source: AGHT+IGB+5P+M83dB+6lYLoXYxvmnH8+bszhskQa6PEBala70BsCh98fDkcV7NmfuMSEpUBcHFuvZQ== X-Received: by 2002:a19:6441:0:b0:4ff:9a75:211e with SMTP id b1-20020a196441000000b004ff9a75211emr504479lfj.42.1693944883068; Tue, 05 Sep 2023 13:14:43 -0700 (PDT) From: Strahinja Jankovic X-Google-Original-From: Strahinja Jankovic To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Beniamino Galvani , Peter Maydell , Strahinja Jankovic Subject: [RFC Patch 4/5] hw/display: Allwinner A10 LCDC emulation Date: Tue, 5 Sep 2023 22:14:24 +0200 Message-Id: <20230905201425.118918-5-strahinja.p.jankovic@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230905201425.118918-1-strahinja.p.jankovic@gmail.com> References: <20230905201425.118918-1-strahinja.p.jankovic@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=strahinjapjankovic@gmail.com; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1693944992643100001 Content-Type: text/plain; charset="utf-8" This patch adds support for Allwinner A10 LCD controller. Current emulation supports only RGB32 colorspace and interacts with DEBE0 to obtain framebuffer address and screen size. Signed-off-by: Strahinja Jankovic --- hw/arm/allwinner-a10.c | 10 + hw/display/allwinner-a10-lcdc.c | 275 ++++++++++++++++++++++++ hw/display/meson.build | 1 + hw/display/trace-events | 5 + include/hw/arm/allwinner-a10.h | 2 + include/hw/display/allwinner-a10-lcdc.h | 77 +++++++ 6 files changed, 370 insertions(+) create mode 100644 hw/display/allwinner-a10-lcdc.c create mode 100644 include/hw/display/allwinner-a10-lcdc.h diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index 624e95af46..f93bc5266d 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -41,6 +41,7 @@ #define AW_A10_WDT_BASE 0x01c20c90 #define AW_A10_RTC_BASE 0x01c20d00 #define AW_A10_I2C0_BASE 0x01c2ac00 +#define AW_A10_LCDC0_BASE 0x01c0c000 #define AW_A10_HDMI_BASE 0x01c16000 #define AW_A10_GPU_BASE 0x01c40000 #define AW_A10_DE_BE0_BASE 0x01e60000 @@ -101,6 +102,8 @@ static void aw_a10_init(Object *obj) =20 object_initialize_child(obj, "hdmi", &s->hdmi, TYPE_AW_A10_HDMI); =20 + object_initialize_child(obj, "lcd0", &s->lcd0, TYPE_AW_A10_LCDC); + object_initialize_child(obj, "de_be0", &s->de_be0, TYPE_AW_A10_DEBE); =20 object_initialize_child(obj, "mali400", &s->gpu, TYPE_AW_GPU); @@ -230,6 +233,13 @@ static void aw_a10_realize(DeviceState *dev, Error **e= rrp) sysbus_realize(SYS_BUS_DEVICE(&s->de_be0), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(&s->de_be0), 0, AW_A10_DE_BE0_BASE); =20 + /* LCD Controller */ + object_property_set_link(OBJECT(&s->lcd0), "debe", + OBJECT(&s->de_be0), &error_fatal); + sysbus_realize(SYS_BUS_DEVICE(&s->lcd0), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->lcd0), 0, AW_A10_LCDC0_BASE); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lcd0), 0, qdev_get_gpio_in(dev, = 44)); + /* MALI GPU */ sysbus_realize(SYS_BUS_DEVICE(&s->gpu), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpu), 0, AW_A10_GPU_BASE); diff --git a/hw/display/allwinner-a10-lcdc.c b/hw/display/allwinner-a10-lcd= c.c new file mode 100644 index 0000000000..8367ac32be --- /dev/null +++ b/hw/display/allwinner-a10-lcdc.c @@ -0,0 +1,275 @@ +/* + * Allwinner A10 LCD Control Module emulation + * + * Copyright (C) 2023 Strahinja Jankovic + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "hw/qdev-properties.h" +#include "qemu/module.h" +#include "hw/display/allwinner-a10-lcdc.h" +#include "hw/irq.h" +#include "ui/pixel_ops.h" +#include "trace.h" +#include "sysemu/dma.h" +#include "framebuffer.h" + +/* LCDC register offsets */ +enum { + REG_TCON_GCTL =3D 0x0000, /* TCON Global control register */ + REG_TCON_GINT0 =3D 0x0004, /* TCON Global interrupt register 0 */ +}; + +/* TCON_GCTL register fields */ +#define REG_TCON_GCTL_EN (1 << 31) + +/* TCON_GINT0 register fields */ +#define REG_TCON_GINT0_VB_INT_EN (1 << 31) +#define REG_TCON_GINT0_VB_INT_FLAG (1 << 14) + +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) + +static void allwinner_a10_lcdc_tick(void *opaque) +{ + AwA10LcdcState *s =3D AW_A10_LCDC(opaque); + + if (s->regs[REG_INDEX(REG_TCON_GINT0)] & REG_TCON_GINT0_VB_INT_EN) { + s->regs[REG_INDEX(REG_TCON_GINT0)] |=3D REG_TCON_GINT0_VB_INT_FLAG; + qemu_irq_raise(s->irq); + } +} + +static uint64_t allwinner_a10_lcdc_read(void *opaque, hwaddr offset, + unsigned size) +{ + AwA10LcdcState *s =3D AW_A10_LCDC(opaque); + const uint32_t idx =3D REG_INDEX(offset); + uint32_t val =3D s->regs[idx]; + + switch (offset) { + case 0x800 ... AW_A10_LCDC_IOSIZE: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + default: + break; + } + + trace_allwinner_a10_lcdc_read(offset, val); + + return val; +} + +static void allwinner_a10_lcdc_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwA10LcdcState *s =3D AW_A10_LCDC(opaque); + const uint32_t idx =3D REG_INDEX(offset); + + switch (offset) { + case REG_TCON_GCTL: + s->is_enabled =3D !!REG_TCON_GCTL_EN; + break; + case REG_TCON_GINT0: + if (0 =3D=3D (val & REG_TCON_GINT0_VB_INT_FLAG)) { + qemu_irq_lower(s->irq); + } + break; + case 0x800 ... AW_A10_LCDC_IOSIZE: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + break; + default: + break; + } + + trace_allwinner_a10_lcdc_write(offset, (uint32_t)val); + + s->regs[idx] =3D (uint32_t) val; +} + +static const MemoryRegionOps allwinner_a10_lcdc_ops =3D { + .read =3D allwinner_a10_lcdc_read, + .write =3D allwinner_a10_lcdc_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, + .impl.min_access_size =3D 1, +}; + +#define COPY_PIXEL(to, from) do { *(uint32_t *)to =3D from; to +=3D 4; } w= hile (0) + +static void draw_line(void *opaque, uint8_t *d, const uint8_t *src, + int width, int deststep) +{ + uint32_t data; + unsigned int r, g, b; + while (width > 0) { + data =3D *(uint32_t *)src; + b =3D data & 0xff; + g =3D (data >> 8) & 0xff; + r =3D (data >> 16) & 0xff; + COPY_PIXEL(d, rgb_to_pixel32(r, g, b)); + width--; + src +=3D 4; + } +} + +static void allwinner_a10_lcdc_invalidate_display(void *opaque) +{ + AwA10LcdcState *s =3D AW_A10_LCDC(opaque); + qemu_console_resize(s->con, s->debe->width, s->debe->height); + s->invalidate =3D 1; +} + +static void allwinner_a10_lcdc_update_display(void *opaque) +{ + AwA10LcdcState *s =3D AW_A10_LCDC(opaque); + DisplaySurface *surface; + int step, width, height, linesize, first =3D 0, last; + + if (!s->is_enabled || !s->debe->ready) { + return; + } + + width =3D s->debe->width; + height =3D s->debe->height; + step =3D width * (s->debe->bpp >> 3); + + if (s->debe->invalidate) { + allwinner_a10_lcdc_invalidate_display(opaque); + s->debe->invalidate =3D false; + } + + surface =3D qemu_console_surface(s->con); + linesize =3D surface_stride(surface); + + if (s->invalidate) { + framebuffer_update_memory_section(&s->fbsection, + sysbus_address_space(SYS_BUS_DEVICE(s)= ), + s->debe->framebuffer_offset, + height, step); + } + + framebuffer_update_display(surface, &s->fbsection, + width, height, + step, linesize, 0, + s->invalidate, + draw_line, NULL, + &first, &last); + + trace_allwinner_a10_draw(first, last, s->invalidate); + + if (first >=3D 0) { + dpy_gfx_update(s->con, 0, first, width, last - first + 1); + } + s->invalidate =3D 0; + +} + +static const GraphicHwOps allwinner_a10_lcdc_gfx_ops =3D { + .invalidate =3D allwinner_a10_lcdc_invalidate_display, + .gfx_update =3D allwinner_a10_lcdc_update_display, +}; + +static void allwinner_a10_lcdc_reset_enter(Object *obj, ResetType type) +{ + AwA10LcdcState *s =3D AW_A10_LCDC(obj); + s->invalidate =3D 1; +} + +static void allwinner_a10_lcdc_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + AwA10LcdcState *s =3D AW_A10_LCDC(obj); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_a10_lcdc_ops, s, + TYPE_AW_A10_LCDC, AW_A10_LCDC_IOSIZE); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); + s->invalidate =3D 1; + s->is_enabled =3D 0; +} + +static void allwinner_a10_lcdc_realize(DeviceState *dev, Error **errp) +{ + AwA10LcdcState *s =3D AW_A10_LCDC(dev); + + s->timer =3D ptimer_init(allwinner_a10_lcdc_tick, s, + PTIMER_POLICY_NO_IMMEDIATE_TRIGGER | + PTIMER_POLICY_NO_IMMEDIATE_RELOAD | + PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); + + ptimer_transaction_begin(s->timer); + /* Set to 60Hz */ + ptimer_set_freq(s->timer, 60); + ptimer_set_limit(s->timer, 0x1, 1); + ptimer_run(s->timer, 0); + ptimer_transaction_commit(s->timer); + + s->invalidate =3D 1; + s->con =3D graphic_console_init(NULL, 0, &allwinner_a10_lcdc_gfx_ops, = s); + qemu_console_resize(s->con, s->debe->width, s->debe->height); +} + +static const VMStateDescription allwinner_a10_lcdc_vmstate =3D { + .name =3D "allwinner-a10_lcdc", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AwA10LcdcState, AW_A10_LCDC_REGS_NUM), + VMSTATE_END_OF_LIST() + } +}; + +static Property allwinner_a10_lcdc_properties[] =3D { + DEFINE_PROP_LINK("debe", AwA10LcdcState, debe, + TYPE_AW_A10_DEBE, AwA10DEBEState *), + DEFINE_PROP_END_OF_LIST(), +}; + +static void allwinner_a10_lcdc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.enter =3D allwinner_a10_lcdc_reset_enter; + dc->vmsd =3D &allwinner_a10_lcdc_vmstate; + dc->realize =3D allwinner_a10_lcdc_realize; + device_class_set_props(dc, allwinner_a10_lcdc_properties); +} + +static const TypeInfo allwinner_a10_lcdc_info =3D { + .name =3D TYPE_AW_A10_LCDC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_init =3D allwinner_a10_lcdc_init, + .instance_size =3D sizeof(AwA10LcdcState), + .class_init =3D allwinner_a10_lcdc_class_init, +}; + +static void allwinner_a10_lcdc_register(void) +{ + type_register_static(&allwinner_a10_lcdc_info); +} + +type_init(allwinner_a10_lcdc_register) diff --git a/hw/display/meson.build b/hw/display/meson.build index a3ef580b1c..e233026fdd 100644 --- a/hw/display/meson.build +++ b/hw/display/meson.build @@ -40,6 +40,7 @@ system_ss.add(when: 'CONFIG_VGA', if_true: files('vga.c')) =20 system_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10-= debe.c', 'allwinner-a10-= hdmi.c', + 'allwinner-a10-= lcdc.c', 'allwinner-gpu.= c')) =20 if (config_all_devices.has_key('CONFIG_VGA_CIRRUS') or diff --git a/hw/display/trace-events b/hw/display/trace-events index 132b66fc81..4b962d6eda 100644 --- a/hw/display/trace-events +++ b/hw/display/trace-events @@ -186,6 +186,11 @@ allwinner_a10_debe_write(uint64_t offset, uint64_t dat= a) "Write: offset 0x%" PRI allwinner_a10_hdmi_read(uint64_t offset, uint64_t data) "Read: offset 0x%"= PRIx64 " data 0x%" PRIx64 allwinner_a10_hdmi_write(uint64_t offset, uint64_t data) "Write: offset 0x= %" PRIx64 " data 0x%" PRIx64 =20 +# allwinner-a10-lcdc.c +allwinner_a10_lcdc_read(uint64_t offset, uint64_t data) "Read: offset 0x%"= PRIx64 " data 0x%" PRIx64 +allwinner_a10_lcdc_write(uint64_t offset, uint64_t data) "Write: offset 0x= %" PRIx64 " data 0x%" PRIx64 +allwinner_a10_draw(uint32_t first, uint32_t last, uint32_t invalidate) "Dr= aw: 0x%x, 0x%x, 0x%x" + # allwinner-gpu.c allwinner_gpu_read(uint64_t offset, uint64_t data) "Read: offset 0x%" PRIx= 64 " data 0x%" PRIx64 allwinner_gpu_write(uint64_t offset, uint64_t data) "Write: offset 0x%" PR= Ix64 " data 0x%" PRIx64 diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index 2de7e402b2..c99ca6c1c4 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -14,6 +14,7 @@ #include "hw/misc/allwinner-a10-dramc.h" #include "hw/display/allwinner-a10-debe.h" #include "hw/display/allwinner-a10-hdmi.h" +#include "hw/display/allwinner-a10-lcdc.h" #include "hw/display/allwinner-gpu.h" #include "hw/i2c/allwinner-i2c.h" #include "hw/watchdog/allwinner-wdt.h" @@ -49,6 +50,7 @@ struct AwA10State { AwA10DEBEState de_be0; AwGpuState gpu; AwA10HdmiState hdmi; + AwA10LcdcState lcd0; MemoryRegion sram_a; EHCISysBusState ehci[AW_A10_NUM_USB]; OHCISysBusState ohci[AW_A10_NUM_USB]; diff --git a/include/hw/display/allwinner-a10-lcdc.h b/include/hw/display/a= llwinner-a10-lcdc.h new file mode 100644 index 0000000000..82f6d397fb --- /dev/null +++ b/include/hw/display/allwinner-a10-lcdc.h @@ -0,0 +1,77 @@ +/* + * Allwinner A10 LCD Control Module emulation + * + * Copyright (C) 2023 Strahinja Jankovic + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef HW_DISPLAY_ALLWINNER_A10_LCDC_H +#define HW_DISPLAY_ALLWINNER_A10_LCDC_H + +#include "qom/object.h" +#include "hw/ptimer.h" +#include "hw/sysbus.h" +#include "ui/console.h" +#include "hw/display/allwinner-a10-debe.h" + +/** + * @name Constants + * @{ + */ + +/** Size of register I/O address space used by LCDC device */ +#define AW_A10_LCDC_IOSIZE (0x1000) + +/** Total number of known registers */ +#define AW_A10_LCDC_REGS_NUM (AW_A10_LCDC_IOSIZE / sizeof(uint32_t)) + +/** @} */ + +/** + * @name Object model + * @{ + */ + +#define TYPE_AW_A10_LCDC "allwinner-a10-lcdc" +OBJECT_DECLARE_SIMPLE_TYPE(AwA10LcdcState, AW_A10_LCDC) + +/** @} */ + +/** + * Allwinner A10 LCDC object instance state. + */ +struct AwA10LcdcState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + qemu_irq irq; + struct ptimer_state *timer; + QemuConsole *con; + + MemoryRegionSection fbsection; + + int invalidate; + bool is_enabled; + + AwA10DEBEState *debe; + + /** Maps I/O registers in physical memory */ + MemoryRegion iomem; + + /** Array of hardware registers */ + uint32_t regs[AW_A10_LCDC_REGS_NUM]; +}; + +#endif /* HW_DISPLAY_ALLWINNER_A10_LCDC_H */ --=20 2.34.1 From nobody Thu Nov 28 08:03:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1693945000; cv=none; d=zohomail.com; s=zohoarc; b=liB4+copPOyfJ9gytmJ8ckR3qFaD+M1CQgMtPzQMwL4HPmJyCR/VhPrWICpDaEn4he6ZtvLEpaTPYZuZeSsVO/FzaGyg7MCs5vrd26UweE6CLEVqOU/cNqjeS8TkmNecblbs33Pqo8cRxFANx/oNauCGgX5CrdPs0KjpEgN0Me0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693945000; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=E8sff0kDi7ewJlSnvd0fkQyO+2KmaSFxSHdiLSeMee0=; b=Q4L9lHgQa74bteQX+10aJThCTvaevNLuch0qNmjUcgJdsoU1mehOMe9N1BBMAuJue2r2GwEve0ymhtcf3DObQxXZnuFS/jtWxF6Cnh5ma0UNoGd/ecONpU8u1rUd4M5VfDP2N9BRHtnvQK7Hy/Ow6Jzkaj5Bb4R7xj9hdhmwZsk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693945000536921.1316106680457; Tue, 5 Sep 2023 13:16:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qdcRn-0004wf-QJ; Tue, 05 Sep 2023 16:14:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qdcRm-0004vN-Cu; Tue, 05 Sep 2023 16:14:50 -0400 Received: from mail-lf1-x132.google.com ([2a00:1450:4864:20::132]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qdcRi-00038D-R3; Tue, 05 Sep 2023 16:14:50 -0400 Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-500760b296aso290655e87.0; Tue, 05 Sep 2023 13:14:46 -0700 (PDT) Received: from localhost.localdomain (81-233-187-21-no600.tbcn.telia.com. [81.233.187.21]) by smtp.gmail.com with ESMTPSA id b25-20020ac25e99000000b004ff725d1a27sm2489811lfq.234.2023.09.05.13.14.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Sep 2023 13:14:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1693944884; x=1694549684; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E8sff0kDi7ewJlSnvd0fkQyO+2KmaSFxSHdiLSeMee0=; b=ifdIAPqpyH5rQF/4sTOhDd3GkA2jKHVhf9t6IxrUvtN2iy44bRq1woB4/t3q6uHTSy CMGhMyqcc1TQx62puiuqBpOIOxIC2vJwsge2gbJrKkeYVQNtliOGqAyxG08s06bjkrzp m9nHKo0CBM73YNuMcuOgZtk4GejH/1nPsk+BL+4+OP+sN8bhjDCKoQqA2VI7P1+wo9Uo h/bcnZbIJzuxb73fhVVvoI1rAl2CvtU5zA2x9Q+nY2VZy1bvTyeSD14+bfx1t0HURvCu nMkeod/YUCgKGRTcsMR2C5WQr+j5E5FXFi8vYVwqh9Hfw9pn4uALuzb0wDLTHGJumhKu puHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693944884; x=1694549684; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E8sff0kDi7ewJlSnvd0fkQyO+2KmaSFxSHdiLSeMee0=; b=gIoiqiwSSXINas1Wk/tzvt3dx2GQh2QP9m8pG/icPVeUWjYnYcB1WP0TZKpgX7tO5W FenwWsfBNd32XdO+EF/fXiyhTi5SszCiMF1Bvb0iHeNC07+L01SIayWG2zKsYpRpa85b EPMJTvj2/cEADPbq0R5icwVWLtxt3X9hu40tpRX9NatVguOg65iD64HqZF3mxgbSuW4N hftF9zr5/xTpIk5gWnrleU9gOWNpk61jdsBQyHHPuqEoaqHAEvISV6XcBuLaQAmCuw7D aHX8LQsQvjWIVddGLIM+n9IX9H1QMbKP15R1AqUALt0UewyfMe1M7Hd36dxU3Y5hEYO8 p3Dg== X-Gm-Message-State: AOJu0Ywjp1xFf6/UslPUTc6wjJpQBBdHzYrB4RPkc2DgGwTYG4tRNc27 u3nyYniVK/uNEJ0H3+UJ0LxsyeU288tGOQ== X-Google-Smtp-Source: AGHT+IEtdsNkr2HK9pWKXsOeD0LZaxYJmFBi4jMuVX6jXWa2FaxZxA/TMMU3AWw6Pcg63HhKWqV0qA== X-Received: by 2002:a05:6512:308d:b0:500:b890:fb3c with SMTP id z13-20020a056512308d00b00500b890fb3cmr426120lfd.27.1693944884535; Tue, 05 Sep 2023 13:14:44 -0700 (PDT) From: Strahinja Jankovic X-Google-Original-From: Strahinja Jankovic To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Beniamino Galvani , Peter Maydell , Strahinja Jankovic Subject: [RFC Patch 5/5] hw/input: Add Allwinner-A10 PS2 emulation Date: Tue, 5 Sep 2023 22:14:25 +0200 Message-Id: <20230905201425.118918-6-strahinja.p.jankovic@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230905201425.118918-1-strahinja.p.jankovic@gmail.com> References: <20230905201425.118918-1-strahinja.p.jankovic@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=strahinjapjankovic@gmail.com; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1693945001750100001 Content-Type: text/plain; charset="utf-8" Add emulation for PS2-0 and PS2-1 for keyboard/mouse. Signed-off-by: Strahinja Jankovic --- hw/arm/allwinner-a10.c | 18 ++ hw/input/allwinner-a10-ps2.c | 345 +++++++++++++++++++++++++++ hw/input/meson.build | 2 + include/hw/arm/allwinner-a10.h | 3 + include/hw/input/allwinner-a10-ps2.h | 96 ++++++++ 5 files changed, 464 insertions(+) create mode 100644 hw/input/allwinner-a10-ps2.c create mode 100644 include/hw/input/allwinner-a10-ps2.h diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index f93bc5266d..3d25dbb4e3 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -40,6 +40,8 @@ #define AW_A10_SATA_BASE 0x01c18000 #define AW_A10_WDT_BASE 0x01c20c90 #define AW_A10_RTC_BASE 0x01c20d00 +#define AW_A10_PS2_0_BASE 0x01c2a000 +#define AW_A10_PS2_1_BASE 0x01c2a400 #define AW_A10_I2C0_BASE 0x01c2ac00 #define AW_A10_LCDC0_BASE 0x01c0c000 #define AW_A10_HDMI_BASE 0x01c16000 @@ -107,6 +109,12 @@ static void aw_a10_init(Object *obj) object_initialize_child(obj, "de_be0", &s->de_be0, TYPE_AW_A10_DEBE); =20 object_initialize_child(obj, "mali400", &s->gpu, TYPE_AW_GPU); + + object_initialize_child(obj, "keyboard", &s->kbd, + TYPE_AW_A10_PS2_KBD_DEVICE); + + object_initialize_child(obj, "mouse", &s->mouse, + TYPE_AW_A10_PS2_MOUSE_DEVICE); } =20 static void aw_a10_realize(DeviceState *dev, Error **errp) @@ -243,6 +251,16 @@ static void aw_a10_realize(DeviceState *dev, Error **e= rrp) /* MALI GPU */ sysbus_realize(SYS_BUS_DEVICE(&s->gpu), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpu), 0, AW_A10_GPU_BASE); + + /* PS2-0 - keyboard */ + sysbus_realize(SYS_BUS_DEVICE(&s->kbd), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->kbd), 0, AW_A10_PS2_0_BASE); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->kbd), 0, qdev_get_gpio_in(dev, 6= 2)); + + /* PS2-1 - mouse */ + sysbus_realize(SYS_BUS_DEVICE(&s->mouse), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->mouse), 0, AW_A10_PS2_1_BASE); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->mouse), 0, qdev_get_gpio_in(dev,= 63)); } =20 static void aw_a10_class_init(ObjectClass *oc, void *data) diff --git a/hw/input/allwinner-a10-ps2.c b/hw/input/allwinner-a10-ps2.c new file mode 100644 index 0000000000..c4b09c0ea3 --- /dev/null +++ b/hw/input/allwinner-a10-ps2.c @@ -0,0 +1,345 @@ +/* + * Allwinner A10 PS2 Module emulation + * + * Copyright (C) 2023 Strahinja Jankovic + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/input/allwinner-a10-ps2.h" +#include "hw/input/ps2.h" +#include "hw/irq.h" + +/* PS2 register offsets */ +enum { + REG_GCTL =3D 0x0000, /* Global Control Reg */ + REG_DATA =3D 0x0004, /* Data Reg */ + REG_LCTL =3D 0x0008, /* Line Control Reg */ + REG_LSTS =3D 0x000C, /* Line Status Reg */ + REG_FCTL =3D 0x0010, /* FIFO Control Reg */ + REG_FSTS =3D 0x0014, /* FIFO Status Reg */ + REG_CLKDR =3D 0x0018, /* Clock Divider Reg */ +}; + +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) + +/* PS2 register reset values */ +enum { + REG_GCTL_RST =3D 0x00000002, + REG_DATA_RST =3D 0x00000000, + REG_LCTL_RST =3D 0x00000000, + REG_LSTS_RST =3D 0x00030000, + REG_FCTL_RST =3D 0x00000000, + REG_FSTS_RST =3D 0x00000100, + REG_CLKDR_RST =3D 0x00002F4F, +}; + +/* REG_GCTL Fields */ +#define FIELD_REG_GCTL_SOFT_RST (1 << 2) +#define FIELD_REG_GCTL_INT_EN (1 << 3) +#define FIELD_REG_GCTL_INT_FLAG (1 << 4) + +/* REG_FCTL Fields */ +#define FIELD_REG_FCTL_RXRDY_IEN (1 << 0) +#define FIELD_REG_FCTL_TXRDY_IEN (1 << 8) + +/* REG_FSTS Fields */ +#define FIELD_REG_FSTS_RX_RDY (1 << 0) +#define FIELD_REG_FSTS_TX_RDY (1 << 8) +#define FIELD_REG_FSTS_RX_LEVEL1 (1 << 16) + +static int allwinner_a10_ps2_fctl_is_irq(AwA10PS2State *s) +{ + return (s->regs[REG_INDEX(REG_FCTL)] & FIELD_REG_FCTL_TXRDY_IEN) || + (s->pending && + (s->regs[REG_INDEX(REG_FCTL)] & FIELD_REG_FCTL_RXRDY_IEN)); +} + +static void allwinner_a10_ps2_update_irq(AwA10PS2State *s) +{ + int level =3D (s->regs[REG_INDEX(REG_GCTL)] & FIELD_REG_GCTL_INT_EN) && + allwinner_a10_ps2_fctl_is_irq(s); + + qemu_set_irq(s->irq, level); +} + +static void allwinner_a10_ps2_set_irq(void *opaque, int n, int level) +{ + AwA10PS2State *s =3D (AwA10PS2State *)opaque; + + s->pending =3D level; + allwinner_a10_ps2_update_irq(s); +} + +static uint64_t allwinner_a10_ps2_read(void *opaque, hwaddr offset, + unsigned size) +{ + AwA10PS2State *s =3D AW_A10_PS2(opaque); + const uint32_t idx =3D REG_INDEX(offset); + + switch (offset) { + case REG_FSTS: + { + uint32_t stat =3D FIELD_REG_FSTS_TX_RDY; + if (s->pending) { + stat |=3D FIELD_REG_FSTS_RX_LEVEL1 | FIELD_REG_FSTS_RX_RDY; + } + return stat; + } + break; + case REG_DATA: + if (s->pending) { + s->last =3D ps2_read_data(s->ps2dev); + } + return s->last; + case REG_GCTL: + { + if (allwinner_a10_ps2_fctl_is_irq(s)) { + s->regs[idx] |=3D FIELD_REG_GCTL_INT_FLAG; + } else { + s->regs[idx] &=3D FIELD_REG_GCTL_INT_FLAG; + } + } + break; + case REG_LCTL: + case REG_LSTS: + case REG_FCTL: + case REG_CLKDR: + break; + case 0x1C ... AW_A10_PS2_IOSIZE: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + default: + qemu_log_mask(LOG_UNIMP, "%s: unimplemented read offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + return s->regs[idx]; +} + +static void allwinner_a10_ps2_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwA10PS2State *s =3D AW_A10_PS2(opaque); + const uint32_t idx =3D REG_INDEX(offset); + + s->regs[idx] =3D (uint32_t) val; + + switch (offset) { + case REG_GCTL: + allwinner_a10_ps2_update_irq(s); + s->regs[idx] &=3D ~FIELD_REG_GCTL_SOFT_RST; + break; + case REG_DATA: + /* ??? This should toggle the TX interrupt line. */ + /* ??? This means kbd/mouse can block each other. */ + if (s->is_mouse) { + ps2_write_mouse(PS2_MOUSE_DEVICE(s->ps2dev), val); + } else { + ps2_write_keyboard(PS2_KBD_DEVICE(s->ps2dev), val); + } + break; + case REG_LCTL: + case REG_LSTS: + case REG_FCTL: + case REG_FSTS: + case REG_CLKDR: + break; + case 0x1C ... AW_A10_PS2_IOSIZE: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n", + __func__, (uint32_t)offset); + break; + } +} + +static const MemoryRegionOps allwinner_a10_ps2_ops =3D { + .read =3D allwinner_a10_ps2_read, + .write =3D allwinner_a10_ps2_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .impl.min_access_size =3D 4, +}; + +static const VMStateDescription allwinner_a10_ps2_vmstate =3D { + .name =3D "allwinner-a10-ps2", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AwA10PS2State, AW_A10_PS2_REGS_NUM), + VMSTATE_INT32(pending, AwA10PS2State), + VMSTATE_UINT32(last, AwA10PS2State), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_a10_ps2_realize(DeviceState *dev, Error **errp) +{ + AwA10PS2State *s =3D AW_A10_PS2(dev); + + qdev_connect_gpio_out(DEVICE(s->ps2dev), PS2_DEVICE_IRQ, + qdev_get_gpio_in_named(dev, "ps2-input-irq", 0)); +} + +static void allwinner_a10_ps2_kbd_realize(DeviceState *dev, Error **errp) +{ + AwA10PS2DeviceClass *pdc =3D AW_A10_PS2_GET_CLASS(dev); + AwA10PS2KbdState *s =3D AW_A10_PS2_KBD_DEVICE(dev); + AwA10PS2State *ps =3D AW_A10_PS2(dev); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->kbd), errp)) { + return; + } + + ps->ps2dev =3D PS2_DEVICE(&s->kbd); + pdc->parent_realize(dev, errp); +} + +static void allwinner_a10_ps2_kbd_init(Object *obj) +{ + AwA10PS2KbdState *s =3D AW_A10_PS2_KBD_DEVICE(obj); + AwA10PS2State *ps =3D AW_A10_PS2(obj); + + ps->is_mouse =3D false; + object_initialize_child(obj, "kbd", &s->kbd, TYPE_PS2_KBD_DEVICE); +} + +static void allwinner_a10_ps2_mouse_realize(DeviceState *dev, Error **errp) +{ + AwA10PS2DeviceClass *pdc =3D AW_A10_PS2_GET_CLASS(dev); + AwA10PS2MouseState *s =3D AW_A10_PS2_MOUSE_DEVICE(dev); + AwA10PS2State *ps =3D AW_A10_PS2(dev); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->mouse), errp)) { + return; + } + + ps->ps2dev =3D PS2_DEVICE(&s->mouse); + pdc->parent_realize(dev, errp); +} + +static void allwinner_a10_ps2_mouse_init(Object *obj) +{ + AwA10PS2MouseState *s =3D AW_A10_PS2_MOUSE_DEVICE(obj); + AwA10PS2State *ps =3D AW_A10_PS2(obj); + + ps->is_mouse =3D true; + object_initialize_child(obj, "mouse", &s->mouse, TYPE_PS2_MOUSE_DEVICE= ); +} + +static void allwinner_a10_ps2_kbd_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + AwA10PS2DeviceClass *pdc =3D AW_A10_PS2_CLASS(oc); + + device_class_set_parent_realize(dc, allwinner_a10_ps2_kbd_realize, + &pdc->parent_realize); +} + +static const TypeInfo allwinner_a10_ps2_kbd_info =3D { + .name =3D TYPE_AW_A10_PS2_KBD_DEVICE, + .parent =3D TYPE_AW_A10_PS2, + .instance_init =3D allwinner_a10_ps2_kbd_init, + .instance_size =3D sizeof(AwA10PS2KbdState), + .class_init =3D allwinner_a10_ps2_kbd_class_init, +}; + +static void allwinner_a10_ps2_mouse_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + AwA10PS2DeviceClass *pdc =3D AW_A10_PS2_CLASS(oc); + + device_class_set_parent_realize(dc, allwinner_a10_ps2_mouse_realize, + &pdc->parent_realize); +} + +static const TypeInfo allwinner_a10_ps2_mouse_info =3D { + .name =3D TYPE_AW_A10_PS2_MOUSE_DEVICE, + .parent =3D TYPE_AW_A10_PS2, + .instance_init =3D allwinner_a10_ps2_mouse_init, + .instance_size =3D sizeof(AwA10PS2MouseState), + .class_init =3D allwinner_a10_ps2_mouse_class_init, +}; + +static void allwinner_a10_ps2_reset_enter(Object *obj, ResetType type) +{ + AwA10PS2State *s =3D AW_A10_PS2(obj); + + /* Set default values for registers */ + s->regs[REG_INDEX(REG_GCTL)] =3D REG_GCTL_RST; + s->regs[REG_INDEX(REG_DATA)] =3D REG_DATA_RST; + s->regs[REG_INDEX(REG_LCTL)] =3D REG_LCTL_RST; + s->regs[REG_INDEX(REG_LSTS)] =3D REG_LSTS_RST; + s->regs[REG_INDEX(REG_FCTL)] =3D REG_FCTL_RST; + s->regs[REG_INDEX(REG_FSTS)] =3D REG_FSTS_RST; + s->regs[REG_INDEX(REG_CLKDR)] =3D REG_CLKDR_RST; +} + +static void allwinner_a10_ps2_init(Object *obj) +{ + AwA10PS2State *s =3D AW_A10_PS2(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &allwinner_a10_ps2_ops, s, + "allwinner-a10-ps2", AW_A10_PS2_IOSIZE); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); + + qdev_init_gpio_in_named(DEVICE(obj), allwinner_a10_ps2_set_irq, + "ps2-input-irq", 1); +} + +static void allwinner_a10_ps2_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + ResettableClass *rc =3D RESETTABLE_CLASS(oc); + + rc->phases.enter =3D allwinner_a10_ps2_reset_enter; + dc->realize =3D allwinner_a10_ps2_realize; + dc->vmsd =3D &allwinner_a10_ps2_vmstate; +} + +static const TypeInfo allwinner_a10_ps2_type_info =3D { + .name =3D TYPE_AW_A10_PS2, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_init =3D allwinner_a10_ps2_init, + .instance_size =3D sizeof(AwA10PS2State), + .class_init =3D allwinner_a10_ps2_class_init, + .class_size =3D sizeof(AwA10PS2DeviceClass), + .abstract =3D true, + .class_init =3D allwinner_a10_ps2_class_init, +}; + +static void allwinner_a10_ps2_register_types(void) +{ + type_register_static(&allwinner_a10_ps2_type_info); + type_register_static(&allwinner_a10_ps2_kbd_info); + type_register_static(&allwinner_a10_ps2_mouse_info); +} + +type_init(allwinner_a10_ps2_register_types) diff --git a/hw/input/meson.build b/hw/input/meson.build index c0d4482180..b7bf4d9c9a 100644 --- a/hw/input/meson.build +++ b/hw/input/meson.build @@ -16,3 +16,5 @@ system_ss.add(when: 'CONFIG_VHOST_USER_INPUT', if_true: f= iles('vhost-user-input. system_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_keypad.c')) system_ss.add(when: 'CONFIG_TSC210X', if_true: files('tsc210x.c')) system_ss.add(when: 'CONFIG_LASIPS2', if_true: files('lasips2.c')) + +system_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10-= ps2.c')) diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index c99ca6c1c4..163cc3af2b 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -17,6 +17,7 @@ #include "hw/display/allwinner-a10-lcdc.h" #include "hw/display/allwinner-gpu.h" #include "hw/i2c/allwinner-i2c.h" +#include "hw/input/allwinner-a10-ps2.h" #include "hw/watchdog/allwinner-wdt.h" #include "sysemu/block-backend.h" =20 @@ -51,6 +52,8 @@ struct AwA10State { AwGpuState gpu; AwA10HdmiState hdmi; AwA10LcdcState lcd0; + AwA10PS2KbdState kbd; + AwA10PS2MouseState mouse; MemoryRegion sram_a; EHCISysBusState ehci[AW_A10_NUM_USB]; OHCISysBusState ohci[AW_A10_NUM_USB]; diff --git a/include/hw/input/allwinner-a10-ps2.h b/include/hw/input/allwin= ner-a10-ps2.h new file mode 100644 index 0000000000..230026bf28 --- /dev/null +++ b/include/hw/input/allwinner-a10-ps2.h @@ -0,0 +1,96 @@ +/* + * Allwinner A10 PS2 Module emulation + * + * Copyright (C) 2023 Strahinja Jankovic + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef HW_INPUT_ALLWINNER_A10_PS2_H +#define HW_INPUT_ALLWINNER_A10_PS2_H + +#include "qom/object.h" +#include "hw/sysbus.h" +#include "hw/input/ps2.h" + +/** + * @name Constants + * @{ + */ + +/** Size of register I/O address space used by CCM device */ +#define AW_A10_PS2_IOSIZE (0x400) + +/** Total number of known registers */ +#define AW_A10_PS2_REGS_NUM (AW_A10_PS2_IOSIZE / sizeof(uint32_t)) + +/** @} */ + +struct AwA10PS2DeviceClass { + SysBusDeviceClass parent_class; + + DeviceRealize parent_realize; +}; + +/** + * @name Object model + * @{ + */ + +#define TYPE_AW_A10_PS2 "allwinner-a10-ps2" +OBJECT_DECLARE_TYPE(AwA10PS2State, AwA10PS2DeviceClass, AW_A10_PS2) + +/** @} */ + +/** + * Allwinner A10 PS2 object instance state. + */ +struct AwA10PS2State { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + /** Maps I/O registers in physical memory */ + MemoryRegion iomem; + + PS2State *ps2dev; + + /** Array of hardware registers */ + uint32_t regs[AW_A10_PS2_REGS_NUM]; + int pending; + uint32_t last; + qemu_irq irq; + bool is_mouse; +}; + +#define TYPE_AW_A10_PS2_KBD_DEVICE "allwinner-a10-ps2-keyboard" +OBJECT_DECLARE_SIMPLE_TYPE(AwA10PS2KbdState, AW_A10_PS2_KBD_DEVICE) + +struct AwA10PS2KbdState { + AwA10PS2State parent_obj; + + PS2KbdState kbd; +}; + +#define TYPE_AW_A10_PS2_MOUSE_DEVICE "allwinner-a10-ps2-mouse" +OBJECT_DECLARE_SIMPLE_TYPE(AwA10PS2MouseState, AW_A10_PS2_MOUSE_DEVICE) + +struct AwA10PS2MouseState { + AwA10PS2State parent_obj; + + PS2MouseState mouse; +}; + + +#endif /* HW_INPUT_ALLWINNER_A10_PS2_H */ --=20 2.34.1