From nobody Tue Feb 10 10:19:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693601082; cv=none; d=zohomail.com; s=zohoarc; b=lH5JL8i03oIt2LFQ4Fgf66ykW4Y2itmEOIPNLuZPgoKQWiBBfcTLM8Wr4oxJ5TxraAyUkZ4GdbeLpBhmKCwefwDa+W3NMrVlLSsYr4jnKMuAj2QiW2+BPxx+xN0xaoncfxYGoIs0OJrEgP9lusTcTpPSDJRpCegW1WLAZHzkEG8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693601082; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HN9bdDKpCXsqx9IM4u0+R/+OpGOMVkY0zwFC+KcDdss=; b=G6hqlS0ub+MCjw03Q466rbOym7+/beAeDC+DDWKxCIk6vl10Deh0SEvAI6xxozfIJ+TgYUMQfX3pwEDDuqXfLpvjI4TLgUZowdoSIZ41UcvuENjfglZnvG+ZFltY4ldxeAbSA8Zq6d0BS5TPBlHyV1rroK8jJ4MN1Whe2aJ6Z5g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693601082201105.3178103412207; Fri, 1 Sep 2023 13:44:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qcAyz-00071M-Po; Fri, 01 Sep 2023 16:43:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qcAyq-0006wv-1W for qemu-devel@nongnu.org; Fri, 01 Sep 2023 16:43:00 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qcAyl-0001wi-U3 for qemu-devel@nongnu.org; Fri, 01 Sep 2023 16:42:59 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-68c0d262933so2072876b3a.0 for ; Fri, 01 Sep 2023 13:42:55 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id j15-20020aa78d0f000000b0068c97a4eb0dsm3320666pfe.191.2023.09.01.13.42.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Sep 2023 13:42:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693600974; x=1694205774; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HN9bdDKpCXsqx9IM4u0+R/+OpGOMVkY0zwFC+KcDdss=; b=i7b0PwzJAd7ZeLiweZG3er6WuQwE5Td7xg9zK3tNFktCUWwVCSMG6IBGcLNS3LyTGP Wn+XkIWCczqOrJo9LoTJ10ugss9ukkZr8d12hqJMZfra8d3dnP3OhEZOvLqKyosbZsFV OFhAuMN00Rs0ZpRAI5VYoy20LZ4T7KNuTwKPYXQ+wjk/rAWsTmgXzTDSzRBzNzm4Gu8U heuYmf6koXdbOasuw9SaxgKxVYOCz6wwAqUU9GVuRGBu6cWOQjXPyJdzkMdOM3rG24yB cNX+xDA7bfomqmpy/SnZJ+iNGzwVBKx/kTbKGW6IlPsmaiBqvBDZKeymnarPnvQWw1F/ de6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693600974; x=1694205774; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HN9bdDKpCXsqx9IM4u0+R/+OpGOMVkY0zwFC+KcDdss=; b=PVqmgyjrBDWjie9/H73krnOnLbdlp78BNaPZxjBzNG+0mTfcOS0G6HradHcHKJerFi L3fviSOnheCQnRXZDQVCJ6ZLJdcrSCE0BpD0PBmtGt12zPRNWuNbCJLHKl2nWIQTAQqn 4cSlrlBdTUJmnv26cp638YHbvr03sUaNjAnZGZeUMnlfcO8Ej39f7mDM8/K8xJYTz/ES 6fM6AtAiMOJJA6cfS/hc0jRx5GqZOP3e3X6mQ+OZXvjPC+80WEwWL4Ey0ntYa6RSQuyZ eF+//P+tvm3yRn5zoD8/O9NA+YsLVk4YIIL4tEwOXLcXJSnm+P0CR4TRWVWXO50dzp7c KOTw== X-Gm-Message-State: AOJu0YyVAkmk3jY7vo6TYEvGjJ1IKfbuNS5QibEujHavmB2KuQVQCyJH sjeLEiaOr0AwTW4L4RbDAwqDCaFP9VaUNDNZPH8= X-Google-Smtp-Source: AGHT+IFTVmOAAiXLgMozC39CZm79BhemktokayZtDKBpXGCyBkfguTgNLqaB+3mYjMVdjkq/tqPHDQ== X-Received: by 2002:a05:6a21:7746:b0:138:60e:9bb with SMTP id bc6-20020a056a21774600b00138060e09bbmr3623655pzc.28.1693600974411; Fri, 01 Sep 2023 13:42:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 02/13] linux-user: Emulate /proc/cpuinfo on aarch64 and arm Date: Fri, 1 Sep 2023 13:42:40 -0700 Message-Id: <20230901204251.137307-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230901204251.137307-1-richard.henderson@linaro.org> References: <20230901204251.137307-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693601084294100002 Content-Type: text/plain; charset="utf-8" From: Helge Deller Add emulation for /proc/cpuinfo for arm architecture. The output below mimics output as seen on debian porterboxes. aarch64 output example: processor : 0 model name : ARMv8 Processor rev 0 (v8l) BogoMIPS : 100.00 Features : swp half thumb fast_mult vfp edsp neon vfpv3 tls vfpv4 id= iva idivt vfpd32 lpae aes pmull sha1 sha2 crc32 CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x1 CPU part : 0xd07 CPU revision : 0 arm 32-bit output example: processor : 0 model name : ARMv7 Processor rev 5 (armv7l) BogoMIPS : 100.00 Features : swp half thumb fast_mult vfp edsp thumbee neon vfpv3 tls vfpv4 i= diva idivt vfpd32 lpae CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x0f CPU part : 0xc07 CPU revision : 5 Signed-off-by: Helge Deller Reviewed-by: Richard Henderson Message-Id: <20230803214450.647040-3-deller@gmx.de> Signed-off-by: Richard Henderson --- linux-user/aarch64/target_proc.h | 2 +- linux-user/arm/target_proc.h | 102 +++++++++++++++++++++++- linux-user/loader.h | 6 +- linux-user/elfload.c | 130 ++++++++++++++++++++++++++++++- 4 files changed, 233 insertions(+), 7 deletions(-) diff --git a/linux-user/aarch64/target_proc.h b/linux-user/aarch64/target_p= roc.h index 43fe29ca72..907df4dcd2 100644 --- a/linux-user/aarch64/target_proc.h +++ b/linux-user/aarch64/target_proc.h @@ -1 +1 @@ -/* No target-specific /proc support */ +#include "../arm/target_proc.h" diff --git a/linux-user/arm/target_proc.h b/linux-user/arm/target_proc.h index 43fe29ca72..ac75af9ca6 100644 --- a/linux-user/arm/target_proc.h +++ b/linux-user/arm/target_proc.h @@ -1 +1,101 @@ -/* No target-specific /proc support */ +/* + * Arm specific proc functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ARM_TARGET_PROC_H +#define ARM_TARGET_PROC_H + +static int open_cpuinfo(CPUArchState *cpu_env, int fd) +{ + ARMCPU *cpu =3D env_archcpu(cpu_env); + int arch, midr_rev, midr_part, midr_var, midr_impl; + target_ulong elf_hwcap =3D get_elf_hwcap(); + target_ulong elf_hwcap2 =3D get_elf_hwcap2(); + const char *elf_name; + int num_cpus, len_part, len_var; + +#if TARGET_BIG_ENDIAN +# define END_SUFFIX "b" +#else +# define END_SUFFIX "l" +#endif + + arch =3D 8; + elf_name =3D "v8" END_SUFFIX; + midr_rev =3D FIELD_EX32(cpu->midr, MIDR_EL1, REVISION); + midr_part =3D FIELD_EX32(cpu->midr, MIDR_EL1, PARTNUM); + midr_var =3D FIELD_EX32(cpu->midr, MIDR_EL1, VARIANT); + midr_impl =3D FIELD_EX32(cpu->midr, MIDR_EL1, IMPLEMENTER); + len_part =3D 3; + len_var =3D 1; + +#ifndef TARGET_AARCH64 + /* For simplicity, treat ARMv8 as an arm64 kernel with CONFIG_COMPAT. = */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { + if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { + arch =3D 7; + midr_var =3D (cpu->midr >> 16) & 0x7f; + len_var =3D 2; + if (arm_feature(&cpu->env, ARM_FEATURE_M)) { + elf_name =3D "armv7m" END_SUFFIX; + } else { + elf_name =3D "armv7" END_SUFFIX; + } + } else { + midr_part =3D cpu->midr >> 4; + len_part =3D 7; + if (arm_feature(&cpu->env, ARM_FEATURE_V6)) { + arch =3D 6; + elf_name =3D "armv6" END_SUFFIX; + } else if (arm_feature(&cpu->env, ARM_FEATURE_V5)) { + arch =3D 5; + elf_name =3D "armv5t" END_SUFFIX; + } else { + arch =3D 4; + elf_name =3D "armv4" END_SUFFIX; + } + } + } +#endif + +#undef END_SUFFIX + + num_cpus =3D sysconf(_SC_NPROCESSORS_ONLN); + for (int i =3D 0; i < num_cpus; i++) { + dprintf(fd, + "processor\t: %d\n" + "model name\t: ARMv%d Processor rev %d (%s)\n" + "BogoMIPS\t: 100.00\n" + "Features\t:", + i, arch, midr_rev, elf_name); + + for (target_ulong j =3D elf_hwcap; j ; j &=3D j - 1) { + dprintf(fd, " %s", elf_hwcap_str(ctz64(j))); + } + for (target_ulong j =3D elf_hwcap2; j ; j &=3D j - 1) { + dprintf(fd, " %s", elf_hwcap2_str(ctz64(j))); + } + + dprintf(fd, "\n" + "CPU implementer\t: 0x%02x\n" + "CPU architecture: %d\n" + "CPU variant\t: 0x%0*x\n", + midr_impl, arch, len_var, midr_var); + if (arch >=3D 7) { + dprintf(fd, "CPU part\t: 0x%0*x\n", len_part, midr_part); + } + dprintf(fd, "CPU revision\t: %d\n\n", midr_rev); + } + + if (arch < 8) { + dprintf(fd, "Hardware\t: QEMU v%s %s\n", QEMU_VERSION, + cpu->dtb_compatible ? : ""); + dprintf(fd, "Revision\t: 0000\n"); + dprintf(fd, "Serial\t\t: 0000000000000000\n"); + } + return 0; +} +#define HAVE_ARCH_PROC_CPUINFO + +#endif /* ARM_TARGET_PROC_H */ diff --git a/linux-user/loader.h b/linux-user/loader.h index 59cbeacf24..324e5c872a 100644 --- a/linux-user/loader.h +++ b/linux-user/loader.h @@ -56,9 +56,13 @@ abi_long memcpy_to_target(abi_ulong dest, const void *sr= c, =20 extern unsigned long guest_stack_size; =20 -#ifdef TARGET_S390X +#if defined(TARGET_S390X) || defined(TARGET_AARCH64) || defined(TARGET_ARM) uint32_t get_elf_hwcap(void); const char *elf_hwcap_str(uint32_t bit); #endif +#if defined(TARGET_AARCH64) || defined(TARGET_ARM) +uint32_t get_elf_hwcap2(void); +const char *elf_hwcap2_str(uint32_t bit); +#endif =20 #endif /* LINUX_USER_LOADER_H */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 92b981c445..7c95098e3e 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -466,7 +466,7 @@ static bool init_guest_commpage(void) #define ELF_HWCAP get_elf_hwcap() #define ELF_HWCAP2 get_elf_hwcap2() =20 -static uint32_t get_elf_hwcap(void) +uint32_t get_elf_hwcap(void) { ARMCPU *cpu =3D ARM_CPU(thread_cpu); uint32_t hwcaps =3D 0; @@ -508,7 +508,7 @@ static uint32_t get_elf_hwcap(void) return hwcaps; } =20 -static uint32_t get_elf_hwcap2(void) +uint32_t get_elf_hwcap2(void) { ARMCPU *cpu =3D ARM_CPU(thread_cpu); uint32_t hwcaps =3D 0; @@ -521,6 +521,49 @@ static uint32_t get_elf_hwcap2(void) return hwcaps; } =20 +const char *elf_hwcap_str(uint32_t bit) +{ + static const char *hwcap_str[] =3D { + [__builtin_ctz(ARM_HWCAP_ARM_SWP )] =3D "swp", + [__builtin_ctz(ARM_HWCAP_ARM_HALF )] =3D "half", + [__builtin_ctz(ARM_HWCAP_ARM_THUMB )] =3D "thumb", + [__builtin_ctz(ARM_HWCAP_ARM_26BIT )] =3D "26bit", + [__builtin_ctz(ARM_HWCAP_ARM_FAST_MULT)] =3D "fast_mult", + [__builtin_ctz(ARM_HWCAP_ARM_FPA )] =3D "fpa", + [__builtin_ctz(ARM_HWCAP_ARM_VFP )] =3D "vfp", + [__builtin_ctz(ARM_HWCAP_ARM_EDSP )] =3D "edsp", + [__builtin_ctz(ARM_HWCAP_ARM_JAVA )] =3D "java", + [__builtin_ctz(ARM_HWCAP_ARM_IWMMXT )] =3D "iwmmxt", + [__builtin_ctz(ARM_HWCAP_ARM_CRUNCH )] =3D "crunch", + [__builtin_ctz(ARM_HWCAP_ARM_THUMBEE )] =3D "thumbee", + [__builtin_ctz(ARM_HWCAP_ARM_NEON )] =3D "neon", + [__builtin_ctz(ARM_HWCAP_ARM_VFPv3 )] =3D "vfpv3", + [__builtin_ctz(ARM_HWCAP_ARM_VFPv3D16 )] =3D "vfpv3d16", + [__builtin_ctz(ARM_HWCAP_ARM_TLS )] =3D "tls", + [__builtin_ctz(ARM_HWCAP_ARM_VFPv4 )] =3D "vfpv4", + [__builtin_ctz(ARM_HWCAP_ARM_IDIVA )] =3D "idiva", + [__builtin_ctz(ARM_HWCAP_ARM_IDIVT )] =3D "idivt", + [__builtin_ctz(ARM_HWCAP_ARM_VFPD32 )] =3D "vfpd32", + [__builtin_ctz(ARM_HWCAP_ARM_LPAE )] =3D "lpae", + [__builtin_ctz(ARM_HWCAP_ARM_EVTSTRM )] =3D "evtstrm", + }; + + return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; +} + +const char *elf_hwcap2_str(uint32_t bit) +{ + static const char *hwcap_str[] =3D { + [__builtin_ctz(ARM_HWCAP2_ARM_AES )] =3D "aes", + [__builtin_ctz(ARM_HWCAP2_ARM_PMULL)] =3D "pmull", + [__builtin_ctz(ARM_HWCAP2_ARM_SHA1 )] =3D "sha1", + [__builtin_ctz(ARM_HWCAP2_ARM_SHA2 )] =3D "sha2", + [__builtin_ctz(ARM_HWCAP2_ARM_CRC32)] =3D "crc32", + }; + + return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; +} + #undef GET_FEATURE #undef GET_FEATURE_ID =20 @@ -668,7 +711,7 @@ enum { #define GET_FEATURE_ID(feat, hwcap) \ do { if (cpu_isar_feature(feat, cpu)) { hwcaps |=3D hwcap; } } while (= 0) =20 -static uint32_t get_elf_hwcap(void) +uint32_t get_elf_hwcap(void) { ARMCPU *cpu =3D ARM_CPU(thread_cpu); uint32_t hwcaps =3D 0; @@ -706,7 +749,7 @@ static uint32_t get_elf_hwcap(void) return hwcaps; } =20 -static uint32_t get_elf_hwcap2(void) +uint32_t get_elf_hwcap2(void) { ARMCPU *cpu =3D ARM_CPU(thread_cpu); uint32_t hwcaps =3D 0; @@ -741,6 +784,85 @@ static uint32_t get_elf_hwcap2(void) return hwcaps; } =20 +const char *elf_hwcap_str(uint32_t bit) +{ + static const char *hwcap_str[] =3D { + [__builtin_ctz(ARM_HWCAP_A64_FP )] =3D "fp", + [__builtin_ctz(ARM_HWCAP_A64_ASIMD )] =3D "asimd", + [__builtin_ctz(ARM_HWCAP_A64_EVTSTRM )] =3D "evtstrm", + [__builtin_ctz(ARM_HWCAP_A64_AES )] =3D "aes", + [__builtin_ctz(ARM_HWCAP_A64_PMULL )] =3D "pmull", + [__builtin_ctz(ARM_HWCAP_A64_SHA1 )] =3D "sha1", + [__builtin_ctz(ARM_HWCAP_A64_SHA2 )] =3D "sha2", + [__builtin_ctz(ARM_HWCAP_A64_CRC32 )] =3D "crc32", + [__builtin_ctz(ARM_HWCAP_A64_ATOMICS )] =3D "atomics", + [__builtin_ctz(ARM_HWCAP_A64_FPHP )] =3D "fphp", + [__builtin_ctz(ARM_HWCAP_A64_ASIMDHP )] =3D "asimdhp", + [__builtin_ctz(ARM_HWCAP_A64_CPUID )] =3D "cpuid", + [__builtin_ctz(ARM_HWCAP_A64_ASIMDRDM)] =3D "asimdrdm", + [__builtin_ctz(ARM_HWCAP_A64_JSCVT )] =3D "jscvt", + [__builtin_ctz(ARM_HWCAP_A64_FCMA )] =3D "fcma", + [__builtin_ctz(ARM_HWCAP_A64_LRCPC )] =3D "lrcpc", + [__builtin_ctz(ARM_HWCAP_A64_DCPOP )] =3D "dcpop", + [__builtin_ctz(ARM_HWCAP_A64_SHA3 )] =3D "sha3", + [__builtin_ctz(ARM_HWCAP_A64_SM3 )] =3D "sm3", + [__builtin_ctz(ARM_HWCAP_A64_SM4 )] =3D "sm4", + [__builtin_ctz(ARM_HWCAP_A64_ASIMDDP )] =3D "asimddp", + [__builtin_ctz(ARM_HWCAP_A64_SHA512 )] =3D "sha512", + [__builtin_ctz(ARM_HWCAP_A64_SVE )] =3D "sve", + [__builtin_ctz(ARM_HWCAP_A64_ASIMDFHM)] =3D "asimdfhm", + [__builtin_ctz(ARM_HWCAP_A64_DIT )] =3D "dit", + [__builtin_ctz(ARM_HWCAP_A64_USCAT )] =3D "uscat", + [__builtin_ctz(ARM_HWCAP_A64_ILRCPC )] =3D "ilrcpc", + [__builtin_ctz(ARM_HWCAP_A64_FLAGM )] =3D "flagm", + [__builtin_ctz(ARM_HWCAP_A64_SSBS )] =3D "ssbs", + [__builtin_ctz(ARM_HWCAP_A64_SB )] =3D "sb", + [__builtin_ctz(ARM_HWCAP_A64_PACA )] =3D "paca", + [__builtin_ctz(ARM_HWCAP_A64_PACG )] =3D "pacg", + }; + + return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; +} + +const char *elf_hwcap2_str(uint32_t bit) +{ + static const char *hwcap_str[] =3D { + [__builtin_ctz(ARM_HWCAP2_A64_DCPODP )] =3D "dcpodp", + [__builtin_ctz(ARM_HWCAP2_A64_SVE2 )] =3D "sve2", + [__builtin_ctz(ARM_HWCAP2_A64_SVEAES )] =3D "sveaes", + [__builtin_ctz(ARM_HWCAP2_A64_SVEPMULL )] =3D "svepmull", + [__builtin_ctz(ARM_HWCAP2_A64_SVEBITPERM )] =3D "svebitperm", + [__builtin_ctz(ARM_HWCAP2_A64_SVESHA3 )] =3D "svesha3", + [__builtin_ctz(ARM_HWCAP2_A64_SVESM4 )] =3D "svesm4", + [__builtin_ctz(ARM_HWCAP2_A64_FLAGM2 )] =3D "flagm2", + [__builtin_ctz(ARM_HWCAP2_A64_FRINT )] =3D "frint", + [__builtin_ctz(ARM_HWCAP2_A64_SVEI8MM )] =3D "svei8mm", + [__builtin_ctz(ARM_HWCAP2_A64_SVEF32MM )] =3D "svef32mm", + [__builtin_ctz(ARM_HWCAP2_A64_SVEF64MM )] =3D "svef64mm", + [__builtin_ctz(ARM_HWCAP2_A64_SVEBF16 )] =3D "svebf16", + [__builtin_ctz(ARM_HWCAP2_A64_I8MM )] =3D "i8mm", + [__builtin_ctz(ARM_HWCAP2_A64_BF16 )] =3D "bf16", + [__builtin_ctz(ARM_HWCAP2_A64_DGH )] =3D "dgh", + [__builtin_ctz(ARM_HWCAP2_A64_RNG )] =3D "rng", + [__builtin_ctz(ARM_HWCAP2_A64_BTI )] =3D "bti", + [__builtin_ctz(ARM_HWCAP2_A64_MTE )] =3D "mte", + [__builtin_ctz(ARM_HWCAP2_A64_ECV )] =3D "ecv", + [__builtin_ctz(ARM_HWCAP2_A64_AFP )] =3D "afp", + [__builtin_ctz(ARM_HWCAP2_A64_RPRES )] =3D "rpres", + [__builtin_ctz(ARM_HWCAP2_A64_MTE3 )] =3D "mte3", + [__builtin_ctz(ARM_HWCAP2_A64_SME )] =3D "sme", + [__builtin_ctz(ARM_HWCAP2_A64_SME_I16I64 )] =3D "sme_i16i64", + [__builtin_ctz(ARM_HWCAP2_A64_SME_F64F64 )] =3D "sme_f64f64", + [__builtin_ctz(ARM_HWCAP2_A64_SME_I8I32 )] =3D "sme_i8i32", + [__builtin_ctz(ARM_HWCAP2_A64_SME_F16F32 )] =3D "sme_f16f32", + [__builtin_ctz(ARM_HWCAP2_A64_SME_B16F32 )] =3D "sme_b16f32", + [__builtin_ctz(ARM_HWCAP2_A64_SME_F32F32 )] =3D "sme_f32f32", + [__builtin_ctz(ARM_HWCAP2_A64_SME_FA64 )] =3D "sme_fa64", + }; + + return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; +} + #undef GET_FEATURE_ID =20 #endif /* not TARGET_AARCH64 */ --=20 2.34.1