From nobody Mon Feb 9 10:27:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1693548012; cv=none; d=zohomail.com; s=zohoarc; b=ITFAuJtvtJkAxaz+o3o2OoZzQiWoLauxrQ/smZxi+TYMNF8RA+A0m9+C/Kb5vXvB+cASCm4Rl6MFACuhZnbewSIck6cP54DblyrleGl85KH/BO6V34o0CMr4/BuC3kllvggWu6PsTGenSRQkQyPQIxTlqF0hLH/UAkRNs68q9IQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693548012; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QB9AQtLpiUUzgbABNLrAi9ymsjmBfrJcr/BEGPoukrA=; b=QLFqkPEQLBEwg7frJPQk61placapg4z/gmJz4q4owHS10csb6qcRQcOAJK55Vsx40fp1hLJ2tEbUd4ybdt+KyM0H+dv8cqoeB17RvEHfvzztwnJC/udJue005mYlEKpJ9feiW8xI5T0hdwCZsQzXFaOIM8xPDwWr946IatWK0mI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693548012573107.03259748679352; Thu, 31 Aug 2023 23:00:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbxC1-0003k4-1V; Fri, 01 Sep 2023 01:59:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbxBy-0003ad-VQ for qemu-devel@nongnu.org; Fri, 01 Sep 2023 01:59:39 -0400 Received: from mgamail.intel.com ([192.55.52.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbxBw-0003XO-FM for qemu-devel@nongnu.org; Fri, 01 Sep 2023 01:59:38 -0400 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2023 22:59:25 -0700 Received: from unknown (HELO fred..) ([172.25.112.68]) by orsmga002.jf.intel.com with ESMTP; 31 Aug 2023 22:59:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693547976; x=1725083976; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dgdPhUMzK6D3ckRjnlBJala0jrjc4SAmU3BSPc0PwkE=; b=EEFsU98ilqzu7TOXUzXGVpf//y1nq7C9j1OZ96++voNaJ2+V35Pr+ok+ Gm3fA3qb8mZxJ/e8okgDK5bkHTmysviaPgdohP/0aYy7O627uaW1+t8uU 1CgahoubL4KCOGyjsTpv8MEvNhH0q95nbyybfuAh2Gr6J6OcE1UbSNmLH qsoLyg3gH1N1gFHhgYxVupooH2q4VHzlP0/HYZuXnRUf62Oszoe2VFRqE vFwuMmqkghzMFlgQEKutzJwxdFyRheZul7A2YPW/D8uItHMxcBI90XvCc Q1PCVKdpQzl0CHzwcbJSBvicw5wnp9ylFjNhIeovIX8vlJCxueEzn09HY w==; X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="356456623" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="356456623" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="739816157" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="739816157" From: Xin Li To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, pbonzini@redhat.com, seanjc@google.com, chao.gao@intel.com, hpa@zytor.com, xiaoyao.li@intel.com, weijiang.yang@intel.com Subject: [PATCH 1/4] target/i386: add support for FRED in CPUID enumeration Date: Thu, 31 Aug 2023 22:30:19 -0700 Message-Id: <20230901053022.18672-2-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230901053022.18672-1-xin3.li@intel.com> References: <20230901053022.18672-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.151; envelope-from=xin3.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1693548012935100001 Content-Type: text/plain; charset="utf-8" FRED, i.e., the Intel flexible return and event delivery architecture, defines simple new transitions that change privilege level (ring transitions). In addition to these transitions, the FRED architecture defines a new instruction (LKGS) for managing the state of the GS segment register. The LKGS instruction can be used by 64-bit operating systems that do not use the new FRED transitions. The CPUID feature flag CPUID.(EAX=3D7,ECX=3D1):EAX[17] enumerates FRED, and the CPUID feature flag CPUID.(EAX=3D7,ECX=3D1):EAX[18] enumerates LKGS. Add CPUID definitions for FRED/LKGS, and expose them to KVM guests only. Because FRED relies on LKGS, add it to feature dependency map. Tested-by: Shan Kang Signed-off-by: Xin Li --- target/i386/cpu.c | 6 +++++- target/i386/cpu.h | 4 ++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 00f913b638..3dba6b46d9 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -963,7 +963,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", NULL, NULL, "fzrm", "fsrs", "fsrc", NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, "fred", "lkgs", NULL, NULL, "amx-fp16", NULL, "avx-ifma", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, @@ -1549,6 +1549,10 @@ static FeatureDep feature_dependencies[] =3D { .from =3D { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_US= ER_WAIT_PAUSE }, .to =3D { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, }, + { + .from =3D { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, + .to =3D { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, + }, }; =20 typedef struct X86RegisterInfo32 { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index a6000e93bd..064decbc85 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -932,6 +932,10 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWor= d w, #define CPUID_7_1_EDX_AVX_NE_CONVERT (1U << 5) /* PREFETCHIT0/1 Instructions */ #define CPUID_7_1_EDX_PREFETCHITI (1U << 14) +/* Flexible return and event delivery (FRED) */ +#define CPUID_7_1_EAX_FRED (1U << 17) +/* Load into IA32_KERNEL_GS_BASE (LKGS) */ +#define CPUID_7_1_EAX_LKGS (1U << 18) =20 /* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */ #define CPUID_7_2_EDX_MCDT_NO (1U << 5) --=20 2.34.1