From nobody Thu May 16 11:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1693548012; cv=none; d=zohomail.com; s=zohoarc; b=ITFAuJtvtJkAxaz+o3o2OoZzQiWoLauxrQ/smZxi+TYMNF8RA+A0m9+C/Kb5vXvB+cASCm4Rl6MFACuhZnbewSIck6cP54DblyrleGl85KH/BO6V34o0CMr4/BuC3kllvggWu6PsTGenSRQkQyPQIxTlqF0hLH/UAkRNs68q9IQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693548012; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QB9AQtLpiUUzgbABNLrAi9ymsjmBfrJcr/BEGPoukrA=; b=QLFqkPEQLBEwg7frJPQk61placapg4z/gmJz4q4owHS10csb6qcRQcOAJK55Vsx40fp1hLJ2tEbUd4ybdt+KyM0H+dv8cqoeB17RvEHfvzztwnJC/udJue005mYlEKpJ9feiW8xI5T0hdwCZsQzXFaOIM8xPDwWr946IatWK0mI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693548012573107.03259748679352; Thu, 31 Aug 2023 23:00:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbxC1-0003k4-1V; Fri, 01 Sep 2023 01:59:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbxBy-0003ad-VQ for qemu-devel@nongnu.org; Fri, 01 Sep 2023 01:59:39 -0400 Received: from mgamail.intel.com ([192.55.52.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbxBw-0003XO-FM for qemu-devel@nongnu.org; Fri, 01 Sep 2023 01:59:38 -0400 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2023 22:59:25 -0700 Received: from unknown (HELO fred..) ([172.25.112.68]) by orsmga002.jf.intel.com with ESMTP; 31 Aug 2023 22:59:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693547976; x=1725083976; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dgdPhUMzK6D3ckRjnlBJala0jrjc4SAmU3BSPc0PwkE=; b=EEFsU98ilqzu7TOXUzXGVpf//y1nq7C9j1OZ96++voNaJ2+V35Pr+ok+ Gm3fA3qb8mZxJ/e8okgDK5bkHTmysviaPgdohP/0aYy7O627uaW1+t8uU 1CgahoubL4KCOGyjsTpv8MEvNhH0q95nbyybfuAh2Gr6J6OcE1UbSNmLH qsoLyg3gH1N1gFHhgYxVupooH2q4VHzlP0/HYZuXnRUf62Oszoe2VFRqE vFwuMmqkghzMFlgQEKutzJwxdFyRheZul7A2YPW/D8uItHMxcBI90XvCc Q1PCVKdpQzl0CHzwcbJSBvicw5wnp9ylFjNhIeovIX8vlJCxueEzn09HY w==; X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="356456623" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="356456623" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="739816157" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="739816157" From: Xin Li To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, pbonzini@redhat.com, seanjc@google.com, chao.gao@intel.com, hpa@zytor.com, xiaoyao.li@intel.com, weijiang.yang@intel.com Subject: [PATCH 1/4] target/i386: add support for FRED in CPUID enumeration Date: Thu, 31 Aug 2023 22:30:19 -0700 Message-Id: <20230901053022.18672-2-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230901053022.18672-1-xin3.li@intel.com> References: <20230901053022.18672-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.151; envelope-from=xin3.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1693548012935100001 Content-Type: text/plain; charset="utf-8" FRED, i.e., the Intel flexible return and event delivery architecture, defines simple new transitions that change privilege level (ring transitions). In addition to these transitions, the FRED architecture defines a new instruction (LKGS) for managing the state of the GS segment register. The LKGS instruction can be used by 64-bit operating systems that do not use the new FRED transitions. The CPUID feature flag CPUID.(EAX=3D7,ECX=3D1):EAX[17] enumerates FRED, and the CPUID feature flag CPUID.(EAX=3D7,ECX=3D1):EAX[18] enumerates LKGS. Add CPUID definitions for FRED/LKGS, and expose them to KVM guests only. Because FRED relies on LKGS, add it to feature dependency map. Tested-by: Shan Kang Signed-off-by: Xin Li --- target/i386/cpu.c | 6 +++++- target/i386/cpu.h | 4 ++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 00f913b638..3dba6b46d9 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -963,7 +963,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", NULL, NULL, "fzrm", "fsrs", "fsrc", NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, "fred", "lkgs", NULL, NULL, "amx-fp16", NULL, "avx-ifma", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, @@ -1549,6 +1549,10 @@ static FeatureDep feature_dependencies[] =3D { .from =3D { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_US= ER_WAIT_PAUSE }, .to =3D { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, }, + { + .from =3D { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, + .to =3D { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, + }, }; =20 typedef struct X86RegisterInfo32 { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index a6000e93bd..064decbc85 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -932,6 +932,10 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWor= d w, #define CPUID_7_1_EDX_AVX_NE_CONVERT (1U << 5) /* PREFETCHIT0/1 Instructions */ #define CPUID_7_1_EDX_PREFETCHITI (1U << 14) +/* Flexible return and event delivery (FRED) */ +#define CPUID_7_1_EAX_FRED (1U << 17) +/* Load into IA32_KERNEL_GS_BASE (LKGS) */ +#define CPUID_7_1_EAX_LKGS (1U << 18) =20 /* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */ #define CPUID_7_2_EDX_MCDT_NO (1U << 5) --=20 2.34.1 From nobody Thu May 16 11:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1693548004; cv=none; d=zohomail.com; s=zohoarc; b=dLQuQkqvNxahexfZfefJKUKc2bbIY4Me4EEg6vIWQ+LatDwCy1gpnfFrH0s4kMRA6LidFfvxRdXNKk/FW+NTrc8jx1TVSt5RKmOdZWCtZm1iTsJQQtSUcldxXlqPnhmf3Cgw2FW2PFl+FZt2UxNHBP0qeBcSZr3qddGHHiXDkmU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693548004; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FPcym41plNxmytHjyrK4Ml72noaR0Gjv4dldc1TRLzM=; b=ggO2P+19PnM8HZ2If6/JluHkfC0NxvzcOpG3OYCv9rFyMypwFgfEiPnTxetYWWgAuPHsO4OvVLTHDsYD+SMDllrkeegIGv2t2AaXdqXWzs6FB32XfSrM3YQnZYoFmmLGs17RofJW98fh4SA+YPVNwNVwSIB7ze2K+tDuwJ9mMgI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169354800403836.709007364666036; Thu, 31 Aug 2023 23:00:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbxBz-0003ae-8r; Fri, 01 Sep 2023 01:59:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbxBy-0003Vf-3d for qemu-devel@nongnu.org; Fri, 01 Sep 2023 01:59:38 -0400 Received: from mgamail.intel.com ([192.55.52.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbxBv-0003WI-Rk for qemu-devel@nongnu.org; Fri, 01 Sep 2023 01:59:37 -0400 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2023 22:59:26 -0700 Received: from unknown (HELO fred..) ([172.25.112.68]) by orsmga002.jf.intel.com with ESMTP; 31 Aug 2023 22:59:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693547975; x=1725083975; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cYxBFAMtro4zbkcrtr3LvUksDBEPZ7yuMe4iZR87FMY=; b=Y++vpIISuPzWOMUbciXFz66E1JqTqq8hAsycLp+3OT2lFKWkv89+TZ8V YBHBEDKk/iH0ZCVaPkWeInKaBlPbUmn7y4Nekd7qHUwgu+v7WyCHBpd5W uODSJKFPRZ2pwEZ/YRrLnyGe9LzBaYMJQUhV0hbdvJ8/BXAFnVR/1AhhQ MRJqPb7kS/pvW9isDVL4gfxaJUzgKAtiV1CrwSviIGoEMrBLW7mJEYtFA kit2lhiRoXwcPywctEnwNBktriKW4fUeZL7ZmiijBMjjyjQGWzt8N2pSK vBO/g+kWZb+GwShU8FR4KRjjuIE/6MZFiYvvXb55jkyy0HHE5sNj/zYkn A==; X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="356456632" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="356456632" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="739816164" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="739816164" From: Xin Li To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, pbonzini@redhat.com, seanjc@google.com, chao.gao@intel.com, hpa@zytor.com, xiaoyao.li@intel.com, weijiang.yang@intel.com Subject: [PATCH 2/4] target/i386: mark CR4.FRED not reserved Date: Thu, 31 Aug 2023 22:30:20 -0700 Message-Id: <20230901053022.18672-3-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230901053022.18672-1-xin3.li@intel.com> References: <20230901053022.18672-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.151; envelope-from=xin3.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1693548004982100001 Content-Type: text/plain; charset="utf-8" The CR4.FRED bit, i.e., CR4[32], is no longer a reserved bit when FRED is exposed to guests, otherwise it is still a reserved bit. Tested-by: Shan Kang Signed-off-by: Xin Li --- target/i386/cpu.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 064decbc85..924819a64c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -262,6 +262,12 @@ typedef enum X86Seg { #define CR4_PKE_MASK (1U << 22) #define CR4_PKS_MASK (1U << 24) =20 +#ifdef TARGET_X86_64 +#define CR4_FRED_MASK (1ULL << 32) +#else +#define CR4_FRED_MASK 0 +#endif + #define CR4_RESERVED_MASK \ (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \ | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \ @@ -269,7 +275,8 @@ typedef enum X86Seg { | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \ | CR4_LA57_MASK \ | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \ - | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_M= ASK)) + | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_M= ASK \ + | CR4_FRED_MASK)) =20 #define DR6_BD (1 << 13) #define DR6_BS (1 << 14) @@ -2481,6 +2488,9 @@ static inline uint64_t cr4_reserved_bits(CPUX86State = *env) if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) { reserved_bits |=3D CR4_PKS_MASK; } + if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED)) { + reserved_bits |=3D CR4_FRED_MASK; + } return reserved_bits; } =20 --=20 2.34.1 From nobody Thu May 16 11:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1693548018; cv=none; d=zohomail.com; s=zohoarc; b=mjHxuuJPgirtJ/zGvhnS09NCP5MwlJQFJIYvZXzE5a+NU9P4YazsqaYVr/MSuCCtce8Qs0rCNbjQrZBZK7vcJPjT/IUnPDr+N9YCsnr5rsaAOI3XaGML7SZYb6UKjCOYbcHFDKUL3og50DPiVgS5kD77wQUXzXdQO90eJ/DZ9iU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693548018; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VDjwMLC8wwy6aWf9NNreUs75dG1XSjSwdGvvtNFeffw=; b=Tl5oMK0CW8UVEvT2u+9VoX6O34qxVXkWeG2pqx1efgpNP2vxsRw64WqXZw3M0bVMD/1u0azThI4Zo4ZCPX3WUEb/8k06Y0oG9usok5GOnEfGc3gqbrgwp7+qkHLLeM8vEDMnu+fTVnIxytUzh7lfKsSvn39v7WlL/dwtdgs9nN4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693548018287907.9197346398902; Thu, 31 Aug 2023 23:00:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbxC2-0003sO-Qq; Fri, 01 Sep 2023 01:59:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbxC0-0003hX-Lh for qemu-devel@nongnu.org; Fri, 01 Sep 2023 01:59:40 -0400 Received: from mgamail.intel.com ([192.55.52.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbxBy-0003WI-GF for qemu-devel@nongnu.org; Fri, 01 Sep 2023 01:59:40 -0400 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2023 22:59:26 -0700 Received: from unknown (HELO fred..) ([172.25.112.68]) by orsmga002.jf.intel.com with ESMTP; 31 Aug 2023 22:59:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693547978; x=1725083978; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kBJjgJUqdsnUFUfQUjqAeWVl/5i30fjbjZiEHQKmmFc=; b=DLvLu23viOTOmOMiYhLqnKZlp7ul0PMBXVpdpID65Eins3UeElAljriY pCq51U1lGYW2y1YU4fQdAy+OwKD9LCNum+BL3yLZTwljOoRb8rnXSaf93 nPAOsmwdw8Vrva/upQ4xWpYDbtZiuJPdUX7biAtbz+WyxOzubLkkXkI7a 9k3hbYTnHrNJglyGrjLgZ1PmVANNYCvdtHO2CedoqsVRAi7xW+XoIjiy0 Fu/QAKwIPwJcQmJ/VVnE61Tz+UBsJKXC5cZW4d/bYgLqmWyOm6g1rZL5J 6QJXJt595fxcksGq6ZePVZqMv+NAOchw0bkwb7amEVQ6j/fu8pMK0x8Sh A==; X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="356456638" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="356456638" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="739816168" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="739816168" From: Xin Li To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, pbonzini@redhat.com, seanjc@google.com, chao.gao@intel.com, hpa@zytor.com, xiaoyao.li@intel.com, weijiang.yang@intel.com Subject: [PATCH 3/4] target/i386: enumerate VMX nested-exception support Date: Thu, 31 Aug 2023 22:30:21 -0700 Message-Id: <20230901053022.18672-4-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230901053022.18672-1-xin3.li@intel.com> References: <20230901053022.18672-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.151; envelope-from=xin3.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1693548019084100001 Content-Type: text/plain; charset="utf-8" Allow VMX nested-exception support to be exposed in KVM guests, thus nested KVM guests can enumerate it. Tested-by: Shan Kang Signed-off-by: Xin Li --- target/i386/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3dba6b46d9..ba579e1fb7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1340,6 +1340,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { .feat_names =3D { [54] =3D "vmx-ins-outs", [55] =3D "vmx-true-ctls", + [58] =3D "vmx-nested-exception", }, .msr =3D { .index =3D MSR_IA32_VMX_BASIC, --=20 2.34.1 From nobody Thu May 16 11:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1693548055; cv=none; d=zohomail.com; s=zohoarc; b=GpKhX8eNo0KGEQ98RqSd8RevJ3F8ijPaHZBGX9d41OfnQ2ut3Eip6/JG3dVBWsL4tPYKz+p7p+qdsJ+GHrfUUNWs7koczzhn4MVDVhv4o8DCJmrnnfDaHEF6dIcqDuld4rS42hSjSVFg/UJd1Nov2ShHZjjFXPXvxRYi8df9jBk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693548055; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VTq5tSdlNqXhrwMfFqonuiPCbCVlsj8lPzsKOUo4To8=; b=AT3luOszfw3BNKIJScZPTbUwMpVnmSvPcPpzN33SmGP10Zt33g6YXvSFdD474OsFJPQanGHSRanSiDH/xcxpTWnFpyJmkwTVrdcXz90prYHF7SDzU4tECY3IA2JNwD+D4a31t7YssJ03uj7iO6AoS54tGJAtoeQ72BH/bQh8u2c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693548055175216.29899994450795; Thu, 31 Aug 2023 23:00:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbxC3-0003ul-A3; Fri, 01 Sep 2023 01:59:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbxC1-0003mf-KT for qemu-devel@nongnu.org; Fri, 01 Sep 2023 01:59:41 -0400 Received: from mgamail.intel.com ([192.55.52.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbxBz-0003Xk-1D for qemu-devel@nongnu.org; Fri, 01 Sep 2023 01:59:41 -0400 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2023 22:59:26 -0700 Received: from unknown (HELO fred..) ([172.25.112.68]) by orsmga002.jf.intel.com with ESMTP; 31 Aug 2023 22:59:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693547978; x=1725083978; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=P4dZkvuV0tYhJwKydOtUzePt0LTMzJINaIN3aOdzRXI=; b=WP31XDNZpQwCw6UfYRfRFVCOA2YgnBShhxLtwYeSC8rcAOD0M1TkLniq p2d4KIh/avOvmponDJPd0zupQvCsHT8Q55A9YriUNl8NqsqTGVDZUfmYu PKLvNRZ4350Qf0gtF2ns19Er1g4yDkZR7dYyKcktay4a180IPXYi8tsnw YcLqDkAszLFGNBWXc8Ym9g2bbOjuolutTQsEv04lLuY+7sH5AghCMGQE2 1uMOrk3uqz4e7nvTq5o9W2ybgXbeGZ/gmtLDlhKiewV8zEFef7i0/S5hL gLK0lG6kSrTHz1FltKpKFyBNVPV0X8anJtkwe5AnL7czgrVg2M6t3spZN w==; X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="356456646" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="356456646" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="739816171" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="739816171" From: Xin Li To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, pbonzini@redhat.com, seanjc@google.com, chao.gao@intel.com, hpa@zytor.com, xiaoyao.li@intel.com, weijiang.yang@intel.com Subject: [PATCH 4/4] target/i386: add live migration support for FRED Date: Thu, 31 Aug 2023 22:30:22 -0700 Message-Id: <20230901053022.18672-5-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230901053022.18672-1-xin3.li@intel.com> References: <20230901053022.18672-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.151; envelope-from=xin3.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1693548055818100001 Content-Type: text/plain; charset="utf-8" FRED CPU states are managed in 10 FRED MSRs, in addtion to a few existing CPU registers and MSRs, e.g., the CR4.FRED bit. Add the 10 new FRED MSRs to x86 CPUArchState for live migration support. Tested-by: Shan Kang Signed-off-by: Xin Li --- target/i386/cpu.h | 24 +++++++++++++++++++ target/i386/kvm/kvm.c | 54 +++++++++++++++++++++++++++++++++++++++++++ target/i386/machine.c | 10 ++++++++ 3 files changed, 88 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 924819a64c..a36a1a58c4 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -529,6 +529,20 @@ typedef enum X86Seg { #define MSR_IA32_XFD 0x000001c4 #define MSR_IA32_XFD_ERR 0x000001c5 =20 +#define MSR_IA32_PL0_SSP 0x000006a4 /* Stack level 0 = shadow stack pointer in ring 0 */ + +/* FRED MSRs */ +#define MSR_IA32_FRED_RSP0 0x000001cc /* Stack level 0 = regular stack pointer */ +#define MSR_IA32_FRED_RSP1 0x000001cd /* Stack level 1 = regular stack pointer */ +#define MSR_IA32_FRED_RSP2 0x000001ce /* Stack level 2 = regular stack pointer */ +#define MSR_IA32_FRED_RSP3 0x000001cf /* Stack level 3 = regular stack pointer */ +#define MSR_IA32_FRED_STKLVLS 0x000001d0 /* FRED exception= stack levels */ +#define MSR_IA32_FRED_SSP0 MSR_IA32_PL0_SSP /* Stack level 0 = shadow stack pointer in ring 0 */ +#define MSR_IA32_FRED_SSP1 0x000001d1 /* Stack level 1 = shadow stack pointer in ring 0 */ +#define MSR_IA32_FRED_SSP2 0x000001d2 /* Stack level 2 = shadow stack pointer in ring 0 */ +#define MSR_IA32_FRED_SSP3 0x000001d3 /* Stack level 3 = shadow stack pointer in ring 0 */ +#define MSR_IA32_FRED_CONFIG 0x000001d4 /* FRED Entrypoin= t and interrupt stack level */ + #define MSR_IA32_BNDCFGS 0x00000d90 #define MSR_IA32_XSS 0x00000da0 #define MSR_IA32_UMWAIT_CONTROL 0xe1 @@ -1680,6 +1694,16 @@ typedef struct CPUArchState { target_ulong cstar; target_ulong fmask; target_ulong kernelgsbase; + target_ulong fred_rsp0; + target_ulong fred_rsp1; + target_ulong fred_rsp2; + target_ulong fred_rsp3; + target_ulong fred_stklvls; + target_ulong fred_ssp0; + target_ulong fred_ssp1; + target_ulong fred_ssp2; + target_ulong fred_ssp3; + target_ulong fred_config; #endif =20 uint64_t tsc_adjust; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 639a242ad8..4b241c82d8 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -3401,6 +3401,18 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase); kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask); kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar); + if (env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) { + kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP0, env->fred_rsp0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP1, env->fred_rsp1); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP2, env->fred_rsp2); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP3, env->fred_rsp3); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_STKLVLS, env->fred_stklvl= s); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP0, env->fred_ssp0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP1, env->fred_ssp1); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP2, env->fred_ssp2); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP3, env->fred_ssp3); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_CONFIG, env->fred_config); + } } #endif =20 @@ -3901,6 +3913,18 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0); kvm_msr_entry_add(cpu, MSR_FMASK, 0); kvm_msr_entry_add(cpu, MSR_LSTAR, 0); + if (env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) { + kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP0, 0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP1, 0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP2, 0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP3, 0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_STKLVLS, 0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP0, 0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP1, 0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP2, 0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP3, 0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_CONFIG, 0); + } } #endif kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0); @@ -4123,6 +4147,36 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_LSTAR: env->lstar =3D msrs[i].data; break; + case MSR_IA32_FRED_RSP0: + env->fred_rsp0 =3D msrs[i].data; + break; + case MSR_IA32_FRED_RSP1: + env->fred_rsp1 =3D msrs[i].data; + break; + case MSR_IA32_FRED_RSP2: + env->fred_rsp2 =3D msrs[i].data; + break; + case MSR_IA32_FRED_RSP3: + env->fred_rsp3 =3D msrs[i].data; + break; + case MSR_IA32_FRED_STKLVLS: + env->fred_stklvls =3D msrs[i].data; + break; + case MSR_IA32_FRED_SSP0: + env->fred_ssp0 =3D msrs[i].data; + break; + case MSR_IA32_FRED_SSP1: + env->fred_ssp1 =3D msrs[i].data; + break; + case MSR_IA32_FRED_SSP2: + env->fred_ssp2 =3D msrs[i].data; + break; + case MSR_IA32_FRED_SSP3: + env->fred_ssp3 =3D msrs[i].data; + break; + case MSR_IA32_FRED_CONFIG: + env->fred_config =3D msrs[i].data; + break; #endif case MSR_IA32_TSC: env->tsc =3D msrs[i].data; diff --git a/target/i386/machine.c b/target/i386/machine.c index c7ac8084b2..5c722a49c5 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1652,6 +1652,16 @@ const VMStateDescription vmstate_x86_cpu =3D { VMSTATE_UINT64(env.cstar, X86CPU), VMSTATE_UINT64(env.fmask, X86CPU), VMSTATE_UINT64(env.kernelgsbase, X86CPU), + VMSTATE_UINT64(env.fred_rsp0, X86CPU), + VMSTATE_UINT64(env.fred_rsp1, X86CPU), + VMSTATE_UINT64(env.fred_rsp2, X86CPU), + VMSTATE_UINT64(env.fred_rsp3, X86CPU), + VMSTATE_UINT64(env.fred_stklvls, X86CPU), + VMSTATE_UINT64(env.fred_ssp0, X86CPU), + VMSTATE_UINT64(env.fred_ssp1, X86CPU), + VMSTATE_UINT64(env.fred_ssp2, X86CPU), + VMSTATE_UINT64(env.fred_ssp3, X86CPU), + VMSTATE_UINT64(env.fred_config, X86CPU), #endif VMSTATE_UINT32(env.smbase, X86CPU), =20 --=20 2.34.1