From nobody Wed May 15 23:43:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693524339; cv=none; d=zohomail.com; s=zohoarc; b=m/mM+dFjytO1vfG3Bt2qlPjNBNljigG0nRAkX7BjS/Th1h/Ou9UDmnzUQIYGIKBsb12dTMOPIqTdfim/x8X0QctQSD29jizu9P50rxSnxaiOgc9IYEdkXAnKKQN55jqd4YfpM6Ll2X/3Sr3nH4e5VGp/NmMqO+WN28U25GKbVdQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693524339; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xJhlXQXtvoaQKGLnjSOd47nDGtHCxt4SmP6oJ81pLWo=; b=JegKyqSZ4HRwAIbzMGz3XSzCDdDEhoWI2P23KWpu9JY5MY0tP/5c23/oQBZ2ZDEaSf4ogFX3i6tpyk89514X2zAtpt6g4YVv6oXpLEMy9Afce1HVAqri9scut660Uky3qQ9tXWwghKlPonOnUNA5jhqq6Dold88ucL71U3WzUIA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16935243397543.6046665994629166; Thu, 31 Aug 2023 16:25:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbr1z-0006nR-Jo; Thu, 31 Aug 2023 19:24:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbr1x-0006mR-LF for qemu-devel@nongnu.org; Thu, 31 Aug 2023 19:24:53 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbr1p-0002HA-Op for qemu-devel@nongnu.org; Thu, 31 Aug 2023 19:24:53 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1c1e3a4a06fso10124895ad.3 for ; Thu, 31 Aug 2023 16:24:44 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id jd5-20020a170903260500b001bb8895848bsm1732711plb.71.2023.08.31.16.24.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 16:24:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693524283; x=1694129083; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xJhlXQXtvoaQKGLnjSOd47nDGtHCxt4SmP6oJ81pLWo=; b=KGgYw5rASumvONBf6UcLSkentlF6tNkXxP+CBv0GtQUmbNzyDQkGZIbS3pbFRaOzj+ TeGgNyyShGaD71pScgey2Ppbm+MJTpJxEsFkPpV9e0BwQ4zLqY2VzJ5XMbG7IqNPUPW3 VedrXZqPsSUCqxg9iO0TnitFDEzfWGdIbQ8JHe6JYMTNqGBxY8Z7TTlcjcWEQxkpAQNW SkpjMPs90TJUQnTWrOX/lbyfS1mSskIk823xXjJR0xLPWa/broifu2taKR8IHfHqnDUd ePA4ZlYGU1nyvAZ+mfHQXmFhCWMThWZAKdRtB2pMsne/tHRl+Hr4RyCItcrdzkdZPqw6 vcSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693524283; x=1694129083; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xJhlXQXtvoaQKGLnjSOd47nDGtHCxt4SmP6oJ81pLWo=; b=CZAjQ7xPPp74zn1QukVKpzgWvT6vlQL8GVVAl6b7xcEax10SQ5nXszN09Yf7/wALA4 jSsMx4OwAigc5CEbupEqo1Ii+QP4HU6TZKKyZrHF0ZVmZwZH13P/017CdnEA/cxYhjzz 7xWsf9WbIAxO1yXiCUXx5HX8f3luXyVImeEJWTsZC2Yv8huOMRX3wohkPcFCx9UGCT0s hNiGn0pPgp6hwoIl2Hcv7OzOeRtsJOpxu9NOfGafMSpBUDbYFA0iP65XJ3J5WGfpu8/Q 7UvXsMI36b6ujodsTQk0+bQ2JLHpV7H/AIw4EqHp3pxUEd/kCmFJrNKhfcy2y9uLqwm+ SRgw== X-Gm-Message-State: AOJu0Yyu5fbnPWirnfNI0NLiuuOlTEbfI3M7+2ptkzc+TL3c1zcIc3bg DipUuuP7AtZcrJpUzvW3ja2VYMe4VyvkRXuiVlo= X-Google-Smtp-Source: AGHT+IGdOpS2d4+8WG10sCaTNOyd6d8nmvsaZqNUi8JDeyNyX8jLbBOkBrArtGuY5pVcG06ljpGBRQ== X-Received: by 2002:a17:902:efc6:b0:1c1:e7b2:27af with SMTP id ja6-20020a170902efc600b001c1e7b227afmr936043plb.57.1693524283242; Thu, 31 Aug 2023 16:24:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 1/5] target/arm: Implement RMR_ELx Date: Thu, 31 Aug 2023 16:24:37 -0700 Message-Id: <20230831232441.66020-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831232441.66020-1-richard.henderson@linaro.org> References: <20230831232441.66020-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693524340419100001 Content-Type: text/plain; charset="utf-8" Provide a stub implementation, as a write is a "request". Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 64 +++++++++++++++++++++++++++++---------------- 1 file changed, 41 insertions(+), 23 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e3f5a7d2bd..654e7d06a8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8682,16 +8682,25 @@ void register_cp_regs_for_features(ARMCPU *cpu) }; modify_arm_cp_regs(v8_idregs, v8_user_idregs); #endif - /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ + /* + * RVBAR_EL1 and RMR_EL1 only implemented if EL1 is the highest EL. + * TODO: For RMR, a write with bit 1 set should do something with + * cpu_reset(). In the meantime, "the bit is strictly a request", + * so we are in spec just ignoring writes. + */ if (!arm_feature(env, ARM_FEATURE_EL3) && !arm_feature(env, ARM_FEATURE_EL2)) { - ARMCPRegInfo rvbar =3D { - .name =3D "RVBAR_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc2 = =3D 1, - .access =3D PL1_R, - .fieldoffset =3D offsetof(CPUARMState, cp15.rvbar), + ARMCPRegInfo el1_reset_regs[] =3D { + { .name =3D "RVBAR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc2= =3D 1, + .access =3D PL1_R, + .fieldoffset =3D offsetof(CPUARMState, cp15.rvbar) }, + { .name =3D "RMR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc2= =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D arm_feature(env, ARM_FEATURE_AARCH64) } }; - define_one_arm_cp_reg(cpu, &rvbar); + define_arm_cp_regs(cpu, el1_reset_regs); } define_arm_cp_regs(cpu, v8_idregs); define_arm_cp_regs(cpu, v8_cp_reginfo); @@ -8775,22 +8784,25 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_sel2, cpu)) { define_arm_cp_regs(cpu, el2_sec_cp_reginfo); } - /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ + /* + * RVBAR_EL2 and RMR_EL2 only implemented if EL2 is the highest EL. + * See commentary near RMR_EL1. + */ if (!arm_feature(env, ARM_FEATURE_EL3)) { - ARMCPRegInfo rvbar[] =3D { - { - .name =3D "RVBAR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .op= c2 =3D 1, - .access =3D PL2_R, - .fieldoffset =3D offsetof(CPUARMState, cp15.rvbar), - }, - { .name =3D "RVBAR", .type =3D ARM_CP_ALIAS, - .cp =3D 15, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc= 2 =3D 1, - .access =3D PL2_R, - .fieldoffset =3D offsetof(CPUARMState, cp15.rvbar), - }, + static const ARMCPRegInfo el2_reset_regs[] =3D { + { .name =3D "RVBAR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2= =3D 1, + .access =3D PL2_R, + .fieldoffset =3D offsetof(CPUARMState, cp15.rvbar) }, + { .name =3D "RVBAR", .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc2 = =3D 1, + .access =3D PL2_R, + .fieldoffset =3D offsetof(CPUARMState, cp15.rvbar) }, + { .name =3D "RMR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2= =3D 2, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue = =3D 1 }, }; - define_arm_cp_regs(cpu, rvbar); + define_arm_cp_regs(cpu, el2_reset_regs); } } =20 @@ -8801,8 +8813,14 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "RVBAR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 12, .crm =3D 0, .opc2 =3D= 1, .access =3D PL3_R, - .fieldoffset =3D offsetof(CPUARMState, cp15.rvbar), - }, + .fieldoffset =3D offsetof(CPUARMState, cp15.rvbar), }, + { .name =3D "RMR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 12, .crm =3D 0, .opc2 =3D= 2, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D = 1 }, + { .name =3D "RMR", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc2 =3D = 2, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D arm_feature(env, ARM_FEATURE_AARCH64) }, { .name =3D "SCTLR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 0, .opc2 =3D = 0, .access =3D PL3_RW, --=20 2.34.1 From nobody Wed May 15 23:43:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id jd5-20020a170903260500b001bb8895848bsm1732711plb.71.2023.08.31.16.24.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 16:24:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693524284; x=1694129084; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fKdHQlw/TcgzSbe1vD4Z7Y3NFBfF1rOhXjA2KTi3TfI=; b=QRN6LwKa/XQRaOUZuZF5BP/hwEnKI77VVaLV8q8EP8tknm+133PZR7uZ2L8ESc7Frl 2c4rWYig2nUjtkbhTjON7UyFP3m5km0RsdmBjo7lU7KSJPXbc6Bomp1WJBnomkhZLdnI wYWcOYdjSrbQec8KzJT8sA/6BFVkVMYNko7+vvK2fiePYcKP6gDTliyBqqXo3WCkKOtm D3wXlyAU6ZMFG34qSsPAld8IYY3jRd6SHxLOa6K1NZT29x9bJ+O/jlxmJtWgWHg4UnAB sG7gJ0zK88ePrivY3clwfK27pX7EHQPQFXoEXpDUV6dO+9r3vuF8J/rPGyfBOeiW7zG3 2cuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693524284; x=1694129084; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fKdHQlw/TcgzSbe1vD4Z7Y3NFBfF1rOhXjA2KTi3TfI=; b=TwuZPmq8qObwa/SxGxdsDTea+eZOSdED2KQT6+euDZXxtF/D478IHoqsUorK161ZLH 7l1LlerOuIr949fTen7U7KSFtRNKHeW9epYDPVFl2f0pmBfw81D8eZMJanlLw/8Sa9/0 ONFSD9htvVwp5rld/mkV1Mhf47e0imNM2tzBeUw9nMcDBiYNBaog5bwYC02oDA1ZJpIh x8XLrYvgoNkBLvuBWc3FqytL/HvH0d8/psRbK009Y2fvPsgngg1hKSf3GsleFylQiHaB hLKHNmjYj8GRXtf9ZH0ySr0wkwRHlLblLrfJ0+18mCJrIJl2NBwVwzx5vo7Qwi2kdA3p J3Lw== X-Gm-Message-State: AOJu0Yw8oA6n8twp8ZNuRp24VPM/bMQvZOCMvXMvDPgWyK5jaelylYVV MT/gdWah+QYOI56xZPwkTucwkzVOdq8Vw5iZi0Q= X-Google-Smtp-Source: AGHT+IH0s9PDLdz3TGNSOEqEnybwxOxDU7E7ydedPMkbuHJ1fS94W2PmQW2dH5tI1eG8/kXm0XGpsw== X-Received: by 2002:a17:902:d2cb:b0:1c2:193e:1106 with SMTP id n11-20020a170902d2cb00b001c2193e1106mr1354166plc.50.1693524284157; Thu, 31 Aug 2023 16:24:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 2/5] target/arm: Implement cortex-a710 Date: Thu, 31 Aug 2023 16:24:38 -0700 Message-Id: <20230831232441.66020-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831232441.66020-1-richard.henderson@linaro.org> References: <20230831232441.66020-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693524392380100001 Content-Type: text/plain; charset="utf-8" The cortex-a710 is a first generation ARMv9.0-A processor. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- docs/system/arm/virt.rst | 1 + hw/arm/virt.c | 1 + target/arm/tcg/cpu64.c | 212 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 214 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 51cdac6841..e1697ac8f4 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -58,6 +58,7 @@ Supported guest CPU types: - ``cortex-a57`` (64-bit) - ``cortex-a72`` (64-bit) - ``cortex-a76`` (64-bit) +- ``cortex-a710`` (64-bit) - ``a64fx`` (64-bit) - ``host`` (with KVM only) - ``neoverse-n1`` (64-bit) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a13c658bbf..8ad78b23c2 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -211,6 +211,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a55"), ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a76"), + ARM_CPU_TYPE_NAME("cortex-a710"), ARM_CPU_TYPE_NAME("a64fx"), ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("neoverse-v1"), diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 0f8972950d..ab63526bea 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -745,6 +745,217 @@ static void aarch64_neoverse_v1_initfn(Object *obj) aarch64_add_sve_properties(obj); } =20 +static const ARMCPRegInfo cortex_a710_cp_reginfo[] =3D { + { .name =3D "CPUACTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .accessfn =3D access_actlr_w }, + { .name =3D "CPUACTLR2_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .accessfn =3D access_actlr_w }, + { .name =3D "CPUACTLR3_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .accessfn =3D access_actlr_w }, + { .name =3D "CPUACTLR4_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .accessfn =3D access_actlr_w }, + { .name =3D "CPUECTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 4, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .accessfn =3D access_actlr_w }, + { .name =3D "CPUECTLR2_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 5, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .accessfn =3D access_actlr_w }, + { .name =3D "CPUPPMCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 2, .opc2 =3D 4, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPWRCTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 2, .opc2 =3D 7, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .accessfn =3D access_actlr_w }, + { .name =3D "ATCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 7, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR5_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 8, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .accessfn =3D access_actlr_w }, + { .name =3D "CPUACTLR6_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 8, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .accessfn =3D access_actlr_w }, + { .name =3D "CPUACTLR7_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 8, .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .accessfn =3D access_actlr_w }, + { .name =3D "ATCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 15, .crm =3D 7, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "AVTCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 15, .crm =3D 7, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPPMCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 2, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPPMCR2_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 2, .opc2 =3D 1, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPPMCR4_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 2, .opc2 =3D 4, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPPMCR5_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 2, .opc2 =3D 5, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPPMCR6_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 2, .opc2 =3D 6, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 4, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "ATCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 7, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPSELR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 8, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 8, .opc2 =3D 1, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPOR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 8, .opc2 =3D 2, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPMR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 8, .opc2 =3D 3, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPOR2_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 8, .opc2 =3D 4, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPMR2_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 8, .opc2 =3D 5, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPFR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 8, .opc2 =3D 6, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + + /* + * Stub RAMINDEX, as we don't actually implement caches, BTB, + * or anything else with cpu internal memory. + * "Read" zeros into the IDATA* and DDATA* output registers. + */ + { .name =3D "RAMINDEX_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, + .access =3D PL3_W, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IDATA0_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, + .access =3D PL3_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IDATA1_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 0, .opc2 =3D 1, + .access =3D PL3_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IDATA2_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 0, .opc2 =3D 2, + .access =3D PL3_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "DDATA0_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 1, .opc2 =3D 0, + .access =3D PL3_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "DDATA1_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 1, .opc2 =3D 1, + .access =3D PL3_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "DDATA2_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 1, .opc2 =3D 2, + .access =3D PL3_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, +}; + +static void aarch64_a710_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a710"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by Section B.4: AArch64 registers */ + cpu->midr =3D 0x412FD471; /* r2p1 */ + cpu->revidr =3D 0; + cpu->isar.id_pfr0 =3D 0x21110131; + cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + cpu->isar.id_dfr0 =3D 0x16011099; + cpu->id_afr0 =3D 0; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x11011121; /* with Crypto */ + cpu->isar.id_mmfr4 =3D 0x21021110; + cpu->isar.id_isar6 =3D 0x01111111; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->isar.id_pfr2 =3D 0x00000011; + cpu->isar.id_aa64pfr0 =3D 0x1201111120111112ull; /* GIC filled in lat= er */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000221ull; + cpu->isar.id_aa64zfr0 =3D 0x0000110100110021ull; /* with Crypto */ + cpu->isar.id_aa64dfr0 =3D 0x000011f010305611ull; + cpu->isar.id_aa64dfr1 =3D 0; + cpu->id_aa64afr0 =3D 0; + cpu->id_aa64afr1 =3D 0; + cpu->isar.id_aa64isar0 =3D 0x0221111110212120ull; /* with Crypto */ + cpu->isar.id_aa64isar1 =3D 0x0010111101211032ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000022200101122ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x1221011110101011ull; + cpu->clidr =3D 0x0000001482000023ull; + cpu->gm_blocksize =3D 4; + cpu->ctr =3D 0x000000049444c004ull; + cpu->dcz_blocksize =3D 4; + /* TODO FEAT_MPAM: mpamidr_el1 =3D 0x0000_0001_0006_003f */ + + /* Section B.5.2: PMCR_EL0 */ + cpu->isar.reset_pmcr_el0 =3D 0xa000; /* with 20 counters */ + + /* Section B.6.7: ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + + /* Section 14: Scalable Vector Extensions support */ + cpu->sve_vq.supported =3D 1 << 0; /* 128bit */ + + /* + * The cortex-a710 TRM does not list CCSIDR values. The layout of + * the caches are in text in Table 7-1, Table 8-1, and Table 9-1. + * + * L1: 4-way set associative 64-byte line size, total either 32K or 64= K. + * L2: 8-way set associative 64 byte line size, total either 256K or 5= 12K. + */ + cpu->ccsidr[0] =3D make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ + cpu->ccsidr[1] =3D cpu->ccsidr[0]; /* L1 icache */ + cpu->ccsidr[2] =3D make_ccsidr64(8, 64, 512 * KiB); /* L2 cache */ + + /* FIXME: Not documented -- copied from neoverse-v1 */ + cpu->reset_sctlr =3D 0x30c50838; + + define_arm_cp_regs(cpu, cortex_a710_cp_reginfo); + + aarch64_add_pauth_properties(obj); + aarch64_add_sve_properties(obj); +} + /* * -cpu max: a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c; @@ -934,6 +1145,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a55", .initfn =3D aarch64_a55_initfn }, { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn }, + { .name =3D "cortex-a710", .initfn =3D aarch64_a710_initfn }, { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "neoverse-v1", .initfn =3D aarch64_neoverse_v1_init= fn }, --=20 2.34.1 From nobody Wed May 15 23:43:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693524370; cv=none; d=zohomail.com; s=zohoarc; b=jgA1ut3yku/8VkAnwyos6ggqpx1frs5q6uNb2j/JYIEhlgKR8F3uihOQXuGI/9j2N1EL299BLdA2/NdgF3211Gops4p2qE+ScKwUREceFm5LE0zZ9pMmqnEalcwy33WIdHVR1EOtBY9j5gwM7FRJ6GLAv+VK9PTdeGjcIq6HyDE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693524370; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=h+xlV3SGZMVXNVWkGKftcbyBWtbVebk+6sY7EU3bpYY=; b=I/4jTCgfIDVdj9v8icQxit7lZ2N7Ibsp3Zq7zgo2RDk7KOgyvJAswJBmDPU5nFGTWGFzk7s3xw+DCa1qiW/p2V+6k0KuBs5BrSTfv/0+cF7ic5B7gLdjzhZN4oSKS7bk3h2O2DPZJASft1MO0YcQJOgTJe2/ITgDOhk34bBzV6U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169352437015639.907502070591704; Thu, 31 Aug 2023 16:26:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbr21-0006oH-Pz; Thu, 31 Aug 2023 19:24:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbr1z-0006nT-Qe for qemu-devel@nongnu.org; Thu, 31 Aug 2023 19:24:55 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbr1r-0002HY-MT for qemu-devel@nongnu.org; Thu, 31 Aug 2023 19:24:55 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1bdf4752c3cso10603925ad.2 for ; Thu, 31 Aug 2023 16:24:45 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id jd5-20020a170903260500b001bb8895848bsm1732711plb.71.2023.08.31.16.24.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 16:24:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693524285; x=1694129085; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h+xlV3SGZMVXNVWkGKftcbyBWtbVebk+6sY7EU3bpYY=; b=UNjaB68YDDIRwEWVvxyeK2ZRUu3iLlAu4fYyaJvxIVO9U74IS8Yr69KSJeAno4ATa0 AjapMPmMQe8ZTyvnb+bTfDaUVEQuJHg6Xs1w2IGaOVhF2foWt/M5oKb0WuE8kTxkizg8 7e5AXGfMZFzSbDxt75QMDAKBSXFNOupLI7nKargJ61l2e3Of0rqhdi0FpFGj3rhTKvp3 IFOq/s+I5XbzC6YKX0pfPQNYkmNqm9MdvXjHSLbRLqUlzKX7MqHJopnD3PrpVw9R8Gzy jKa+FiZBzgV0UF6UKfCT2zk19xU6pgIJbWxPKNTKKoHNwDf6QqjAHdVPIeAdO2aRi0g1 DFAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693524285; x=1694129085; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h+xlV3SGZMVXNVWkGKftcbyBWtbVebk+6sY7EU3bpYY=; b=YcWVnlB/SdZMap26YAFovPoYswnQwo4Q1/f1r2CQa0S5FMMlUBSF5LktXLE4MuLCxG OfWXGhjDr74aI59ONuGzN3DqSz3M0B2rTT0mR5qYxM63hGasgU4WTmn9RTZ8K7iRdhdK CLrj6kkU+sTLRY0WjSX09z5dt1Qx4/FFZm9ETaNvjgtkAlBW2KwC+VxpGyNWzmoNGnwq C39egMhkQAjI6wz23eIQMQECLOTHoZgncyfhSDhDnZCb2dktn/oCDgR2cTA4JmsePVM2 XEQk/mFRvpMb7Txsf99l6WSgfakxuHYRkF2wGb0ElekbwfEkRks8h62eQYFvbfU5jLYL StUA== X-Gm-Message-State: AOJu0Yz6JVThIYJW9WluqMAbRrFEXy9EA8jE8ipddfp5eb6slEkR36lc 3pb0VHHn5q0AMhYrGyg+DQyVK0VPWAxCSrETeZE= X-Google-Smtp-Source: AGHT+IEG2nEjYH5V/EhS5beDeoyLhNk/ug0D6QeLGXbP3LYt6lMHNG5p/IIrL/hN2uMLWyzmcZNGYw== X-Received: by 2002:a17:902:ef8c:b0:1b6:af1a:7dd3 with SMTP id iz12-20020a170902ef8c00b001b6af1a7dd3mr1108532plb.23.1693524284892; Thu, 31 Aug 2023 16:24:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 3/5] target/arm: Implement HCR_EL2.TIDCP Date: Thu, 31 Aug 2023 16:24:39 -0700 Message-Id: <20230831232441.66020-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831232441.66020-1-richard.henderson@linaro.org> References: <20230831232441.66020-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693524371349100001 Content-Type: text/plain; charset="utf-8" Perform the check for EL2 enabled in the security space and the TIDCP bit in an out-of-line helper. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.h | 1 + target/arm/tcg/op_helper.c | 13 +++++++++++++ target/arm/tcg/translate-a64.c | 16 ++++++++++++++-- target/arm/tcg/translate.c | 27 +++++++++++++++++++++++++++ 4 files changed, 55 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 95e32a697a..cf5c55a12b 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -81,6 +81,7 @@ DEF_HELPER_FLAGS_2(check_bxj_trap, TCG_CALL_NO_WG, void, = env, i32) =20 DEF_HELPER_4(access_check_cp_reg, cptr, env, i32, i32, i32) DEF_HELPER_FLAGS_2(lookup_cp_reg, TCG_CALL_NO_RWG_SE, cptr, env, i32) +DEF_HELPER_FLAGS_2(tidcp_el1, TCG_CALL_NO_WG, void, env, i32) DEF_HELPER_3(set_cp_reg, void, env, cptr, i32) DEF_HELPER_2(get_cp_reg, i32, env, cptr) DEF_HELPER_3(set_cp_reg64, void, env, cptr, i64) diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 3baf8004f6..9014c3ca46 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -764,6 +764,19 @@ const void *HELPER(lookup_cp_reg)(CPUARMState *env, ui= nt32_t key) return ri; } =20 +/* + * Test for HCR_EL2.TIDCP at EL1. + * Since implementation defined registers are rare, and within QEMU + * most of them are no-op, do not waste HFLAGS space for this and + * always use a helper. + */ +void HELPER(tidcp_el1)(CPUARMState *env, uint32_t syndrome) +{ + if (arm_hcr_el2_eff(env) & HCR_TIDCP) { + raise_exception_ra(env, EXCP_UDEF, syndrome, 2, GETPC()); + } +} + void HELPER(set_cp_reg)(CPUARMState *env, const void *rip, uint32_t value) { const ARMCPRegInfo *ri =3D rip; diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 0b77c92437..786a568d31 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2154,6 +2154,20 @@ static void handle_sys(DisasContext *s, bool isread, bool need_exit_tb =3D false; TCGv_ptr tcg_ri =3D NULL; TCGv_i64 tcg_rt; + uint32_t syndrome; + + if (crn =3D=3D 11 || crn =3D=3D 15) { + /* + * Check for TIDCP trap, which must take precedence over + * the UNDEF for "no such register" etc. + */ + syndrome =3D syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isre= ad); + switch (s->current_el) { + case 1: + gen_helper_tidcp_el1(cpu_env, tcg_constant_i32(syndrome)); + break; + } + } =20 if (!ri) { /* Unknown register; this might be a guest error or a QEMU @@ -2176,8 +2190,6 @@ static void handle_sys(DisasContext *s, bool isread, /* Emit code to perform further access permissions checks at * runtime; this may result in an exception. */ - uint32_t syndrome; - syndrome =3D syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isre= ad); gen_a64_update_pc(s, 0); tcg_ri =3D tcg_temp_new_ptr(); diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 38ad8dd4bd..47d3bc5fd5 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -4538,6 +4538,20 @@ void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, u= int32_t rn_ofs, tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]); } =20 +static bool aa32_cpreg_encoding_in_impdef_space(uint8_t crn, uint8_t crm) +{ + static const uint16_t mask[3] =3D { + 0b0000000111100111, /* crn =3D=3D 9, crm =3D=3D {c0-c2, c5-c8} = */ + 0b0000000100010011, /* crn =3D=3D 10, crm =3D=3D {c0, c1, c4, c8}= */ + 0b1000000111111111, /* crn =3D=3D 11, crm =3D=3D {c0-c8, c15} = */ + }; + + if (crn >=3D 9 && crn <=3D 11) { + return (mask[crn - 9] >> crm) & 1; + } + return false; +} + static void do_coproc_insn(DisasContext *s, int cpnum, int is64, int opc1, int crn, int crm, int opc2, bool isread, int rt, int rt2) @@ -4619,6 +4633,19 @@ static void do_coproc_insn(DisasContext *s, int cpnu= m, int is64, } } =20 + if (cpnum =3D=3D 15 && aa32_cpreg_encoding_in_impdef_space(crn, crm)) { + /* + * Check for TIDCP trap, which must take precedence over the UNDEF + * for "no such register" etc. It shares precedence with HSTR, + * but raises the same exception, so order doesn't matter. + */ + switch (s->current_el) { + case 1: + gen_helper_tidcp_el1(cpu_env, tcg_constant_i32(syndrome)); + break; + } + } + if (!ri) { /* * Unknown register; this might be a guest error or a QEMU --=20 2.34.1 From nobody Wed May 15 23:43:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693524378207100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/cpu.h | 5 +++++ target/arm/helper.h | 1 + target/arm/tcg/cpu64.c | 1 + target/arm/tcg/op_helper.c | 20 ++++++++++++++++++++ target/arm/tcg/translate-a64.c | 5 +++++ target/arm/tcg/translate.c | 6 ++++++ 7 files changed, 39 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 2e6a7c8961..ce81fd82fc 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -85,6 +85,7 @@ the following architecture extensions: - FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instruc= tions) - FEAT_SPECRES (Speculation restriction instructions) - FEAT_SSBS (Speculative Store Bypass Safe) +- FEAT_TIDCP1 (EL0 use of IMPLEMENTATION DEFINED functionality) - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain) - FEAT_TLBIRANGE (TLB invalidate range instructions) - FEAT_TTCNP (Translation table Common not private translations) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 278cc135c2..c4ce1b915f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3947,6 +3947,11 @@ static inline bool isar_feature_aa64_hcx(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) !=3D 0; } =20 +static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR1, TIDCP1) !=3D 0; +} + static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) !=3D 0; diff --git a/target/arm/helper.h b/target/arm/helper.h index cf5c55a12b..2b02733305 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -81,6 +81,7 @@ DEF_HELPER_FLAGS_2(check_bxj_trap, TCG_CALL_NO_WG, void, = env, i32) =20 DEF_HELPER_4(access_check_cp_reg, cptr, env, i32, i32, i32) DEF_HELPER_FLAGS_2(lookup_cp_reg, TCG_CALL_NO_RWG_SE, cptr, env, i32) +DEF_HELPER_FLAGS_2(tidcp_el0, TCG_CALL_NO_WG, void, env, i32) DEF_HELPER_FLAGS_2(tidcp_el1, TCG_CALL_NO_WG, void, env, i32) DEF_HELPER_3(set_cp_reg, void, env, cptr, i32) DEF_HELPER_2(get_cp_reg, i32, env, cptr) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index ab63526bea..b9691f24f8 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1069,6 +1069,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ t =3D FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */ t =3D FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* FEAT_TIDCP1 */ cpu->isar.id_aa64mmfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr2; diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 9014c3ca46..403f8b09d3 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -777,6 +777,26 @@ void HELPER(tidcp_el1)(CPUARMState *env, uint32_t synd= rome) } } =20 +/* + * Similarly, for FEAT_TIDCP1 at EL0. + * We have already checked for the presence of the feature. + */ +void HELPER(tidcp_el0)(CPUARMState *env, uint32_t syndrome) +{ + /* See arm_sctlr(), but we also need the sctlr el. */ + ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, 0); + int target_el =3D mmu_idx =3D=3D ARMMMUIdx_E20_0 ? 2 : 1; + + /* + * The bit is not valid unless the target el is aa64, but since the + * bit test is simpler perform that first and check validity after. + */ + if ((env->cp15.sctlr_el[target_el] & SCTLR_TIDCP) + && arm_el_is_aa64(env, target_el)) { + raise_exception_ra(env, EXCP_UDEF, syndrome, target_el, GETPC()); + } +} + void HELPER(set_cp_reg)(CPUARMState *env, const void *rip, uint32_t value) { const ARMCPRegInfo *ri =3D rip; diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 786a568d31..15d985d95e 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2163,6 +2163,11 @@ static void handle_sys(DisasContext *s, bool isread, */ syndrome =3D syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isre= ad); switch (s->current_el) { + case 0: + if (dc_isar_feature(aa64_tidcp1, s)) { + gen_helper_tidcp_el0(cpu_env, tcg_constant_i32(syndrome)); + } + break; case 1: gen_helper_tidcp_el1(cpu_env, tcg_constant_i32(syndrome)); break; diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 47d3bc5fd5..976b704200 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -4640,6 +4640,12 @@ static void do_coproc_insn(DisasContext *s, int cpnu= m, int is64, * but raises the same exception, so order doesn't matter. */ switch (s->current_el) { + case 0: + if (arm_dc_feature(s, ARM_FEATURE_AARCH64) + && dc_isar_feature(aa64_tidcp1, s)) { + gen_helper_tidcp_el0(cpu_env, tcg_constant_i32(syndrome)); + } + break; case 1: gen_helper_tidcp_el1(cpu_env, tcg_constant_i32(syndrome)); break; --=20 2.34.1 From nobody Wed May 15 23:43:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693524385; cv=none; d=zohomail.com; s=zohoarc; b=jo0pNiC1d6+0NhA5FS+pWjTi++NawT66OKN07QhCmZ4Gb3v4alyCsazgwBNc9Zgd8nHXR8+VuO79nIGFDgTWrmlNf0crzojFrFIXKtPbXXtH2LEdsF4vEe4DmOedMXQ0Z5WQc/SoqktEWq5nFzME+/nA4mUYumyS+cgcbezbqNY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693524385; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WknjyyvkUA5R2BgSlGNmVEJEpeTJCnFvoRCppP0P3KM=; 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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id jd5-20020a170903260500b001bb8895848bsm1732711plb.71.2023.08.31.16.24.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 16:24:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693524286; x=1694129086; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WknjyyvkUA5R2BgSlGNmVEJEpeTJCnFvoRCppP0P3KM=; b=ID9qTH1e8l70XOoWNZbmTClNjyiLUsqvM7NxEdhHgsY1mzvcMw4mtuJnYAMXnhwr7W 4jixWe8CQMs9vIJBWlRGnhq2Ra0T4kxUVSfASPt48xAQao8j9NwT09x4h9tR88cpzRzK mF3UB1YlDle7hgueVppK6ZL4HThyP6nc+skv+3I8Tzn0a7UmRb9jw8673DJWQ/kSxcgT UcXAbyv+LQHGSV2MiTzLupkVRKU4GAH2tWVC/rFz+/STpy4PS6yWs7QAH1OodedeYUwh s8xOzYPq6nU4asI5CeJ44+i+2RhGkTj3pHXk0HZCrHmRcGOPeGcVbdECjBFc6uucIIlt PmHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693524286; x=1694129086; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WknjyyvkUA5R2BgSlGNmVEJEpeTJCnFvoRCppP0P3KM=; b=Rgfizz4TDHgghKerx9UtWHgl6Dut1mKT16eduj4lnOrHKb1/mYyr7deId4GY8HhL98 2Rt7mTm+jDS2PoyhmJj0wVDI6aNrk47/h/2vPcGsF7a4iXhp1G2a4KcdAgIVfuX3vMZw 4EbhFOlHkp4e3WQPKBfwhJtlV2mnHroVicWT7f2pFBPjOr8LwMY8Goic7qMhRBl08pxZ 4XbhOWvuc9JxhdIcS5CX6QqU8OZFPzq5ivrspnqEguxHWMugA+/LhqVfg8tdVUPwAh+q pogA2eRuxcWa1y/EjV+v6rmKc8hcdq9eIiJGGyuHBRZQn0+6rLA1VvwE3OlqoEpkSx9B O7SA== X-Gm-Message-State: AOJu0YyIbGs7ib80MLFh3uQuigV9dmGbyGO1HqHmMv3VDdC7GOSCKr+V ii/05cEI+0FZHuTspZ/HAfDu8SQCv043i+QJlBc= X-Google-Smtp-Source: AGHT+IHAeOy0lLd+S/ScgvLrZs7FxN41prYgIHyvrqaFqOlxmVb04158MkvZgTmTZBed8YQWWUwxfw== X-Received: by 2002:a05:6a21:7742:b0:14d:f8a4:d0d1 with SMTP id bc2-20020a056a21774200b0014df8a4d0d1mr1171762pzc.35.1693524286590; Thu, 31 Aug 2023 16:24:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 5/5] target/arm: Enable SCTLR_EL1.TIDCP for user-only Date: Thu, 31 Aug 2023 16:24:41 -0700 Message-Id: <20230831232441.66020-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831232441.66020-1-richard.henderson@linaro.org> References: <20230831232441.66020-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693524385523100003 Content-Type: text/plain; charset="utf-8" The linux kernel detects and enables this bit. Once trapped, EC_SYSTEMREGISTERTRAP is treated like EC_UNCATEGORIZED, so no changes required within linux-user/aarch64/cpu_loop.c. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0bb0585441..b9e09a702d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -243,6 +243,10 @@ static void arm_cpu_reset_hold(Object *obj) SCTLR_EnDA | SCTLR_EnDB); /* Trap on btype=3D3 for PACIxSP. */ env->cp15.sctlr_el[1] |=3D SCTLR_BT0; + /* Trap on implementation defined registers. */ + if (cpu_isar_feature(aa64_tidcp1, cpu)) { + env->cp15.sctlr_el[1] |=3D SCTLR_TIDCP; + } /* and to the FP/Neon instructions */ env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, CPACR_EL1, FPEN, 3); --=20 2.34.1