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bh=o+2KyMTfnBLukFgKCHiZLb49AOPGtSjL7wjYjiU/DWM=; b=Adc5g9JJzFCHlFU7kjXMDZUACiVvhBAOqbOk13KAjPTVyQsTwPOesNJ0xVnNdHPwsx yxvvpBG2GK9zLsQjkB2WsYz2HF4dWmobJmJhOSP+nBouqmXtyvIyMr9xRRrJaz2jFByH AgeqrTD4mSlv18H3LE/37/Ku6EzUrZk7AWZkMdVY81+56gQKB17wU4Oqj5YauEBKyBR6 rkSxeDDZBxiLkhoO3IcmMAvOJxVrI8u0iQfmgXjpcq2V3lCuAyqhlqGQfA+MFiA8lkma aXUuAj/I92ciyWSHVvacKj6Hgwv/f8O+O3EfG5JJpOT+iJCH8ny7N0eDaHjRJY4lBVYN O+8Q== X-Gm-Message-State: AOJu0Yx0KzC18svSMRMl1f0KL13mxLoqfFXESV3cf4DZEdOXi+X1PhKT 8GbLx4NnUEFdK1fMg0dVD1/nUw== X-Google-Smtp-Source: AGHT+IGBw4V6ZwO6/SUWQbgZrCXTzC4dY3ZvnQ9j2K7D9NftKl5+lQxmM5mdTvGYYxWZbW6KXGYtwg== X-Received: by 2002:a1c:7217:0:b0:3fe:21b9:806 with SMTP id n23-20020a1c7217000000b003fe21b90806mr4243980wmc.0.1693486614756; Thu, 31 Aug 2023 05:56:54 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 01/41] accel: Remove HAX accelerator Date: Thu, 31 Aug 2023 14:56:03 +0200 Message-ID: <20230831125646.67855-2-philmd@linaro.org> In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 3.1 on 10.11.54.2 X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Thomas Huth , qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , libvir-list@redhat.com, Richard Henderson , Markus Armbruster , Wainer dos Santos Moschetta , Yanan Wang , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Marcel Apfelbaum , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Beraldo Leal Errors-To: libvir-list-bounces@redhat.com Sender: "libvir-list" X-Scanned-By: MIMEDefang 3.1 on 10.11.54.4 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: linaro.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1693486905519100001 HAX is deprecated since commits 73741fda6c ("MAINTAINERS: Abort HAXM maintenance") and 90c167a1da ("docs/about/deprecated: Mark HAXM in QEMU as deprecated"), released in v8.0.0. Per the latest HAXM release (v7.8 [*]), the latest QEMU supported is v7.2: Note: Up to this release, HAXM supports QEMU from 2.9.0 to 7.2.0. The next commit (https://github.com/intel/haxm/commit/da1b8ec072) added: HAXM v7.8.0 is our last release and we will not accept pull requests or respond to issues after this. It became very hard to build and test HAXM. Its previous maintainers made it clear they won't help. It doesn't seem to be a very good use of QEMU maintainers to spend their time in a dead project. Save our time by removing this orphan zombie code. [*] https://github.com/intel/haxm/releases/tag/v7.8.0 Reviewed-by: Richard Henderson Acked-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Message-Id: <20230831082016.60885-1-philmd@linaro.org> --- MAINTAINERS | 8 - docs/about/build-platforms.rst | 2 +- docs/about/deprecated.rst | 6 - docs/about/index.rst | 2 +- docs/about/removed-features.rst | 11 +- docs/system/index.rst | 2 +- docs/system/introduction.rst | 3 - meson.build | 7 - include/exec/poison.h | 1 - include/hw/core/cpu.h | 2 +- include/sysemu/hax.h | 49 - include/sysemu/hw_accel.h | 1 - target/i386/hax/hax-accel-ops.h | 31 - target/i386/hax/hax-i386.h | 98 -- target/i386/hax/hax-interface.h | 369 ------ target/i386/hax/hax-posix.h | 61 - target/i386/hax/hax-windows.h | 88 -- accel/stubs/hax-stub.c | 24 - hw/intc/apic_common.c | 3 +- softmmu/cpus.c | 6 - softmmu/vl.c | 6 - target/i386/hax/hax-accel-ops.c | 105 -- target/i386/hax/hax-all.c | 1141 ----------------- target/i386/hax/hax-mem.c | 323 ----- target/i386/hax/hax-posix.c | 305 ----- target/i386/hax/hax-windows.c | 485 ------- accel/Kconfig | 3 - accel/stubs/meson.build | 1 - meson_options.txt | 2 - qemu-options.hx | 8 +- .../ci/org.centos/stream/8/x86_64/configure | 1 - scripts/meson-buildoptions.sh | 3 - target/i386/hax/meson.build | 7 - target/i386/meson.build | 1 - 34 files changed, 16 insertions(+), 3149 deletions(-) delete mode 100644 include/sysemu/hax.h delete mode 100644 target/i386/hax/hax-accel-ops.h delete mode 100644 target/i386/hax/hax-i386.h delete mode 100644 target/i386/hax/hax-interface.h delete mode 100644 target/i386/hax/hax-posix.h delete mode 100644 target/i386/hax/hax-windows.h delete mode 100644 accel/stubs/hax-stub.c delete mode 100644 target/i386/hax/hax-accel-ops.c delete mode 100644 target/i386/hax/hax-all.c delete mode 100644 target/i386/hax/hax-mem.c delete mode 100644 target/i386/hax/hax-posix.c delete mode 100644 target/i386/hax/hax-windows.c delete mode 100644 target/i386/hax/meson.build diff --git a/MAINTAINERS b/MAINTAINERS index 6111b6b4d9..3b29568ed4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -543,14 +543,6 @@ F: include/sysemu/xen.h F: include/sysemu/xen-mapcache.h F: stubs/xen-hw-stub.c =20 -Guest CPU Cores (HAXM) ---------------------- -X86 HAXM CPUs -S: Orphan -F: accel/stubs/hax-stub.c -F: include/sysemu/hax.h -F: target/i386/hax/ - Guest CPU Cores (NVMM) ---------------------- NetBSD Virtual Machine Monitor (NVMM) CPU support diff --git a/docs/about/build-platforms.rst b/docs/about/build-platforms.rst index 0e2cb9e770..f2a7aec56f 100644 --- a/docs/about/build-platforms.rst +++ b/docs/about/build-platforms.rst @@ -52,7 +52,7 @@ Those hosts are officially supported, with various accele= rators: * - SPARC - tcg * - x86 - - hax, hvf (64 bit only), kvm, nvmm, tcg, whpx (64 bit only), xen + - hvf (64 bit only), kvm, nvmm, tcg, whpx (64 bit only), xen =20 Other host architectures are not supported. It is possible to build QEMU s= ystem emulation on an unsupported host architecture using the configure diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 92a2bafd2b..dc4da95329 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -105,12 +105,6 @@ Use ``-machine hpet=3Doff`` instead. The ``-no-acpi`` setting has been turned into a machine property. Use ``-machine acpi=3Doff`` instead. =20 -``-accel hax`` (since 8.0) -'''''''''''''''''''''''''' - -The HAXM project has been retired (see https://github.com/intel/haxm#statu= s). -Use "whpx" (on Windows) or "hvf" (on macOS) instead. - ``-async-teardown`` (since 8.1) ''''''''''''''''''''''''''''''' =20 diff --git a/docs/about/index.rst b/docs/about/index.rst index b00b584b31..4f96ab5d91 100644 --- a/docs/about/index.rst +++ b/docs/about/index.rst @@ -8,7 +8,7 @@ QEMU can be used in several different ways. The most common= is for :ref:`System Emulation`, where it provides a virtual model of an entire machine (CPU, memory and emulated devices) to run a guest OS. In this mode the CPU may be fully emulated, or it may work with a -hypervisor such as KVM, Xen, Hax or Hypervisor.Framework to allow the +hypervisor such as KVM, Xen or Hypervisor.Framework to allow the guest to run directly on the host CPU. =20 The second supported way to use QEMU is :ref:`User Mode Emulation`, diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.= rst index 5b258b446b..c2043fd415 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -659,15 +659,18 @@ Use ``Icelake-Server`` instead. System accelerators ------------------- =20 -Userspace local APIC with KVM (x86, removed 8.0) -'''''''''''''''''''''''''''''''''''''''''''''''' +Userspace local APIC with KVM (x86, removed in 8.0) +''''''''''''''''''''''''''''''''''''''''''''''''''' =20 ``-M kernel-irqchip=3Doff`` cannot be used on KVM if the CPU model includes a local APIC. The ``split`` setting is supported, as is using ``-M kernel-irqchip=3Doff`` when the CPU does not have a local APIC. =20 -System accelerators -------------------- +HAXM (``-accel hax``) (removed in 8.2) +'''''''''''''''''''''''''''''''''''''' + +The HAXM project has been retired (see https://github.com/intel/haxm#statu= s). +Use "whpx" (on Windows) or "hvf" (on macOS) instead. =20 MIPS "Trap-and-Emulate" KVM support (removed in 8.0) '''''''''''''''''''''''''''''''''''''''''''''''''''' diff --git a/docs/system/index.rst b/docs/system/index.rst index 3605bbe1ce..45bf1f19e7 100644 --- a/docs/system/index.rst +++ b/docs/system/index.rst @@ -6,7 +6,7 @@ System Emulation =20 This section of the manual is the overall guide for users using QEMU for full system emulation (as opposed to user-mode emulation). -This includes working with hypervisors such as KVM, Xen, Hax +This includes working with hypervisors such as KVM, Xen or Hypervisor.Framework. =20 .. toctree:: diff --git a/docs/system/introduction.rst b/docs/system/introduction.rst index 3e256f8326..51ac132d6c 100644 --- a/docs/system/introduction.rst +++ b/docs/system/introduction.rst @@ -21,9 +21,6 @@ Tiny Code Generator (TCG) capable of emulating many CPUs. * - Xen - Linux (as dom0) - Arm, x86 - * - Intel HAXM (hax) - - Linux, Windows - - x86 * - Hypervisor Framework (hvf) - MacOS - x86 (64 bit only), Arm (64 bit only) diff --git a/meson.build b/meson.build index 98e68ef0b1..ec14079c67 100644 --- a/meson.build +++ b/meson.build @@ -140,7 +140,6 @@ if cpu in ['x86', 'x86_64', 'arm', 'aarch64'] endif if cpu in ['x86', 'x86_64'] accelerator_targets +=3D { - 'CONFIG_HAX': ['i386-softmmu', 'x86_64-softmmu'], 'CONFIG_HVF': ['x86_64-softmmu'], 'CONFIG_NVMM': ['i386-softmmu', 'x86_64-softmmu'], 'CONFIG_WHPX': ['i386-softmmu', 'x86_64-softmmu'], @@ -663,11 +662,6 @@ if get_option('hvf').allowed() accelerators +=3D 'CONFIG_HVF' endif endif -if get_option('hax').allowed() - if get_option('hax').enabled() or targetos in ['windows', 'darwin', 'net= bsd'] - accelerators +=3D 'CONFIG_HAX' - endif -endif if targetos =3D=3D 'netbsd' nvmm =3D cc.find_library('nvmm', required: get_option('nvmm')) if nvmm.found() @@ -4140,7 +4134,6 @@ endif summary_info =3D {} if have_system summary_info +=3D {'KVM support': config_all.has_key('CONFIG_KVM')} - summary_info +=3D {'HAX support': config_all.has_key('CONFIG_HAX')} summary_info +=3D {'HVF support': config_all.has_key('CONFIG_HVF')} summary_info +=3D {'WHPX support': config_all.has_key('CONFIG_WHPX'= )} summary_info +=3D {'NVMM support': config_all.has_key('CONFIG_NVMM'= )} diff --git a/include/exec/poison.h b/include/exec/poison.h index e94ee8dfef..1ea5633eb3 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -81,7 +81,6 @@ #pragma GCC poison CONFIG_SPARC_DIS #pragma GCC poison CONFIG_XTENSA_DIS =20 -#pragma GCC poison CONFIG_HAX #pragma GCC poison CONFIG_HVF #pragma GCC poison CONFIG_LINUX_USER #pragma GCC poison CONFIG_KVM diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index fdcbe87352..92a4234439 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -422,7 +422,7 @@ struct CPUState { int32_t exception_index; =20 AccelCPUState *accel; - /* shared by kvm, hax and hvf */ + /* shared by kvm and hvf */ bool vcpu_dirty; =20 /* Used to keep track of an outstanding cpu throttle thread for migrat= ion diff --git a/include/sysemu/hax.h b/include/sysemu/hax.h deleted file mode 100644 index 80fc716f80..0000000000 --- a/include/sysemu/hax.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * QEMU HAXM support - * - * Copyright IBM, Corp. 2008 - * - * Authors: - * Anthony Liguori - * - * Copyright (c) 2011 Intel Corporation - * Written by: - * Jiang Yunhong - * Xin Xiaohui - * Zhang Xiantao - * - * Copyright 2016 Google, Inc. - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - * - */ - -/* header to be included in non-HAX-specific code */ - -#ifndef QEMU_HAX_H -#define QEMU_HAX_H - -int hax_sync_vcpus(void); - -#ifdef NEED_CPU_H -# ifdef CONFIG_HAX -# define CONFIG_HAX_IS_POSSIBLE -# endif -#else /* !NEED_CPU_H */ -# define CONFIG_HAX_IS_POSSIBLE -#endif - -#ifdef CONFIG_HAX_IS_POSSIBLE - -extern bool hax_allowed; - -#define hax_enabled() (hax_allowed) - -#else /* !CONFIG_HAX_IS_POSSIBLE */ - -#define hax_enabled() (0) - -#endif /* CONFIG_HAX_IS_POSSIBLE */ - -#endif /* QEMU_HAX_H */ diff --git a/include/sysemu/hw_accel.h b/include/sysemu/hw_accel.h index 22903a55f7..c71b77e71f 100644 --- a/include/sysemu/hw_accel.h +++ b/include/sysemu/hw_accel.h @@ -12,7 +12,6 @@ #define QEMU_HW_ACCEL_H =20 #include "hw/core/cpu.h" -#include "sysemu/hax.h" #include "sysemu/kvm.h" #include "sysemu/hvf.h" #include "sysemu/whpx.h" diff --git a/target/i386/hax/hax-accel-ops.h b/target/i386/hax/hax-accel-op= s.h deleted file mode 100644 index 9e357e7b40..0000000000 --- a/target/i386/hax/hax-accel-ops.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Accelerator CPUS Interface - * - * Copyright 2020 SUSE LLC - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - */ - -#ifndef TARGET_I386_HAX_ACCEL_OPS_H -#define TARGET_I386_HAX_ACCEL_OPS_H - -#include "sysemu/cpus.h" - -#include "hax-interface.h" -#include "hax-i386.h" - -int hax_init_vcpu(CPUState *cpu); -int hax_smp_cpu_exec(CPUState *cpu); -int hax_populate_ram(uint64_t va, uint64_t size); - -void hax_cpu_synchronize_state(CPUState *cpu); -void hax_cpu_synchronize_post_reset(CPUState *cpu); -void hax_cpu_synchronize_post_init(CPUState *cpu); -void hax_cpu_synchronize_pre_loadvm(CPUState *cpu); - -int hax_vcpu_destroy(CPUState *cpu); -void hax_raise_event(CPUState *cpu); -void hax_reset_vcpu_state(void *opaque); - -#endif /* TARGET_I386_HAX_ACCEL_OPS_H */ diff --git a/target/i386/hax/hax-i386.h b/target/i386/hax/hax-i386.h deleted file mode 100644 index 87153f40ab..0000000000 --- a/target/i386/hax/hax-i386.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * QEMU HAXM support - * - * Copyright (c) 2011 Intel Corporation - * Written by: - * Jiang Yunhong - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - * - */ - -#ifndef HAX_I386_H -#define HAX_I386_H - -#include "cpu.h" -#include "sysemu/hax.h" - -#ifdef CONFIG_POSIX -typedef int hax_fd; -#endif - -#ifdef CONFIG_WIN32 -typedef HANDLE hax_fd; -#endif - -extern struct hax_state hax_global; - -struct AccelCPUState { -#ifdef _WIN32 - HANDLE hThread; -#endif - hax_fd fd; - int vcpu_id; - struct hax_tunnel *tunnel; - unsigned char *iobuf; -}; - -struct hax_state { - hax_fd fd; /* the global hax device interface */ - uint32_t version; - struct hax_vm *vm; - uint64_t mem_quota; - bool supports_64bit_ramblock; -}; - -#define HAX_MAX_VCPU 0x10 - -struct hax_vm { - hax_fd fd; - int id; - int numvcpus; - AccelCPUState **vcpus; -}; - -/* Functions exported to host specific mode */ -hax_fd hax_vcpu_get_fd(CPUArchState *env); -int valid_hax_tunnel_size(uint16_t size); - -/* Host specific functions */ -int hax_mod_version(struct hax_state *hax, struct hax_module_version *vers= ion); -int hax_inject_interrupt(CPUArchState *env, int vector); -struct hax_vm *hax_vm_create(struct hax_state *hax, int max_cpus); -int hax_vcpu_run(AccelCPUState *vcpu); -int hax_vcpu_create(int id); -void hax_kick_vcpu_thread(CPUState *cpu); - -int hax_sync_vcpu_state(CPUArchState *env, struct vcpu_state_t *state, - int set); -int hax_sync_msr(CPUArchState *env, struct hax_msr_data *msrs, int set); -int hax_sync_fpu(CPUArchState *env, struct fx_layout *fl, int set); - -int hax_vm_destroy(struct hax_vm *vm); -int hax_capability(struct hax_state *hax, struct hax_capabilityinfo *cap); -int hax_notify_qemu_version(hax_fd vm_fd, struct hax_qemu_version *qversio= n); -int hax_set_ram(uint64_t start_pa, uint32_t size, uint64_t host_va, int fl= ags); - -/* Common host function */ -int hax_host_create_vm(struct hax_state *hax, int *vm_id); -hax_fd hax_host_open_vm(struct hax_state *hax, int vm_id); -int hax_host_create_vcpu(hax_fd vm_fd, int vcpuid); -hax_fd hax_host_open_vcpu(int vmid, int vcpuid); -int hax_host_setup_vcpu_channel(AccelCPUState *vcpu); -hax_fd hax_mod_open(void); -void hax_memory_init(void); - - -#ifdef CONFIG_POSIX -#include "hax-posix.h" -#endif - -#ifdef CONFIG_WIN32 -#include "hax-windows.h" -#endif - -#include "hax-interface.h" - -#endif diff --git a/target/i386/hax/hax-interface.h b/target/i386/hax/hax-interfac= e.h deleted file mode 100644 index 537ae084e9..0000000000 --- a/target/i386/hax/hax-interface.h +++ /dev/null @@ -1,369 +0,0 @@ -/* - * QEMU HAXM support - * - * Copyright (c) 2011 Intel Corporation - * Written by: - * Jiang Yunhong - * Xin Xiaohui - * Zhang Xiantao - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - * - */ - -/* Interface with HAX kernel module */ - -#ifndef HAX_INTERFACE_H -#define HAX_INTERFACE_H - -/* fx_layout has 3 formats table 3-56, 512bytes */ -struct fx_layout { - uint16_t fcw; - uint16_t fsw; - uint8_t ftw; - uint8_t res1; - uint16_t fop; - union { - struct { - uint32_t fip; - uint16_t fcs; - uint16_t res2; - }; - uint64_t fpu_ip; - }; - union { - struct { - uint32_t fdp; - uint16_t fds; - uint16_t res3; - }; - uint64_t fpu_dp; - }; - uint32_t mxcsr; - uint32_t mxcsr_mask; - uint8_t st_mm[8][16]; - uint8_t mmx_1[8][16]; - uint8_t mmx_2[8][16]; - uint8_t pad[96]; -} __attribute__ ((aligned(8))); - -struct vmx_msr { - uint64_t entry; - uint64_t value; -} __attribute__ ((__packed__)); - -/* - * Fixed array is not good, but it makes Mac support a bit easier by avoid= ing - * memory map or copyin staff. - */ -#define HAX_MAX_MSR_ARRAY 0x20 -struct hax_msr_data { - uint16_t nr_msr; - uint16_t done; - uint16_t pad[2]; - struct vmx_msr entries[HAX_MAX_MSR_ARRAY]; -} __attribute__ ((__packed__)); - -union interruptibility_state_t { - uint32_t raw; - struct { - uint32_t sti_blocking:1; - uint32_t movss_blocking:1; - uint32_t smi_blocking:1; - uint32_t nmi_blocking:1; - uint32_t reserved:28; - }; - uint64_t pad; -}; - -typedef union interruptibility_state_t interruptibility_state_t; - -/* Segment descriptor */ -struct segment_desc_t { - uint16_t selector; - uint16_t _dummy; - uint32_t limit; - uint64_t base; - union { - struct { - uint32_t type:4; - uint32_t desc:1; - uint32_t dpl:2; - uint32_t present:1; - uint32_t:4; - uint32_t available:1; - uint32_t long_mode:1; - uint32_t operand_size:1; - uint32_t granularity:1; - uint32_t null:1; - uint32_t:15; - }; - uint32_t ar; - }; - uint32_t ipad; -}; - -typedef struct segment_desc_t segment_desc_t; - -struct vcpu_state_t { - union { - uint64_t _regs[16]; - struct { - union { - struct { - uint8_t _al, _ah; - }; - uint16_t _ax; - uint32_t _eax; - uint64_t _rax; - }; - union { - struct { - uint8_t _cl, _ch; - }; - uint16_t _cx; - uint32_t _ecx; - uint64_t _rcx; - }; - union { - struct { - uint8_t _dl, _dh; - }; - uint16_t _dx; - uint32_t _edx; - uint64_t _rdx; - }; - union { - struct { - uint8_t _bl, _bh; - }; - uint16_t _bx; - uint32_t _ebx; - uint64_t _rbx; - }; - union { - uint16_t _sp; - uint32_t _esp; - uint64_t _rsp; - }; - union { - uint16_t _bp; - uint32_t _ebp; - uint64_t _rbp; - }; - union { - uint16_t _si; - uint32_t _esi; - uint64_t _rsi; - }; - union { - uint16_t _di; - uint32_t _edi; - uint64_t _rdi; - }; - - uint64_t _r8; - uint64_t _r9; - uint64_t _r10; - uint64_t _r11; - uint64_t _r12; - uint64_t _r13; - uint64_t _r14; - uint64_t _r15; - }; - }; - - union { - uint32_t _eip; - uint64_t _rip; - }; - - union { - uint32_t _eflags; - uint64_t _rflags; - }; - - segment_desc_t _cs; - segment_desc_t _ss; - segment_desc_t _ds; - segment_desc_t _es; - segment_desc_t _fs; - segment_desc_t _gs; - segment_desc_t _ldt; - segment_desc_t _tr; - - segment_desc_t _gdt; - segment_desc_t _idt; - - uint64_t _cr0; - uint64_t _cr2; - uint64_t _cr3; - uint64_t _cr4; - - uint64_t _dr0; - uint64_t _dr1; - uint64_t _dr2; - uint64_t _dr3; - uint64_t _dr6; - uint64_t _dr7; - uint64_t _pde; - - uint32_t _efer; - - uint32_t _sysenter_cs; - uint64_t _sysenter_eip; - uint64_t _sysenter_esp; - - uint32_t _activity_state; - uint32_t pad; - interruptibility_state_t _interruptibility_state; -}; - -/* HAX exit status */ -enum exit_status { - /* IO port request */ - HAX_EXIT_IO =3D 1, - /* MMIO instruction emulation */ - HAX_EXIT_MMIO, - /* QEMU emulation mode request, currently means guest enter non-PG mod= e */ - HAX_EXIT_REAL, - /* - * Interrupt window open, qemu can inject interrupt now - * Also used when signal pending since at that time qemu usually need - * check interrupt - */ - HAX_EXIT_INTERRUPT, - /* Unknown vmexit, mostly trigger reboot */ - HAX_EXIT_UNKNOWN_VMEXIT, - /* HALT from guest */ - HAX_EXIT_HLT, - /* Reboot request, like because of tripple fault in guest */ - HAX_EXIT_STATECHANGE, - /* the vcpu is now only paused when destroy, so simply return to hax */ - HAX_EXIT_PAUSED, - HAX_EXIT_FAST_MMIO, -}; - -/* - * The interface definition: - * 1. vcpu_run execute will return 0 on success, otherwise mean failed - * 2. exit_status return the exit reason, as stated in enum exit_status - * 3. exit_reason is the vmx exit reason - */ -struct hax_tunnel { - uint32_t _exit_reason; - uint32_t _exit_flag; - uint32_t _exit_status; - uint32_t user_event_pending; - int ready_for_interrupt_injection; - int request_interrupt_window; - union { - struct { - /* 0: read, 1: write */ -#define HAX_EXIT_IO_IN 1 -#define HAX_EXIT_IO_OUT 0 - uint8_t _direction; - uint8_t _df; - uint16_t _size; - uint16_t _port; - uint16_t _count; - uint8_t _flags; - uint8_t _pad0; - uint16_t _pad1; - uint32_t _pad2; - uint64_t _vaddr; - } pio; - struct { - uint64_t gla; - } mmio; - struct { - } state; - }; -} __attribute__ ((__packed__)); - -struct hax_module_version { - uint32_t compat_version; - uint32_t cur_version; -} __attribute__ ((__packed__)); - -/* This interface is support only after API version 2 */ -struct hax_qemu_version { - /* Current API version in QEMU */ - uint32_t cur_version; - /* The minimum API version supported by QEMU */ - uint32_t min_version; -} __attribute__ ((__packed__)); - -/* The mac specfic interface to qemu, mostly is ioctl related */ -struct hax_tunnel_info { - uint64_t va; - uint64_t io_va; - uint16_t size; - uint16_t pad[3]; -} __attribute__ ((__packed__)); - -struct hax_alloc_ram_info { - uint32_t size; - uint32_t pad; - uint64_t va; -} __attribute__ ((__packed__)); - -struct hax_ramblock_info { - uint64_t start_va; - uint64_t size; - uint64_t reserved; -} __attribute__ ((__packed__)); - -#define HAX_RAM_INFO_ROM 0x01 /* Read-Only */ -#define HAX_RAM_INFO_INVALID 0x80 /* Unmapped, usually used for MMIO */ -struct hax_set_ram_info { - uint64_t pa_start; - uint32_t size; - uint8_t flags; - uint8_t pad[3]; - uint64_t va; -} __attribute__ ((__packed__)); - -#define HAX_CAP_STATUS_WORKING 0x1 -#define HAX_CAP_STATUS_NOTWORKING 0x0 -#define HAX_CAP_WORKSTATUS_MASK 0x1 - -#define HAX_CAP_FAILREASON_VT 0x1 -#define HAX_CAP_FAILREASON_NX 0x2 - -#define HAX_CAP_MEMQUOTA 0x2 -#define HAX_CAP_UG 0x4 -#define HAX_CAP_64BIT_RAMBLOCK 0x8 - -struct hax_capabilityinfo { - /* bit 0: 1 - working - * 0 - not working, possibly because NT/NX disabled - * bit 1: 1 - memory limitation working - * 0 - no memory limitation - */ - uint16_t wstatus; - /* valid when not working - * bit 0: VT not enabeld - * bit 1: NX not enabled*/ - uint16_t winfo; - uint32_t pad; - uint64_t mem_quota; -} __attribute__ ((__packed__)); - -struct hax_fastmmio { - uint64_t gpa; - union { - uint64_t value; - uint64_t gpa2; /* since HAX API v4 */ - }; - uint8_t size; - uint8_t direction; - uint16_t reg_index; - uint32_t pad0; - uint64_t _cr0; - uint64_t _cr2; - uint64_t _cr3; - uint64_t _cr4; -} __attribute__ ((__packed__)); -#endif diff --git a/target/i386/hax/hax-posix.h b/target/i386/hax/hax-posix.h deleted file mode 100644 index fb7c64426d..0000000000 --- a/target/i386/hax/hax-posix.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * QEMU HAXM support - * - * Copyright (c) 2011 Intel Corporation - * Written by: - * Jiang Yunhong - * Xin Xiaohui - * Zhang Xiantao - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - * - */ - -#ifndef TARGET_I386_HAX_POSIX_H -#define TARGET_I386_HAX_POSIX_H - -#include - -#define HAX_INVALID_FD (-1) -static inline int hax_invalid_fd(hax_fd fd) -{ - return fd <=3D 0; -} - -static inline void hax_mod_close(struct hax_state *hax) -{ - close(hax->fd); -} - -static inline void hax_close_fd(hax_fd fd) -{ - close(fd); -} - -/* HAX model level ioctl */ -#define HAX_IOCTL_VERSION _IOWR(0, 0x20, struct hax_module_version) -#define HAX_IOCTL_CREATE_VM _IOWR(0, 0x21, uint32_t) -#define HAX_IOCTL_DESTROY_VM _IOW(0, 0x22, uint32_t) -#define HAX_IOCTL_CAPABILITY _IOR(0, 0x23, struct hax_capabilityinfo) - -#define HAX_VM_IOCTL_VCPU_CREATE _IOWR(0, 0x80, uint32_t) -#define HAX_VM_IOCTL_ALLOC_RAM _IOWR(0, 0x81, struct hax_alloc_ram_info) -#define HAX_VM_IOCTL_SET_RAM _IOWR(0, 0x82, struct hax_set_ram_info) -#define HAX_VM_IOCTL_VCPU_DESTROY _IOW(0, 0x83, uint32_t) -#define HAX_VM_IOCTL_NOTIFY_QEMU_VERSION _IOW(0, 0x84, struct hax_qemu_ver= sion) -#define HAX_VM_IOCTL_ADD_RAMBLOCK _IOW(0, 0x85, struct hax_ramblock_info) - -#define HAX_VCPU_IOCTL_RUN _IO(0, 0xc0) -#define HAX_VCPU_IOCTL_SET_MSRS _IOWR(0, 0xc1, struct hax_msr_data) -#define HAX_VCPU_IOCTL_GET_MSRS _IOWR(0, 0xc2, struct hax_msr_data) - -#define HAX_VCPU_IOCTL_SET_FPU _IOW(0, 0xc3, struct fx_layout) -#define HAX_VCPU_IOCTL_GET_FPU _IOR(0, 0xc4, struct fx_layout) - -#define HAX_VCPU_IOCTL_SETUP_TUNNEL _IOWR(0, 0xc5, struct hax_tunnel_info) -#define HAX_VCPU_IOCTL_INTERRUPT _IOWR(0, 0xc6, uint32_t) -#define HAX_VCPU_SET_REGS _IOWR(0, 0xc7, struct vcpu_state_t) -#define HAX_VCPU_GET_REGS _IOWR(0, 0xc8, struct vcpu_state_t) - -#endif /* TARGET_I386_HAX_POSIX_H */ diff --git a/target/i386/hax/hax-windows.h b/target/i386/hax/hax-windows.h deleted file mode 100644 index b1f5d4f32f..0000000000 --- a/target/i386/hax/hax-windows.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * QEMU HAXM support - * - * Copyright IBM, Corp. 2008 - * - * Authors: - * Anthony Liguori - * - * Copyright (c) 2011 Intel Corporation - * Written by: - * Jiang Yunhong - * Xin Xiaohui - * Zhang Xiantao - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - * - */ - -#ifndef TARGET_I386_HAX_WINDOWS_H -#define TARGET_I386_HAX_WINDOWS_H - -#include -#include - -#include "hax-accel-ops.h" - -#define HAX_INVALID_FD INVALID_HANDLE_VALUE - -static inline void hax_mod_close(struct hax_state *hax) -{ - CloseHandle(hax->fd); -} - -static inline void hax_close_fd(hax_fd fd) -{ - CloseHandle(fd); -} - -static inline int hax_invalid_fd(hax_fd fd) -{ - return (fd =3D=3D INVALID_HANDLE_VALUE); -} - -#define HAX_DEVICE_TYPE 0x4000 - -#define HAX_IOCTL_VERSION CTL_CODE(HAX_DEVICE_TYPE, 0x900, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) -#define HAX_IOCTL_CREATE_VM CTL_CODE(HAX_DEVICE_TYPE, 0x901, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) -#define HAX_IOCTL_CAPABILITY CTL_CODE(HAX_DEVICE_TYPE, 0x910, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) - -#define HAX_VM_IOCTL_VCPU_CREATE CTL_CODE(HAX_DEVICE_TYPE, 0x902, \ - METHOD_BUFFERED, FILE_ANY_ACCE= SS) -#define HAX_VM_IOCTL_ALLOC_RAM CTL_CODE(HAX_DEVICE_TYPE, 0x903, \ - METHOD_BUFFERED, FILE_ANY_ACCE= SS) -#define HAX_VM_IOCTL_SET_RAM CTL_CODE(HAX_DEVICE_TYPE, 0x904, \ - METHOD_BUFFERED, FILE_ANY_ACCE= SS) -#define HAX_VM_IOCTL_VCPU_DESTROY CTL_CODE(HAX_DEVICE_TYPE, 0x905, \ - METHOD_BUFFERED, FILE_ANY_ACCE= SS) -#define HAX_VM_IOCTL_ADD_RAMBLOCK CTL_CODE(HAX_DEVICE_TYPE, 0x913, \ - METHOD_BUFFERED, FILE_ANY_ACCE= SS) - -#define HAX_VCPU_IOCTL_RUN CTL_CODE(HAX_DEVICE_TYPE, 0x906, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) -#define HAX_VCPU_IOCTL_SET_MSRS CTL_CODE(HAX_DEVICE_TYPE, 0x907, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) -#define HAX_VCPU_IOCTL_GET_MSRS CTL_CODE(HAX_DEVICE_TYPE, 0x908, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) -#define HAX_VCPU_IOCTL_SET_FPU CTL_CODE(HAX_DEVICE_TYPE, 0x909, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) -#define HAX_VCPU_IOCTL_GET_FPU CTL_CODE(HAX_DEVICE_TYPE, 0x90a, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) - -#define HAX_VCPU_IOCTL_SETUP_TUNNEL CTL_CODE(HAX_DEVICE_TYPE, 0x90b, \ - METHOD_BUFFERED, FILE_ANY_AC= CESS) -#define HAX_VCPU_IOCTL_INTERRUPT CTL_CODE(HAX_DEVICE_TYPE, 0x90c, \ - METHOD_BUFFERED, FILE_ANY_AC= CESS) -#define HAX_VCPU_SET_REGS CTL_CODE(HAX_DEVICE_TYPE, 0x90d, \ - METHOD_BUFFERED, FILE_ANY_AC= CESS) -#define HAX_VCPU_GET_REGS CTL_CODE(HAX_DEVICE_TYPE, 0x90e, \ - METHOD_BUFFERED, FILE_ANY_AC= CESS) - -#define HAX_VM_IOCTL_NOTIFY_QEMU_VERSION CTL_CODE(HAX_DEVICE_TYPE, 0x910, \ - METHOD_BUFFERED, \ - FILE_ANY_ACCESS) -#endif /* TARGET_I386_HAX_WINDOWS_H */ diff --git a/accel/stubs/hax-stub.c b/accel/stubs/hax-stub.c deleted file mode 100644 index 2fe31aaa9a..0000000000 --- a/accel/stubs/hax-stub.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * QEMU HAXM support - * - * Copyright (c) 2015, Intel Corporation - * - * Copyright 2016 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * See the COPYING file in the top-level directory. - * - */ - -#include "qemu/osdep.h" -#include "sysemu/hax.h" - -bool hax_allowed; - -int hax_sync_vcpus(void) -{ - return 0; -} diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 4a34f03047..68ad30e2f5 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -28,7 +28,6 @@ #include "hw/intc/kvm_irqcount.h" #include "trace.h" #include "hw/boards.h" -#include "sysemu/hax.h" #include "sysemu/kvm.h" #include "hw/qdev-properties.h" #include "hw/sysbus.h" @@ -271,7 +270,7 @@ static void apic_common_realize(DeviceState *dev, Error= **errp) =20 /* Note: We need at least 1M to map the VAPIC option ROM */ if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK && - !hax_enabled() && current_machine->ram_size >=3D 1024 * 1024) { + current_machine->ram_size >=3D 1024 * 1024) { vapic =3D sysbus_create_simple("kvmvapic", -1, NULL); } s->vapic =3D vapic; diff --git a/softmmu/cpus.c b/softmmu/cpus.c index fed20ffb5d..0848e0dbdb 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -427,12 +427,6 @@ void qemu_wait_io_event(CPUState *cpu) qemu_plugin_vcpu_resume_cb(cpu); } =20 -#ifdef _WIN32 - /* Eat dummy APC queued by cpus_kick_thread. */ - if (hax_enabled()) { - SleepEx(0, TRUE); - } -#endif qemu_wait_io_event_common(cpu); } =20 diff --git a/softmmu/vl.c b/softmmu/vl.c index b0b96f67fa..5a10b3c309 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -86,7 +86,6 @@ #include "migration/colo.h" #include "migration/postcopy-ram.h" #include "sysemu/kvm.h" -#include "sysemu/hax.h" #include "qapi/qobject-input-visitor.h" #include "qemu/option.h" #include "qemu/config-file.h" @@ -2546,11 +2545,6 @@ static void qemu_init_board(void) drive_check_orphaned(); =20 realtime_init(); - - if (hax_enabled()) { - /* FIXME: why isn't cpu_synchronize_all_post_init enough? */ - hax_sync_vcpus(); - } } =20 static void qemu_create_cli_devices(void) diff --git a/target/i386/hax/hax-accel-ops.c b/target/i386/hax/hax-accel-op= s.c deleted file mode 100644 index 5031096760..0000000000 --- a/target/i386/hax/hax-accel-ops.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * QEMU HAX support - * - * Copyright IBM, Corp. 2008 - * Red Hat, Inc. 2008 - * - * Authors: - * Anthony Liguori - * Glauber Costa - * - * Copyright (c) 2011 Intel Corporation - * Written by: - * Jiang Yunhong - * Xin Xiaohui - * Zhang Xiantao - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - * - */ - -#include "qemu/osdep.h" -#include "qemu/error-report.h" -#include "qemu/main-loop.h" -#include "sysemu/runstate.h" -#include "sysemu/cpus.h" -#include "qemu/guest-random.h" - -#include "hax-accel-ops.h" - -static void *hax_cpu_thread_fn(void *arg) -{ - CPUState *cpu =3D arg; - int r; - - rcu_register_thread(); - qemu_mutex_lock_iothread(); - qemu_thread_get_self(cpu->thread); - - cpu->thread_id =3D qemu_get_thread_id(); - current_cpu =3D cpu; - hax_init_vcpu(cpu); - cpu_thread_signal_created(cpu); - qemu_guest_random_seed_thread_part2(cpu->random_seed); - - do { - if (cpu_can_run(cpu)) { - r =3D hax_smp_cpu_exec(cpu); - if (r =3D=3D EXCP_DEBUG) { - cpu_handle_guest_debug(cpu); - } - } - - qemu_wait_io_event(cpu); - } while (!cpu->unplug || cpu_can_run(cpu)); - hax_vcpu_destroy(cpu); - cpu_thread_signal_destroyed(cpu); - rcu_unregister_thread(); - return NULL; -} - -static void hax_start_vcpu_thread(CPUState *cpu) -{ - char thread_name[VCPU_THREAD_NAME_SIZE]; - - cpu->thread =3D g_new0(QemuThread, 1); - cpu->halt_cond =3D g_new0(QemuCond, 1); - qemu_cond_init(cpu->halt_cond); - - snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/HAX", - cpu->cpu_index); - qemu_thread_create(cpu->thread, thread_name, hax_cpu_thread_fn, - cpu, QEMU_THREAD_JOINABLE); - assert(cpu->accel); -#ifdef _WIN32 - cpu->accel->hThread =3D qemu_thread_get_handle(cpu->thread); -#endif -} - -static void hax_accel_ops_class_init(ObjectClass *oc, void *data) -{ - AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); - - ops->create_vcpu_thread =3D hax_start_vcpu_thread; - ops->kick_vcpu_thread =3D hax_kick_vcpu_thread; - - ops->synchronize_post_reset =3D hax_cpu_synchronize_post_reset; - ops->synchronize_post_init =3D hax_cpu_synchronize_post_init; - ops->synchronize_state =3D hax_cpu_synchronize_state; - ops->synchronize_pre_loadvm =3D hax_cpu_synchronize_pre_loadvm; -} - -static const TypeInfo hax_accel_ops_type =3D { - .name =3D ACCEL_OPS_NAME("hax"), - - .parent =3D TYPE_ACCEL_OPS, - .class_init =3D hax_accel_ops_class_init, - .abstract =3D true, -}; - -static void hax_accel_ops_register_types(void) -{ - type_register_static(&hax_accel_ops_type); -} -type_init(hax_accel_ops_register_types); diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c deleted file mode 100644 index 18d78e5b6b..0000000000 --- a/target/i386/hax/hax-all.c +++ /dev/null @@ -1,1141 +0,0 @@ -/* - * QEMU HAX support - * - * Copyright IBM, Corp. 2008 - * Red Hat, Inc. 2008 - * - * Authors: - * Anthony Liguori - * Glauber Costa - * - * Copyright (c) 2011 Intel Corporation - * Written by: - * Jiang Yunhong - * Xin Xiaohui - * Zhang Xiantao - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - * - */ - -/* - * HAX common code for both windows and darwin - */ - -#include "qemu/osdep.h" -#include "cpu.h" -#include "exec/address-spaces.h" - -#include "qemu/accel.h" -#include "sysemu/reset.h" -#include "sysemu/runstate.h" -#include "hw/boards.h" - -#include "hax-accel-ops.h" - -#define DEBUG_HAX 0 - -#define DPRINTF(fmt, ...) \ - do { \ - if (DEBUG_HAX) { \ - fprintf(stdout, fmt, ## __VA_ARGS__); \ - } \ - } while (0) - -/* Current version */ -const uint32_t hax_cur_version =3D 0x4; /* API v4: unmapping and MMIO move= s */ -/* Minimum HAX kernel version */ -const uint32_t hax_min_version =3D 0x4; /* API v4: supports unmapping */ - -bool hax_allowed; - -struct hax_state hax_global; - -static void hax_vcpu_sync_state(CPUArchState *env, int modified); -static int hax_arch_get_registers(CPUArchState *env); - -int valid_hax_tunnel_size(uint16_t size) -{ - return size >=3D sizeof(struct hax_tunnel); -} - -hax_fd hax_vcpu_get_fd(CPUArchState *env) -{ - AccelCPUState *vcpu =3D env_cpu(env)->accel; - if (!vcpu) { - return HAX_INVALID_FD; - } - return vcpu->fd; -} - -static int hax_get_capability(struct hax_state *hax) -{ - int ret; - struct hax_capabilityinfo capinfo, *cap =3D &capinfo; - - ret =3D hax_capability(hax, cap); - if (ret) { - return ret; - } - - if ((cap->wstatus & HAX_CAP_WORKSTATUS_MASK) =3D=3D HAX_CAP_STATUS_NOT= WORKING) { - if (cap->winfo & HAX_CAP_FAILREASON_VT) { - DPRINTF - ("VTX feature is not enabled, HAX driver will not work.\n"= ); - } else if (cap->winfo & HAX_CAP_FAILREASON_NX) { - DPRINTF - ("NX feature is not enabled, HAX driver will not work.\n"); - } - return -ENXIO; - - } - - if (!(cap->winfo & HAX_CAP_UG)) { - fprintf(stderr, "UG mode is not supported by the hardware.\n"); - return -ENOTSUP; - } - - hax->supports_64bit_ramblock =3D !!(cap->winfo & HAX_CAP_64BIT_RAMBLOC= K); - - if (cap->wstatus & HAX_CAP_MEMQUOTA) { - if (cap->mem_quota < hax->mem_quota) { - fprintf(stderr, "The VM memory needed exceeds the driver limit= .\n"); - return -ENOSPC; - } - } - return 0; -} - -static int hax_version_support(struct hax_state *hax) -{ - int ret; - struct hax_module_version version; - - ret =3D hax_mod_version(hax, &version); - if (ret < 0) { - return 0; - } - - if (hax_min_version > version.cur_version) { - fprintf(stderr, "Incompatible HAX module version %d,", - version.cur_version); - fprintf(stderr, "requires minimum version %d\n", hax_min_version); - return 0; - } - if (hax_cur_version < version.compat_version) { - fprintf(stderr, "Incompatible QEMU HAX API version %x,", - hax_cur_version); - fprintf(stderr, "requires minimum HAX API version %x\n", - version.compat_version); - return 0; - } - - return 1; -} - -int hax_vcpu_create(int id) -{ - AccelCPUState *vcpu =3D NULL; - int ret; - - if (!hax_global.vm) { - fprintf(stderr, "vcpu %x created failed, vm is null\n", id); - return -1; - } - - if (hax_global.vm->vcpus[id]) { - fprintf(stderr, "vcpu %x allocated already\n", id); - return 0; - } - - vcpu =3D g_new0(AccelCPUState, 1); - - ret =3D hax_host_create_vcpu(hax_global.vm->fd, id); - if (ret) { - fprintf(stderr, "Failed to create vcpu %x\n", id); - goto error; - } - - vcpu->vcpu_id =3D id; - vcpu->fd =3D hax_host_open_vcpu(hax_global.vm->id, id); - if (hax_invalid_fd(vcpu->fd)) { - fprintf(stderr, "Failed to open the vcpu\n"); - ret =3D -ENODEV; - goto error; - } - - hax_global.vm->vcpus[id] =3D vcpu; - - ret =3D hax_host_setup_vcpu_channel(vcpu); - if (ret) { - fprintf(stderr, "Invalid hax tunnel size\n"); - ret =3D -EINVAL; - goto error; - } - return 0; - - error: - /* vcpu and tunnel will be closed automatically */ - if (vcpu && !hax_invalid_fd(vcpu->fd)) { - hax_close_fd(vcpu->fd); - } - - hax_global.vm->vcpus[id] =3D NULL; - g_free(vcpu); - return -1; -} - -int hax_vcpu_destroy(CPUState *cpu) -{ - AccelCPUState *vcpu =3D cpu->accel; - - if (!hax_global.vm) { - fprintf(stderr, "vcpu %x destroy failed, vm is null\n", vcpu->vcpu= _id); - return -1; - } - - if (!vcpu) { - return 0; - } - - /* - * 1. The hax_tunnel is also destroyed when vcpu is destroyed - * 2. close fd will cause hax module vcpu be cleaned - */ - hax_close_fd(vcpu->fd); - hax_global.vm->vcpus[vcpu->vcpu_id] =3D NULL; -#ifdef _WIN32 - CloseHandle(vcpu->hThread); -#endif - g_free(vcpu); - cpu->accel =3D NULL; - return 0; -} - -int hax_init_vcpu(CPUState *cpu) -{ - int ret; - - ret =3D hax_vcpu_create(cpu->cpu_index); - if (ret < 0) { - fprintf(stderr, "Failed to create HAX vcpu\n"); - exit(-1); - } - - cpu->accel =3D hax_global.vm->vcpus[cpu->cpu_index]; - cpu->vcpu_dirty =3D true; - qemu_register_reset(hax_reset_vcpu_state, cpu->env_ptr); - - return ret; -} - -struct hax_vm *hax_vm_create(struct hax_state *hax, int max_cpus) -{ - struct hax_vm *vm; - int vm_id =3D 0, ret, i; - - if (hax_invalid_fd(hax->fd)) { - return NULL; - } - - if (hax->vm) { - return hax->vm; - } - - if (max_cpus > HAX_MAX_VCPU) { - fprintf(stderr, "Maximum VCPU number QEMU supported is %d\n", HAX_= MAX_VCPU); - return NULL; - } - - vm =3D g_new0(struct hax_vm, 1); - - ret =3D hax_host_create_vm(hax, &vm_id); - if (ret) { - fprintf(stderr, "Failed to create vm %x\n", ret); - goto error; - } - vm->id =3D vm_id; - vm->fd =3D hax_host_open_vm(hax, vm_id); - if (hax_invalid_fd(vm->fd)) { - fprintf(stderr, "Failed to open vm %d\n", vm_id); - goto error; - } - - vm->numvcpus =3D max_cpus; - vm->vcpus =3D g_new0(AccelCPUState *, vm->numvcpus); - for (i =3D 0; i < vm->numvcpus; i++) { - vm->vcpus[i] =3D NULL; - } - - hax->vm =3D vm; - return vm; - - error: - g_free(vm); - hax->vm =3D NULL; - return NULL; -} - -int hax_vm_destroy(struct hax_vm *vm) -{ - int i; - - for (i =3D 0; i < vm->numvcpus; i++) - if (vm->vcpus[i]) { - fprintf(stderr, "VCPU should be cleaned before vm clean\n"); - return -1; - } - hax_close_fd(vm->fd); - vm->numvcpus =3D 0; - g_free(vm->vcpus); - g_free(vm); - hax_global.vm =3D NULL; - return 0; -} - -static int hax_init(ram_addr_t ram_size, int max_cpus) -{ - struct hax_state *hax =3D NULL; - struct hax_qemu_version qversion; - int ret; - - hax =3D &hax_global; - - memset(hax, 0, sizeof(struct hax_state)); - hax->mem_quota =3D ram_size; - - hax->fd =3D hax_mod_open(); - if (hax_invalid_fd(hax->fd)) { - hax->fd =3D 0; - ret =3D -ENODEV; - goto error; - } - - ret =3D hax_get_capability(hax); - - if (ret) { - if (ret !=3D -ENOSPC) { - ret =3D -EINVAL; - } - goto error; - } - - if (!hax_version_support(hax)) { - ret =3D -EINVAL; - goto error; - } - - hax->vm =3D hax_vm_create(hax, max_cpus); - if (!hax->vm) { - fprintf(stderr, "Failed to create HAX VM\n"); - ret =3D -EINVAL; - goto error; - } - - hax_memory_init(); - - qversion.cur_version =3D hax_cur_version; - qversion.min_version =3D hax_min_version; - hax_notify_qemu_version(hax->vm->fd, &qversion); - - return ret; - error: - if (hax->vm) { - hax_vm_destroy(hax->vm); - } - if (hax->fd) { - hax_mod_close(hax); - } - - return ret; -} - -static int hax_accel_init(MachineState *ms) -{ - int ret =3D hax_init(ms->ram_size, (int)ms->smp.max_cpus); - - if (ret && (ret !=3D -ENOSPC)) { - fprintf(stderr, "No accelerator found.\n"); - } else { - fprintf(stdout, "HAX is %s and emulator runs in %s mode.\n", - !ret ? "working" : "not working", - !ret ? "fast virt" : "emulation"); - fprintf(stdout, - "NOTE: HAX is deprecated and will be removed in a future r= elease.\n" - " Use 'whpx' (on Windows) or 'hvf' (on macOS) instead= .\n"); - } - return ret; -} - -static int hax_handle_fastmmio(CPUArchState *env, struct hax_fastmmio *hft) -{ - if (hft->direction < 2) { - cpu_physical_memory_rw(hft->gpa, &hft->value, hft->size, - hft->direction); - } else { - /* - * HAX API v4 supports transferring data between two MMIO addresse= s, - * hft->gpa and hft->gpa2 (instructions such as MOVS require this): - * hft->direction =3D=3D 2: gpa =3D=3D> gpa2 - */ - uint64_t value; - cpu_physical_memory_read(hft->gpa, &value, hft->size); - cpu_physical_memory_write(hft->gpa2, &value, hft->size); - } - - return 0; -} - -static int hax_handle_io(CPUArchState *env, uint32_t df, uint16_t port, - int direction, int size, int count, void *buffer) -{ - uint8_t *ptr; - int i; - MemTxAttrs attrs =3D { 0 }; - - if (!df) { - ptr =3D buffer; - } else { - ptr =3D buffer + size * count - size; - } - for (i =3D 0; i < count; i++) { - address_space_rw(&address_space_io, port, attrs, - ptr, size, direction =3D=3D HAX_EXIT_IO_OUT); - if (!df) { - ptr +=3D size; - } else { - ptr -=3D size; - } - } - - return 0; -} - -static int hax_vcpu_interrupt(CPUArchState *env) -{ - CPUState *cpu =3D env_cpu(env); - AccelCPUState *vcpu =3D cpu->accel; - struct hax_tunnel *ht =3D vcpu->tunnel; - - /* - * Try to inject an interrupt if the guest can accept it - * Unlike KVM, HAX kernel check for the eflags, instead of qemu - */ - if (ht->ready_for_interrupt_injection && - (cpu->interrupt_request & CPU_INTERRUPT_HARD)) { - int irq; - - irq =3D cpu_get_pic_interrupt(env); - if (irq >=3D 0) { - hax_inject_interrupt(env, irq); - cpu->interrupt_request &=3D ~CPU_INTERRUPT_HARD; - } - } - - /* If we have an interrupt but the guest is not ready to receive an - * interrupt, request an interrupt window exit. This will - * cause a return to userspace as soon as the guest is ready to - * receive interrupts. */ - if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) { - ht->request_interrupt_window =3D 1; - } else { - ht->request_interrupt_window =3D 0; - } - return 0; -} - -void hax_raise_event(CPUState *cpu) -{ - AccelCPUState *vcpu =3D cpu->accel; - - if (!vcpu) { - return; - } - vcpu->tunnel->user_event_pending =3D 1; -} - -/* - * Ask hax kernel module to run the CPU for us till: - * 1. Guest crash or shutdown - * 2. Need QEMU's emulation like guest execute MMIO instruction - * 3. Guest execute HLT - * 4. QEMU have Signal/event pending - * 5. An unknown VMX exit happens - */ -static int hax_vcpu_hax_exec(CPUArchState *env) -{ - int ret =3D 0; - CPUState *cpu =3D env_cpu(env); - X86CPU *x86_cpu =3D X86_CPU(cpu); - AccelCPUState *vcpu =3D cpu->accel; - struct hax_tunnel *ht =3D vcpu->tunnel; - - if (!hax_enabled()) { - DPRINTF("Trying to vcpu execute at eip:" TARGET_FMT_lx "\n", env->= eip); - return 0; - } - - if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { - cpu->interrupt_request &=3D ~CPU_INTERRUPT_POLL; - apic_poll_irq(x86_cpu->apic_state); - } - - /* After a vcpu is halted (either because it is an AP and has just been - * reset, or because it has executed the HLT instruction), it will not= be - * run (hax_vcpu_run()) until it is unhalted. The next few if blocks c= heck - * for events that may change the halted state of this vcpu: - * a) Maskable interrupt, when RFLAGS.IF is 1; - * Note: env->eflags may not reflect the current RFLAGS state, bec= ause - * it is not updated after each hax_vcpu_run(). We cannot af= ford - * to fail to recognize any unhalt-by-maskable-interrupt eve= nt - * (in which case the vcpu will halt forever), and yet we ca= nnot - * afford the overhead of hax_vcpu_sync_state(). The current - * solution is to err on the side of caution and have the HLT - * handler (see case HAX_EXIT_HLT below) unconditionally set= the - * IF_MASK bit in env->eflags, which, in effect, disables the - * RFLAGS.IF check. - * b) NMI; - * c) INIT signal; - * d) SIPI signal. - */ - if (((cpu->interrupt_request & CPU_INTERRUPT_HARD) && - (env->eflags & IF_MASK)) || - (cpu->interrupt_request & CPU_INTERRUPT_NMI)) { - cpu->halted =3D 0; - } - - if (cpu->interrupt_request & CPU_INTERRUPT_INIT) { - DPRINTF("\nhax_vcpu_hax_exec: handling INIT for %d\n", - cpu->cpu_index); - do_cpu_init(x86_cpu); - hax_vcpu_sync_state(env, 1); - } - - if (cpu->interrupt_request & CPU_INTERRUPT_SIPI) { - DPRINTF("hax_vcpu_hax_exec: handling SIPI for %d\n", - cpu->cpu_index); - hax_vcpu_sync_state(env, 0); - do_cpu_sipi(x86_cpu); - hax_vcpu_sync_state(env, 1); - } - - if (cpu->halted) { - /* If this vcpu is halted, we must not ask HAXM to run it. Instead= , we - * break out of hax_smp_cpu_exec() as if this vcpu had executed HL= T. - * That way, this vcpu thread will be trapped in qemu_wait_io_even= t(), - * until the vcpu is unhalted. - */ - cpu->exception_index =3D EXCP_HLT; - return 0; - } - - do { - int hax_ret; - - if (cpu->exit_request) { - ret =3D 1; - break; - } - - hax_vcpu_interrupt(env); - - qemu_mutex_unlock_iothread(); - cpu_exec_start(cpu); - hax_ret =3D hax_vcpu_run(vcpu); - cpu_exec_end(cpu); - qemu_mutex_lock_iothread(); - - /* Simply continue the vcpu_run if system call interrupted */ - if (hax_ret =3D=3D -EINTR || hax_ret =3D=3D -EAGAIN) { - DPRINTF("io window interrupted\n"); - continue; - } - - if (hax_ret < 0) { - fprintf(stderr, "vcpu run failed for vcpu %x\n", vcpu->vcpu_i= d); - abort(); - } - switch (ht->_exit_status) { - case HAX_EXIT_IO: - ret =3D hax_handle_io(env, ht->pio._df, ht->pio._port, - ht->pio._direction, - ht->pio._size, ht->pio._count, vcpu->iobuf); - break; - case HAX_EXIT_FAST_MMIO: - ret =3D hax_handle_fastmmio(env, (struct hax_fastmmio *) vcpu-= >iobuf); - break; - /* Guest state changed, currently only for shutdown */ - case HAX_EXIT_STATECHANGE: - fprintf(stdout, "VCPU shutdown request\n"); - qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); - hax_vcpu_sync_state(env, 0); - ret =3D 1; - break; - case HAX_EXIT_UNKNOWN_VMEXIT: - fprintf(stderr, "Unknown VMX exit %x from guest\n", - ht->_exit_reason); - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); - hax_vcpu_sync_state(env, 0); - cpu_dump_state(cpu, stderr, 0); - ret =3D -1; - break; - case HAX_EXIT_HLT: - if (!(cpu->interrupt_request & CPU_INTERRUPT_HARD) && - !(cpu->interrupt_request & CPU_INTERRUPT_NMI)) { - /* hlt instruction with interrupt disabled is shutdown */ - env->eflags |=3D IF_MASK; - cpu->halted =3D 1; - cpu->exception_index =3D EXCP_HLT; - ret =3D 1; - } - break; - /* these situations will continue to hax module */ - case HAX_EXIT_INTERRUPT: - case HAX_EXIT_PAUSED: - break; - case HAX_EXIT_MMIO: - /* Should not happen on UG system */ - fprintf(stderr, "HAX: unsupported MMIO emulation\n"); - ret =3D -1; - break; - case HAX_EXIT_REAL: - /* Should not happen on UG system */ - fprintf(stderr, "HAX: unimplemented real mode emulation\n"); - ret =3D -1; - break; - default: - fprintf(stderr, "Unknown exit %x from HAX\n", ht->_exit_status= ); - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); - hax_vcpu_sync_state(env, 0); - cpu_dump_state(cpu, stderr, 0); - ret =3D 1; - break; - } - } while (!ret); - - if (cpu->exit_request) { - cpu->exit_request =3D 0; - cpu->exception_index =3D EXCP_INTERRUPT; - } - return ret < 0; -} - -static void do_hax_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data ar= g) -{ - CPUArchState *env =3D cpu->env_ptr; - - hax_arch_get_registers(env); - cpu->vcpu_dirty =3D true; -} - -void hax_cpu_synchronize_state(CPUState *cpu) -{ - if (!cpu->vcpu_dirty) { - run_on_cpu(cpu, do_hax_cpu_synchronize_state, RUN_ON_CPU_NULL); - } -} - -static void do_hax_cpu_synchronize_post_reset(CPUState *cpu, - run_on_cpu_data arg) -{ - CPUArchState *env =3D cpu->env_ptr; - - hax_vcpu_sync_state(env, 1); - cpu->vcpu_dirty =3D false; -} - -void hax_cpu_synchronize_post_reset(CPUState *cpu) -{ - run_on_cpu(cpu, do_hax_cpu_synchronize_post_reset, RUN_ON_CPU_NULL); -} - -static void do_hax_cpu_synchronize_post_init(CPUState *cpu, run_on_cpu_dat= a arg) -{ - CPUArchState *env =3D cpu->env_ptr; - - hax_vcpu_sync_state(env, 1); - cpu->vcpu_dirty =3D false; -} - -void hax_cpu_synchronize_post_init(CPUState *cpu) -{ - run_on_cpu(cpu, do_hax_cpu_synchronize_post_init, RUN_ON_CPU_NULL); -} - -static void do_hax_cpu_synchronize_pre_loadvm(CPUState *cpu, run_on_cpu_da= ta arg) -{ - cpu->vcpu_dirty =3D true; -} - -void hax_cpu_synchronize_pre_loadvm(CPUState *cpu) -{ - run_on_cpu(cpu, do_hax_cpu_synchronize_pre_loadvm, RUN_ON_CPU_NULL); -} - -int hax_smp_cpu_exec(CPUState *cpu) -{ - CPUArchState *env =3D cpu->env_ptr; - int fatal; - int ret; - - while (1) { - if (cpu->exception_index >=3D EXCP_INTERRUPT) { - ret =3D cpu->exception_index; - cpu->exception_index =3D -1; - break; - } - - fatal =3D hax_vcpu_hax_exec(env); - - if (fatal) { - fprintf(stderr, "Unsupported HAX vcpu return\n"); - abort(); - } - } - - return ret; -} - -static void set_v8086_seg(struct segment_desc_t *lhs, const SegmentCache *= rhs) -{ - memset(lhs, 0, sizeof(struct segment_desc_t)); - lhs->selector =3D rhs->selector; - lhs->base =3D rhs->base; - lhs->limit =3D rhs->limit; - lhs->type =3D 3; - lhs->present =3D 1; - lhs->dpl =3D 3; - lhs->operand_size =3D 0; - lhs->desc =3D 1; - lhs->long_mode =3D 0; - lhs->granularity =3D 0; - lhs->available =3D 0; -} - -static void get_seg(SegmentCache *lhs, const struct segment_desc_t *rhs) -{ - lhs->selector =3D rhs->selector; - lhs->base =3D rhs->base; - lhs->limit =3D rhs->limit; - lhs->flags =3D (rhs->type << DESC_TYPE_SHIFT) - | (rhs->present * DESC_P_MASK) - | (rhs->dpl << DESC_DPL_SHIFT) - | (rhs->operand_size << DESC_B_SHIFT) - | (rhs->desc * DESC_S_MASK) - | (rhs->long_mode << DESC_L_SHIFT) - | (rhs->granularity * DESC_G_MASK) | (rhs->available * DESC_AVL_MA= SK); -} - -static void set_seg(struct segment_desc_t *lhs, const SegmentCache *rhs) -{ - unsigned flags =3D rhs->flags; - - memset(lhs, 0, sizeof(struct segment_desc_t)); - lhs->selector =3D rhs->selector; - lhs->base =3D rhs->base; - lhs->limit =3D rhs->limit; - lhs->type =3D (flags >> DESC_TYPE_SHIFT) & 15; - lhs->present =3D (flags & DESC_P_MASK) !=3D 0; - lhs->dpl =3D rhs->selector & 3; - lhs->operand_size =3D (flags >> DESC_B_SHIFT) & 1; - lhs->desc =3D (flags & DESC_S_MASK) !=3D 0; - lhs->long_mode =3D (flags >> DESC_L_SHIFT) & 1; - lhs->granularity =3D (flags & DESC_G_MASK) !=3D 0; - lhs->available =3D (flags & DESC_AVL_MASK) !=3D 0; -} - -static void hax_getput_reg(uint64_t *hax_reg, target_ulong *qemu_reg, int = set) -{ - target_ulong reg =3D *hax_reg; - - if (set) { - *hax_reg =3D *qemu_reg; - } else { - *qemu_reg =3D reg; - } -} - -/* The sregs has been synced with HAX kernel already before this call */ -static int hax_get_segments(CPUArchState *env, struct vcpu_state_t *sregs) -{ - get_seg(&env->segs[R_CS], &sregs->_cs); - get_seg(&env->segs[R_DS], &sregs->_ds); - get_seg(&env->segs[R_ES], &sregs->_es); - get_seg(&env->segs[R_FS], &sregs->_fs); - get_seg(&env->segs[R_GS], &sregs->_gs); - get_seg(&env->segs[R_SS], &sregs->_ss); - - get_seg(&env->tr, &sregs->_tr); - get_seg(&env->ldt, &sregs->_ldt); - env->idt.limit =3D sregs->_idt.limit; - env->idt.base =3D sregs->_idt.base; - env->gdt.limit =3D sregs->_gdt.limit; - env->gdt.base =3D sregs->_gdt.base; - return 0; -} - -static int hax_set_segments(CPUArchState *env, struct vcpu_state_t *sregs) -{ - if ((env->eflags & VM_MASK)) { - set_v8086_seg(&sregs->_cs, &env->segs[R_CS]); - set_v8086_seg(&sregs->_ds, &env->segs[R_DS]); - set_v8086_seg(&sregs->_es, &env->segs[R_ES]); - set_v8086_seg(&sregs->_fs, &env->segs[R_FS]); - set_v8086_seg(&sregs->_gs, &env->segs[R_GS]); - set_v8086_seg(&sregs->_ss, &env->segs[R_SS]); - } else { - set_seg(&sregs->_cs, &env->segs[R_CS]); - set_seg(&sregs->_ds, &env->segs[R_DS]); - set_seg(&sregs->_es, &env->segs[R_ES]); - set_seg(&sregs->_fs, &env->segs[R_FS]); - set_seg(&sregs->_gs, &env->segs[R_GS]); - set_seg(&sregs->_ss, &env->segs[R_SS]); - - if (env->cr[0] & CR0_PE_MASK) { - /* force ss cpl to cs cpl */ - sregs->_ss.selector =3D (sregs->_ss.selector & ~3) | - (sregs->_cs.selector & 3); - sregs->_ss.dpl =3D sregs->_ss.selector & 3; - } - } - - set_seg(&sregs->_tr, &env->tr); - set_seg(&sregs->_ldt, &env->ldt); - sregs->_idt.limit =3D env->idt.limit; - sregs->_idt.base =3D env->idt.base; - sregs->_gdt.limit =3D env->gdt.limit; - sregs->_gdt.base =3D env->gdt.base; - return 0; -} - -static int hax_sync_vcpu_register(CPUArchState *env, int set) -{ - struct vcpu_state_t regs; - int ret; - memset(®s, 0, sizeof(struct vcpu_state_t)); - - if (!set) { - ret =3D hax_sync_vcpu_state(env, ®s, 0); - if (ret < 0) { - return -1; - } - } - - /* generic register */ - hax_getput_reg(®s._rax, &env->regs[R_EAX], set); - hax_getput_reg(®s._rbx, &env->regs[R_EBX], set); - hax_getput_reg(®s._rcx, &env->regs[R_ECX], set); - hax_getput_reg(®s._rdx, &env->regs[R_EDX], set); - hax_getput_reg(®s._rsi, &env->regs[R_ESI], set); - hax_getput_reg(®s._rdi, &env->regs[R_EDI], set); - hax_getput_reg(®s._rsp, &env->regs[R_ESP], set); - hax_getput_reg(®s._rbp, &env->regs[R_EBP], set); -#ifdef TARGET_X86_64 - hax_getput_reg(®s._r8, &env->regs[8], set); - hax_getput_reg(®s._r9, &env->regs[9], set); - hax_getput_reg(®s._r10, &env->regs[10], set); - hax_getput_reg(®s._r11, &env->regs[11], set); - hax_getput_reg(®s._r12, &env->regs[12], set); - hax_getput_reg(®s._r13, &env->regs[13], set); - hax_getput_reg(®s._r14, &env->regs[14], set); - hax_getput_reg(®s._r15, &env->regs[15], set); -#endif - hax_getput_reg(®s._rflags, &env->eflags, set); - hax_getput_reg(®s._rip, &env->eip, set); - - if (set) { - regs._cr0 =3D env->cr[0]; - regs._cr2 =3D env->cr[2]; - regs._cr3 =3D env->cr[3]; - regs._cr4 =3D env->cr[4]; - hax_set_segments(env, ®s); - } else { - env->cr[0] =3D regs._cr0; - env->cr[2] =3D regs._cr2; - env->cr[3] =3D regs._cr3; - env->cr[4] =3D regs._cr4; - hax_get_segments(env, ®s); - } - - if (set) { - ret =3D hax_sync_vcpu_state(env, ®s, 1); - if (ret < 0) { - return -1; - } - } - return 0; -} - -static void hax_msr_entry_set(struct vmx_msr *item, uint32_t index, - uint64_t value) -{ - item->entry =3D index; - item->value =3D value; -} - -static int hax_get_msrs(CPUArchState *env) -{ - struct hax_msr_data md; - struct vmx_msr *msrs =3D md.entries; - int ret, i, n; - - n =3D 0; - msrs[n++].entry =3D MSR_IA32_SYSENTER_CS; - msrs[n++].entry =3D MSR_IA32_SYSENTER_ESP; - msrs[n++].entry =3D MSR_IA32_SYSENTER_EIP; - msrs[n++].entry =3D MSR_IA32_TSC; -#ifdef TARGET_X86_64 - msrs[n++].entry =3D MSR_EFER; - msrs[n++].entry =3D MSR_STAR; - msrs[n++].entry =3D MSR_LSTAR; - msrs[n++].entry =3D MSR_CSTAR; - msrs[n++].entry =3D MSR_FMASK; - msrs[n++].entry =3D MSR_KERNELGSBASE; -#endif - md.nr_msr =3D n; - ret =3D hax_sync_msr(env, &md, 0); - if (ret < 0) { - return ret; - } - - for (i =3D 0; i < md.done; i++) { - switch (msrs[i].entry) { - case MSR_IA32_SYSENTER_CS: - env->sysenter_cs =3D msrs[i].value; - break; - case MSR_IA32_SYSENTER_ESP: - env->sysenter_esp =3D msrs[i].value; - break; - case MSR_IA32_SYSENTER_EIP: - env->sysenter_eip =3D msrs[i].value; - break; - case MSR_IA32_TSC: - env->tsc =3D msrs[i].value; - break; -#ifdef TARGET_X86_64 - case MSR_EFER: - env->efer =3D msrs[i].value; - break; - case MSR_STAR: - env->star =3D msrs[i].value; - break; - case MSR_LSTAR: - env->lstar =3D msrs[i].value; - break; - case MSR_CSTAR: - env->cstar =3D msrs[i].value; - break; - case MSR_FMASK: - env->fmask =3D msrs[i].value; - break; - case MSR_KERNELGSBASE: - env->kernelgsbase =3D msrs[i].value; - break; -#endif - } - } - - return 0; -} - -static int hax_set_msrs(CPUArchState *env) -{ - struct hax_msr_data md; - struct vmx_msr *msrs; - msrs =3D md.entries; - int n =3D 0; - - memset(&md, 0, sizeof(struct hax_msr_data)); - hax_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); - hax_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp= ); - hax_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip= ); - hax_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); -#ifdef TARGET_X86_64 - hax_msr_entry_set(&msrs[n++], MSR_EFER, env->efer); - hax_msr_entry_set(&msrs[n++], MSR_STAR, env->star); - hax_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); - hax_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); - hax_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); - hax_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); -#endif - md.nr_msr =3D n; - md.done =3D 0; - - return hax_sync_msr(env, &md, 1); -} - -static int hax_get_fpu(CPUArchState *env) -{ - struct fx_layout fpu; - int i, ret; - - ret =3D hax_sync_fpu(env, &fpu, 0); - if (ret < 0) { - return ret; - } - - env->fpstt =3D (fpu.fsw >> 11) & 7; - env->fpus =3D fpu.fsw; - env->fpuc =3D fpu.fcw; - for (i =3D 0; i < 8; ++i) { - env->fptags[i] =3D !((fpu.ftw >> i) & 1); - } - memcpy(env->fpregs, fpu.st_mm, sizeof(env->fpregs)); - - for (i =3D 0; i < 8; i++) { - env->xmm_regs[i].ZMM_Q(0) =3D ldq_p(&fpu.mmx_1[i][0]); - env->xmm_regs[i].ZMM_Q(1) =3D ldq_p(&fpu.mmx_1[i][8]); - if (CPU_NB_REGS > 8) { - env->xmm_regs[i + 8].ZMM_Q(0) =3D ldq_p(&fpu.mmx_2[i][0]); - env->xmm_regs[i + 8].ZMM_Q(1) =3D ldq_p(&fpu.mmx_2[i][8]); - } - } - env->mxcsr =3D fpu.mxcsr; - - return 0; -} - -static int hax_set_fpu(CPUArchState *env) -{ - struct fx_layout fpu; - int i; - - memset(&fpu, 0, sizeof(fpu)); - fpu.fsw =3D env->fpus & ~(7 << 11); - fpu.fsw |=3D (env->fpstt & 7) << 11; - fpu.fcw =3D env->fpuc; - - for (i =3D 0; i < 8; ++i) { - fpu.ftw |=3D (!env->fptags[i]) << i; - } - - memcpy(fpu.st_mm, env->fpregs, sizeof(env->fpregs)); - for (i =3D 0; i < 8; i++) { - stq_p(&fpu.mmx_1[i][0], env->xmm_regs[i].ZMM_Q(0)); - stq_p(&fpu.mmx_1[i][8], env->xmm_regs[i].ZMM_Q(1)); - if (CPU_NB_REGS > 8) { - stq_p(&fpu.mmx_2[i][0], env->xmm_regs[i + 8].ZMM_Q(0)); - stq_p(&fpu.mmx_2[i][8], env->xmm_regs[i + 8].ZMM_Q(1)); - } - } - - fpu.mxcsr =3D env->mxcsr; - - return hax_sync_fpu(env, &fpu, 1); -} - -static int hax_arch_get_registers(CPUArchState *env) -{ - int ret; - - ret =3D hax_sync_vcpu_register(env, 0); - if (ret < 0) { - return ret; - } - - ret =3D hax_get_fpu(env); - if (ret < 0) { - return ret; - } - - ret =3D hax_get_msrs(env); - if (ret < 0) { - return ret; - } - - x86_update_hflags(env); - return 0; -} - -static int hax_arch_set_registers(CPUArchState *env) -{ - int ret; - ret =3D hax_sync_vcpu_register(env, 1); - - if (ret < 0) { - fprintf(stderr, "Failed to sync vcpu reg\n"); - return ret; - } - ret =3D hax_set_fpu(env); - if (ret < 0) { - fprintf(stderr, "FPU failed\n"); - return ret; - } - ret =3D hax_set_msrs(env); - if (ret < 0) { - fprintf(stderr, "MSR failed\n"); - return ret; - } - - return 0; -} - -static void hax_vcpu_sync_state(CPUArchState *env, int modified) -{ - if (hax_enabled()) { - if (modified) { - hax_arch_set_registers(env); - } else { - hax_arch_get_registers(env); - } - } -} - -/* - * much simpler than kvm, at least in first stage because: - * We don't need consider the device pass-through, we don't need - * consider the framebuffer, and we may even remove the bios at all - */ -int hax_sync_vcpus(void) -{ - if (hax_enabled()) { - CPUState *cpu; - - cpu =3D first_cpu; - if (!cpu) { - return 0; - } - - for (; cpu !=3D NULL; cpu =3D CPU_NEXT(cpu)) { - int ret; - - ret =3D hax_arch_set_registers(cpu->env_ptr); - if (ret < 0) { - return ret; - } - } - } - - return 0; -} - -void hax_reset_vcpu_state(void *opaque) -{ - CPUState *cpu; - for (cpu =3D first_cpu; cpu !=3D NULL; cpu =3D CPU_NEXT(cpu)) { - cpu->accel->tunnel->user_event_pending =3D 0; - cpu->accel->tunnel->ready_for_interrupt_injection =3D 0; - } -} - -static void hax_accel_class_init(ObjectClass *oc, void *data) -{ - AccelClass *ac =3D ACCEL_CLASS(oc); - ac->name =3D "HAX"; - ac->init_machine =3D hax_accel_init; - ac->allowed =3D &hax_allowed; -} - -static const TypeInfo hax_accel_type =3D { - .name =3D ACCEL_CLASS_NAME("hax"), - .parent =3D TYPE_ACCEL, - .class_init =3D hax_accel_class_init, -}; - -static void hax_type_init(void) -{ - type_register_static(&hax_accel_type); -} - -type_init(hax_type_init); diff --git a/target/i386/hax/hax-mem.c b/target/i386/hax/hax-mem.c deleted file mode 100644 index bb5ffbc9ac..0000000000 --- a/target/i386/hax/hax-mem.c +++ /dev/null @@ -1,323 +0,0 @@ -/* - * HAX memory mapping operations - * - * Copyright (c) 2015-16 Intel Corporation - * Copyright 2016 Google, Inc. - * - * This work is licensed under the terms of the GNU GPL, version 2. See - * the COPYING file in the top-level directory. - */ - -#include "qemu/osdep.h" -#include "cpu.h" -#include "exec/address-spaces.h" -#include "qemu/error-report.h" - -#include "hax-accel-ops.h" -#include "qemu/queue.h" - -#define DEBUG_HAX_MEM 0 - -#define DPRINTF(fmt, ...) \ - do { \ - if (DEBUG_HAX_MEM) { \ - fprintf(stdout, fmt, ## __VA_ARGS__); \ - } \ - } while (0) - -/** - * HAXMapping: describes a pending guest physical memory mapping - * - * @start_pa: a guest physical address marking the start of the region; mu= st be - * page-aligned - * @size: a guest physical address marking the end of the region; must be - * page-aligned - * @host_va: the host virtual address of the start of the mapping - * @flags: mapping parameters e.g. HAX_RAM_INFO_ROM or HAX_RAM_INFO_INVALID - * @entry: additional fields for linking #HAXMapping instances together - */ -typedef struct HAXMapping { - uint64_t start_pa; - uint32_t size; - uint64_t host_va; - int flags; - QTAILQ_ENTRY(HAXMapping) entry; -} HAXMapping; - -/* - * A doubly-linked list (actually a tail queue) of the pending page mappin= gs - * for the ongoing memory transaction. - * - * It is used to optimize the number of page mapping updates done through = the - * kernel module. For example, it's effective when a driver is digging an = MMIO - * hole inside an existing memory mapping. It will get a deletion of the w= hole - * region, then the addition of the 2 remaining RAM areas around the hole = and - * finally the memory transaction commit. During the commit, it will effec= tively - * send to the kernel only the removal of the pages from the MMIO hole aft= er - * having computed locally the result of the deletion and additions. - */ -static QTAILQ_HEAD(, HAXMapping) mappings =3D - QTAILQ_HEAD_INITIALIZER(mappings); - -/** - * hax_mapping_dump_list: dumps @mappings to stdout (for debugging) - */ -static void hax_mapping_dump_list(void) -{ - HAXMapping *entry; - - DPRINTF("%s updates:\n", __func__); - QTAILQ_FOREACH(entry, &mappings, entry) { - DPRINTF("\t%c 0x%016" PRIx64 "->0x%016" PRIx64 " VA 0x%016" PRIx64 - "%s\n", entry->flags & HAX_RAM_INFO_INVALID ? '-' : '+', - entry->start_pa, entry->start_pa + entry->size, entry->hos= t_va, - entry->flags & HAX_RAM_INFO_ROM ? " ROM" : ""); - } -} - -static void hax_insert_mapping_before(HAXMapping *next, uint64_t start_pa, - uint32_t size, uint64_t host_va, - uint8_t flags) -{ - HAXMapping *entry; - - entry =3D g_malloc0(sizeof(*entry)); - entry->start_pa =3D start_pa; - entry->size =3D size; - entry->host_va =3D host_va; - entry->flags =3D flags; - if (!next) { - QTAILQ_INSERT_TAIL(&mappings, entry, entry); - } else { - QTAILQ_INSERT_BEFORE(next, entry, entry); - } -} - -static bool hax_mapping_is_opposite(HAXMapping *entry, uint64_t host_va, - uint8_t flags) -{ - /* removed then added without change for the read-only flag */ - bool nop_flags =3D (entry->flags ^ flags) =3D=3D HAX_RAM_INFO_INVALID; - - return (entry->host_va =3D=3D host_va) && nop_flags; -} - -static void hax_update_mapping(uint64_t start_pa, uint32_t size, - uint64_t host_va, uint8_t flags) -{ - uint64_t end_pa =3D start_pa + size; - HAXMapping *entry, *next; - - QTAILQ_FOREACH_SAFE(entry, &mappings, entry, next) { - uint32_t chunk_sz; - if (start_pa >=3D entry->start_pa + entry->size) { - continue; - } - if (start_pa < entry->start_pa) { - chunk_sz =3D end_pa <=3D entry->start_pa ? size - : entry->start_pa - start= _pa; - hax_insert_mapping_before(entry, start_pa, chunk_sz, - host_va, flags); - start_pa +=3D chunk_sz; - host_va +=3D chunk_sz; - size -=3D chunk_sz; - } else if (start_pa > entry->start_pa) { - /* split the existing chunk at start_pa */ - chunk_sz =3D start_pa - entry->start_pa; - hax_insert_mapping_before(entry, entry->start_pa, chunk_sz, - entry->host_va, entry->flags); - entry->start_pa +=3D chunk_sz; - entry->host_va +=3D chunk_sz; - entry->size -=3D chunk_sz; - } - /* now start_pa =3D=3D entry->start_pa */ - chunk_sz =3D MIN(size, entry->size); - if (chunk_sz) { - bool nop =3D hax_mapping_is_opposite(entry, host_va, flags); - bool partial =3D chunk_sz < entry->size; - if (partial) { - /* remove the beginning of the existing chunk */ - entry->start_pa +=3D chunk_sz; - entry->host_va +=3D chunk_sz; - entry->size -=3D chunk_sz; - if (!nop) { - hax_insert_mapping_before(entry, start_pa, chunk_sz, - host_va, flags); - } - } else { /* affects the full mapping entry */ - if (nop) { /* no change to this mapping, remove it */ - QTAILQ_REMOVE(&mappings, entry, entry); - g_free(entry); - } else { /* update mapping properties */ - entry->host_va =3D host_va; - entry->flags =3D flags; - } - } - start_pa +=3D chunk_sz; - host_va +=3D chunk_sz; - size -=3D chunk_sz; - } - if (!size) { /* we are done */ - break; - } - } - if (size) { /* add the leftover */ - hax_insert_mapping_before(NULL, start_pa, size, host_va, flags); - } -} - -static void hax_process_section(MemoryRegionSection *section, uint8_t flag= s) -{ - MemoryRegion *mr =3D section->mr; - hwaddr start_pa =3D section->offset_within_address_space; - ram_addr_t size =3D int128_get64(section->size); - unsigned int delta; - uint64_t host_va; - uint32_t max_mapping_size; - - /* We only care about RAM and ROM regions */ - if (!memory_region_is_ram(mr)) { - if (memory_region_is_romd(mr)) { - /* HAXM kernel module does not support ROMD yet */ - warn_report("Ignoring ROMD region 0x%016" PRIx64 "->0x%016" PR= Ix64, - start_pa, start_pa + size); - } - return; - } - - /* Adjust start_pa and size so that they are page-aligned. (Cf - * kvm_set_phys_mem() in kvm-all.c). - */ - delta =3D qemu_real_host_page_size() - (start_pa & ~qemu_real_host_pag= e_mask()); - delta &=3D ~qemu_real_host_page_mask(); - if (delta > size) { - return; - } - start_pa +=3D delta; - size -=3D delta; - size &=3D qemu_real_host_page_mask(); - if (!size || (start_pa & ~qemu_real_host_page_mask())) { - return; - } - - host_va =3D (uintptr_t)memory_region_get_ram_ptr(mr) - + section->offset_within_region + delta; - if (memory_region_is_rom(section->mr)) { - flags |=3D HAX_RAM_INFO_ROM; - } - - /* - * The kernel module interface uses 32-bit sizes: - * https://github.com/intel/haxm/blob/master/API.md#hax_vm_ioctl_set_r= am - * - * If the mapping size is longer than 32 bits, we can't process it in = one - * call into the kernel. Instead, we split the mapping into smaller on= es, - * and call hax_update_mapping() on each. - */ - max_mapping_size =3D UINT32_MAX & qemu_real_host_page_mask(); - while (size > max_mapping_size) { - hax_update_mapping(start_pa, max_mapping_size, host_va, flags); - start_pa +=3D max_mapping_size; - size -=3D max_mapping_size; - host_va +=3D max_mapping_size; - } - /* Now size <=3D max_mapping_size */ - hax_update_mapping(start_pa, (uint32_t)size, host_va, flags); -} - -static void hax_region_add(MemoryListener *listener, - MemoryRegionSection *section) -{ - memory_region_ref(section->mr); - hax_process_section(section, 0); -} - -static void hax_region_del(MemoryListener *listener, - MemoryRegionSection *section) -{ - hax_process_section(section, HAX_RAM_INFO_INVALID); - memory_region_unref(section->mr); -} - -static void hax_transaction_begin(MemoryListener *listener) -{ - g_assert(QTAILQ_EMPTY(&mappings)); -} - -static void hax_transaction_commit(MemoryListener *listener) -{ - if (!QTAILQ_EMPTY(&mappings)) { - HAXMapping *entry, *next; - - if (DEBUG_HAX_MEM) { - hax_mapping_dump_list(); - } - QTAILQ_FOREACH_SAFE(entry, &mappings, entry, next) { - if (entry->flags & HAX_RAM_INFO_INVALID) { - /* for unmapping, put the values expected by the kernel */ - entry->flags =3D HAX_RAM_INFO_INVALID; - entry->host_va =3D 0; - } - if (hax_set_ram(entry->start_pa, entry->size, - entry->host_va, entry->flags)) { - fprintf(stderr, "%s: Failed mapping @0x%016" PRIx64 "+0x%" - PRIx32 " flags %02x\n", __func__, entry->start_pa, - entry->size, entry->flags); - } - QTAILQ_REMOVE(&mappings, entry, entry); - g_free(entry); - } - } -} - -/* currently we fake the dirty bitmap sync, always dirty */ -static void hax_log_sync(MemoryListener *listener, - MemoryRegionSection *section) -{ - MemoryRegion *mr =3D section->mr; - - if (!memory_region_is_ram(mr)) { - /* Skip MMIO regions */ - return; - } - - memory_region_set_dirty(mr, 0, int128_get64(section->size)); -} - -static MemoryListener hax_memory_listener =3D { - .name =3D "hax", - .begin =3D hax_transaction_begin, - .commit =3D hax_transaction_commit, - .region_add =3D hax_region_add, - .region_del =3D hax_region_del, - .log_sync =3D hax_log_sync, - .priority =3D MEMORY_LISTENER_PRIORITY_ACCEL, -}; - -static void hax_ram_block_added(RAMBlockNotifier *n, void *host, size_t si= ze, - size_t max_size) -{ - /* - * We must register each RAM block with the HAXM kernel module, or - * hax_set_ram() will fail for any mapping into the RAM block: - * https://github.com/intel/haxm/blob/master/API.md#hax_vm_ioctl_alloc= _ram - * - * Old versions of the HAXM kernel module (< 6.2.0) used to preallocat= e all - * host physical pages for the RAM block as part of this registration - * process, hence the name hax_populate_ram(). - */ - if (hax_populate_ram((uint64_t)(uintptr_t)host, max_size) < 0) { - fprintf(stderr, "HAX failed to populate RAM\n"); - abort(); - } -} - -static struct RAMBlockNotifier hax_ram_notifier =3D { - .ram_block_added =3D hax_ram_block_added, -}; - -void hax_memory_init(void) -{ - ram_block_notifier_add(&hax_ram_notifier); - memory_listener_register(&hax_memory_listener, &address_space_memory); -} diff --git a/target/i386/hax/hax-posix.c b/target/i386/hax/hax-posix.c deleted file mode 100644 index a057a5bd94..0000000000 --- a/target/i386/hax/hax-posix.c +++ /dev/null @@ -1,305 +0,0 @@ -/* - * QEMU HAXM support - * - * Copyright (c) 2011 Intel Corporation - * Written by: - * Jiang Yunhong - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - * - */ - -/* HAX module interface - darwin version */ -#include "qemu/osdep.h" -#include - -#include "sysemu/cpus.h" -#include "hax-accel-ops.h" - -hax_fd hax_mod_open(void) -{ - int fd =3D open("/dev/HAX", O_RDWR); - if (fd =3D=3D -1) { - fprintf(stderr, "Failed to open the hax module\n"); - } - - qemu_set_cloexec(fd); - - return fd; -} - -int hax_populate_ram(uint64_t va, uint64_t size) -{ - int ret; - - if (!hax_global.vm || !hax_global.vm->fd) { - fprintf(stderr, "Allocate memory before vm create?\n"); - return -EINVAL; - } - - if (hax_global.supports_64bit_ramblock) { - struct hax_ramblock_info ramblock =3D { - .start_va =3D va, - .size =3D size, - .reserved =3D 0 - }; - - ret =3D ioctl(hax_global.vm->fd, HAX_VM_IOCTL_ADD_RAMBLOCK, &rambl= ock); - } else { - struct hax_alloc_ram_info info =3D { - .size =3D (uint32_t)size, - .pad =3D 0, - .va =3D va - }; - - ret =3D ioctl(hax_global.vm->fd, HAX_VM_IOCTL_ALLOC_RAM, &info); - } - if (ret < 0) { - fprintf(stderr, "Failed to register RAM block: ret=3D%d, va=3D0x%"= PRIx64 - ", size=3D0x%" PRIx64 ", method=3D%s\n", ret, va, size, - hax_global.supports_64bit_ramblock ? "new" : "legacy"); - return ret; - } - return 0; -} - -int hax_set_ram(uint64_t start_pa, uint32_t size, uint64_t host_va, int fl= ags) -{ - struct hax_set_ram_info info; - int ret; - - info.pa_start =3D start_pa; - info.size =3D size; - info.va =3D host_va; - info.flags =3D (uint8_t) flags; - - ret =3D ioctl(hax_global.vm->fd, HAX_VM_IOCTL_SET_RAM, &info); - if (ret < 0) { - return -errno; - } - return 0; -} - -int hax_capability(struct hax_state *hax, struct hax_capabilityinfo *cap) -{ - int ret; - - ret =3D ioctl(hax->fd, HAX_IOCTL_CAPABILITY, cap); - if (ret =3D=3D -1) { - fprintf(stderr, "Failed to get HAX capability\n"); - return -errno; - } - - return 0; -} - -int hax_mod_version(struct hax_state *hax, struct hax_module_version *vers= ion) -{ - int ret; - - ret =3D ioctl(hax->fd, HAX_IOCTL_VERSION, version); - if (ret =3D=3D -1) { - fprintf(stderr, "Failed to get HAX version\n"); - return -errno; - } - - return 0; -} - -static char *hax_vm_devfs_string(int vm_id) -{ - return g_strdup_printf("/dev/hax_vm/vm%02d", vm_id); -} - -static char *hax_vcpu_devfs_string(int vm_id, int vcpu_id) -{ - return g_strdup_printf("/dev/hax_vm%02d/vcpu%02d", vm_id, vcpu_id); -} - -int hax_host_create_vm(struct hax_state *hax, int *vmid) -{ - int ret; - int vm_id =3D 0; - - if (hax_invalid_fd(hax->fd)) { - return -EINVAL; - } - - if (hax->vm) { - return 0; - } - - ret =3D ioctl(hax->fd, HAX_IOCTL_CREATE_VM, &vm_id); - *vmid =3D vm_id; - return ret; -} - -hax_fd hax_host_open_vm(struct hax_state *hax, int vm_id) -{ - hax_fd fd; - char *vm_name =3D NULL; - - vm_name =3D hax_vm_devfs_string(vm_id); - if (!vm_name) { - return -1; - } - - fd =3D open(vm_name, O_RDWR); - g_free(vm_name); - - qemu_set_cloexec(fd); - - return fd; -} - -int hax_notify_qemu_version(hax_fd vm_fd, struct hax_qemu_version *qversio= n) -{ - int ret; - - if (hax_invalid_fd(vm_fd)) { - return -EINVAL; - } - - ret =3D ioctl(vm_fd, HAX_VM_IOCTL_NOTIFY_QEMU_VERSION, qversion); - - if (ret < 0) { - fprintf(stderr, "Failed to notify qemu API version\n"); - return ret; - } - return 0; -} - -/* Simply assume the size should be bigger than the hax_tunnel, - * since the hax_tunnel can be extended later with compatibility considered - */ -int hax_host_create_vcpu(hax_fd vm_fd, int vcpuid) -{ - int ret; - - ret =3D ioctl(vm_fd, HAX_VM_IOCTL_VCPU_CREATE, &vcpuid); - if (ret < 0) { - fprintf(stderr, "Failed to create vcpu %x\n", vcpuid); - } - - return ret; -} - -hax_fd hax_host_open_vcpu(int vmid, int vcpuid) -{ - char *devfs_path =3D NULL; - hax_fd fd; - - devfs_path =3D hax_vcpu_devfs_string(vmid, vcpuid); - if (!devfs_path) { - fprintf(stderr, "Failed to get the devfs\n"); - return -EINVAL; - } - - fd =3D open(devfs_path, O_RDWR); - g_free(devfs_path); - if (fd < 0) { - fprintf(stderr, "Failed to open the vcpu devfs\n"); - } - qemu_set_cloexec(fd); - return fd; -} - -int hax_host_setup_vcpu_channel(AccelCPUState *vcpu) -{ - int ret; - struct hax_tunnel_info info; - - ret =3D ioctl(vcpu->fd, HAX_VCPU_IOCTL_SETUP_TUNNEL, &info); - if (ret) { - fprintf(stderr, "Failed to setup the hax tunnel\n"); - return ret; - } - - if (!valid_hax_tunnel_size(info.size)) { - fprintf(stderr, "Invalid hax tunnel size %x\n", info.size); - ret =3D -EINVAL; - return ret; - } - - vcpu->tunnel =3D (struct hax_tunnel *) (intptr_t) (info.va); - vcpu->iobuf =3D (unsigned char *) (intptr_t) (info.io_va); - return 0; -} - -int hax_vcpu_run(AccelCPUState *vcpu) -{ - return ioctl(vcpu->fd, HAX_VCPU_IOCTL_RUN, NULL); -} - -int hax_sync_fpu(CPUArchState *env, struct fx_layout *fl, int set) -{ - int ret, fd; - - fd =3D hax_vcpu_get_fd(env); - if (fd <=3D 0) { - return -1; - } - - if (set) { - ret =3D ioctl(fd, HAX_VCPU_IOCTL_SET_FPU, fl); - } else { - ret =3D ioctl(fd, HAX_VCPU_IOCTL_GET_FPU, fl); - } - return ret; -} - -int hax_sync_msr(CPUArchState *env, struct hax_msr_data *msrs, int set) -{ - int ret, fd; - - fd =3D hax_vcpu_get_fd(env); - if (fd <=3D 0) { - return -1; - } - if (set) { - ret =3D ioctl(fd, HAX_VCPU_IOCTL_SET_MSRS, msrs); - } else { - ret =3D ioctl(fd, HAX_VCPU_IOCTL_GET_MSRS, msrs); - } - return ret; -} - -int hax_sync_vcpu_state(CPUArchState *env, struct vcpu_state_t *state, int= set) -{ - int ret, fd; - - fd =3D hax_vcpu_get_fd(env); - if (fd <=3D 0) { - return -1; - } - - if (set) { - ret =3D ioctl(fd, HAX_VCPU_SET_REGS, state); - } else { - ret =3D ioctl(fd, HAX_VCPU_GET_REGS, state); - } - return ret; -} - -int hax_inject_interrupt(CPUArchState *env, int vector) -{ - int fd; - - fd =3D hax_vcpu_get_fd(env); - if (fd <=3D 0) { - return -1; - } - - return ioctl(fd, HAX_VCPU_IOCTL_INTERRUPT, &vector); -} - -void hax_kick_vcpu_thread(CPUState *cpu) -{ - /* - * FIXME: race condition with the exit_request check in - * hax_vcpu_hax_exec - */ - cpu->exit_request =3D 1; - cpus_kick_thread(cpu); -} diff --git a/target/i386/hax/hax-windows.c b/target/i386/hax/hax-windows.c deleted file mode 100644 index 4bf6cc08d2..0000000000 --- a/target/i386/hax/hax-windows.c +++ /dev/null @@ -1,485 +0,0 @@ -/* - * QEMU HAXM support - * - * Copyright (c) 2011 Intel Corporation - * Written by: - * Jiang Yunhong - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - * - */ - -#include "qemu/osdep.h" -#include "cpu.h" -#include "hax-accel-ops.h" - -/* - * return 0 when success, -1 when driver not loaded, - * other negative value for other failure - */ -static int hax_open_device(hax_fd *fd) -{ - uint32_t errNum =3D 0; - HANDLE hDevice; - - if (!fd) { - return -2; - } - - hDevice =3D CreateFile("\\\\.\\HAX", - GENERIC_READ | GENERIC_WRITE, - 0, NULL, CREATE_ALWAYS, FILE_ATTRIBUTE_NORMAL, NU= LL); - - if (hDevice =3D=3D INVALID_HANDLE_VALUE) { - fprintf(stderr, "Failed to open the HAX device!\n"); - errNum =3D GetLastError(); - if (errNum =3D=3D ERROR_FILE_NOT_FOUND) { - return -1; - } - return -2; - } - *fd =3D hDevice; - return 0; -} - -/* hax_fd hax_mod_open */ - hax_fd hax_mod_open(void) -{ - int ret; - hax_fd fd =3D NULL; - - ret =3D hax_open_device(&fd); - if (ret !=3D 0) { - fprintf(stderr, "Open HAX device failed\n"); - } - - return fd; -} - -int hax_populate_ram(uint64_t va, uint64_t size) -{ - int ret; - HANDLE hDeviceVM; - DWORD dSize =3D 0; - - if (!hax_global.vm || !hax_global.vm->fd) { - fprintf(stderr, "Allocate memory before vm create?\n"); - return -EINVAL; - } - - hDeviceVM =3D hax_global.vm->fd; - if (hax_global.supports_64bit_ramblock) { - struct hax_ramblock_info ramblock =3D { - .start_va =3D va, - .size =3D size, - .reserved =3D 0 - }; - - ret =3D DeviceIoControl(hDeviceVM, - HAX_VM_IOCTL_ADD_RAMBLOCK, - &ramblock, sizeof(ramblock), NULL, 0, &dSize, - (LPOVERLAPPED) NULL); - } else { - struct hax_alloc_ram_info info =3D { - .size =3D (uint32_t) size, - .pad =3D 0, - .va =3D va - }; - - ret =3D DeviceIoControl(hDeviceVM, - HAX_VM_IOCTL_ALLOC_RAM, - &info, sizeof(info), NULL, 0, &dSize, - (LPOVERLAPPED) NULL); - } - - if (!ret) { - fprintf(stderr, "Failed to register RAM block: va=3D0x%" PRIx64 - ", size=3D0x%" PRIx64 ", method=3D%s\n", va, size, - hax_global.supports_64bit_ramblock ? "new" : "legacy"); - return ret; - } - - return 0; -} - -int hax_set_ram(uint64_t start_pa, uint32_t size, uint64_t host_va, int fl= ags) -{ - struct hax_set_ram_info info; - HANDLE hDeviceVM =3D hax_global.vm->fd; - DWORD dSize =3D 0; - int ret; - - info.pa_start =3D start_pa; - info.size =3D size; - info.va =3D host_va; - info.flags =3D (uint8_t) flags; - - ret =3D DeviceIoControl(hDeviceVM, HAX_VM_IOCTL_SET_RAM, - &info, sizeof(info), NULL, 0, &dSize, - (LPOVERLAPPED) NULL); - - if (!ret) { - return -EFAULT; - } else { - return 0; - } -} - -int hax_capability(struct hax_state *hax, struct hax_capabilityinfo *cap) -{ - int ret; - HANDLE hDevice =3D hax->fd; /* handle to hax module */ - DWORD dSize =3D 0; - DWORD err =3D 0; - - if (hax_invalid_fd(hDevice)) { - fprintf(stderr, "Invalid fd for hax device!\n"); - return -ENODEV; - } - - ret =3D DeviceIoControl(hDevice, HAX_IOCTL_CAPABILITY, NULL, 0, cap, - sizeof(*cap), &dSize, (LPOVERLAPPED) NULL); - - if (!ret) { - err =3D GetLastError(); - if (err =3D=3D ERROR_INSUFFICIENT_BUFFER || err =3D=3D ERROR_MORE_= DATA) { - fprintf(stderr, "hax capability is too long to hold.\n"); - } - fprintf(stderr, "Failed to get Hax capability:%luu\n", err); - return -EFAULT; - } else { - return 0; - } -} - -int hax_mod_version(struct hax_state *hax, struct hax_module_version *vers= ion) -{ - int ret; - HANDLE hDevice =3D hax->fd; /* handle to hax module */ - DWORD dSize =3D 0; - DWORD err =3D 0; - - if (hax_invalid_fd(hDevice)) { - fprintf(stderr, "Invalid fd for hax device!\n"); - return -ENODEV; - } - - ret =3D DeviceIoControl(hDevice, - HAX_IOCTL_VERSION, - NULL, 0, - version, sizeof(*version), &dSize, - (LPOVERLAPPED) NULL); - - if (!ret) { - err =3D GetLastError(); - if (err =3D=3D ERROR_INSUFFICIENT_BUFFER || err =3D=3D ERROR_MORE_= DATA) { - fprintf(stderr, "hax module verion is too long to hold.\n"); - } - fprintf(stderr, "Failed to get Hax module version:%lu\n", err); - return -EFAULT; - } else { - return 0; - } -} - -static char *hax_vm_devfs_string(int vm_id) -{ - return g_strdup_printf("\\\\.\\hax_vm%02d", vm_id); -} - -static char *hax_vcpu_devfs_string(int vm_id, int vcpu_id) -{ - return g_strdup_printf("\\\\.\\hax_vm%02d_vcpu%02d", vm_id, vcpu_id); -} - -int hax_host_create_vm(struct hax_state *hax, int *vmid) -{ - int ret; - int vm_id =3D 0; - DWORD dSize =3D 0; - - if (hax_invalid_fd(hax->fd)) { - return -EINVAL; - } - - if (hax->vm) { - return 0; - } - - ret =3D DeviceIoControl(hax->fd, - HAX_IOCTL_CREATE_VM, - NULL, 0, &vm_id, sizeof(vm_id), &dSize, - (LPOVERLAPPED) NULL); - if (!ret) { - fprintf(stderr, "Failed to create VM. Error code: %lu\n", - GetLastError()); - return -1; - } - *vmid =3D vm_id; - return 0; -} - -hax_fd hax_host_open_vm(struct hax_state *hax, int vm_id) -{ - char *vm_name =3D NULL; - hax_fd hDeviceVM; - - vm_name =3D hax_vm_devfs_string(vm_id); - if (!vm_name) { - fprintf(stderr, "Failed to open VM. VM name is null\n"); - return INVALID_HANDLE_VALUE; - } - - hDeviceVM =3D CreateFile(vm_name, - GENERIC_READ | GENERIC_WRITE, - 0, NULL, CREATE_ALWAYS, FILE_ATTRIBUTE_NORMAL, = NULL); - if (hDeviceVM =3D=3D INVALID_HANDLE_VALUE) { - fprintf(stderr, "Open the vm device error:%s, ec:%lu\n", - vm_name, GetLastError()); - } - - g_free(vm_name); - return hDeviceVM; -} - -int hax_notify_qemu_version(hax_fd vm_fd, struct hax_qemu_version *qversio= n) -{ - int ret; - DWORD dSize =3D 0; - if (hax_invalid_fd(vm_fd)) { - return -EINVAL; - } - ret =3D DeviceIoControl(vm_fd, - HAX_VM_IOCTL_NOTIFY_QEMU_VERSION, - qversion, sizeof(struct hax_qemu_version), - NULL, 0, &dSize, (LPOVERLAPPED) NULL); - if (!ret) { - fprintf(stderr, "Failed to notify qemu API version\n"); - return -1; - } - return 0; -} - -int hax_host_create_vcpu(hax_fd vm_fd, int vcpuid) -{ - int ret; - DWORD dSize =3D 0; - - ret =3D DeviceIoControl(vm_fd, - HAX_VM_IOCTL_VCPU_CREATE, - &vcpuid, sizeof(vcpuid), NULL, 0, &dSize, - (LPOVERLAPPED) NULL); - if (!ret) { - fprintf(stderr, "Failed to create vcpu %x\n", vcpuid); - return -1; - } - - return 0; -} - -hax_fd hax_host_open_vcpu(int vmid, int vcpuid) -{ - char *devfs_path =3D NULL; - hax_fd hDeviceVCPU; - - devfs_path =3D hax_vcpu_devfs_string(vmid, vcpuid); - if (!devfs_path) { - fprintf(stderr, "Failed to get the devfs\n"); - return INVALID_HANDLE_VALUE; - } - - hDeviceVCPU =3D CreateFile(devfs_path, - GENERIC_READ | GENERIC_WRITE, - 0, NULL, CREATE_ALWAYS, FILE_ATTRIBUTE_NORMAL, - NULL); - - if (hDeviceVCPU =3D=3D INVALID_HANDLE_VALUE) { - fprintf(stderr, "Failed to open the vcpu devfs\n"); - } - g_free(devfs_path); - return hDeviceVCPU; -} - -int hax_host_setup_vcpu_channel(AccelCPUState *vcpu) -{ - hax_fd hDeviceVCPU =3D vcpu->fd; - int ret; - struct hax_tunnel_info info; - DWORD dSize =3D 0; - - ret =3D DeviceIoControl(hDeviceVCPU, - HAX_VCPU_IOCTL_SETUP_TUNNEL, - NULL, 0, &info, sizeof(info), &dSize, - (LPOVERLAPPED) NULL); - if (!ret) { - fprintf(stderr, "Failed to setup the hax tunnel\n"); - return -1; - } - - if (!valid_hax_tunnel_size(info.size)) { - fprintf(stderr, "Invalid hax tunnel size %x\n", info.size); - ret =3D -EINVAL; - return ret; - } - vcpu->tunnel =3D (struct hax_tunnel *) (intptr_t) (info.va); - vcpu->iobuf =3D (unsigned char *) (intptr_t) (info.io_va); - return 0; -} - -int hax_vcpu_run(AccelCPUState *vcpu) -{ - int ret; - HANDLE hDeviceVCPU =3D vcpu->fd; - DWORD dSize =3D 0; - - ret =3D DeviceIoControl(hDeviceVCPU, - HAX_VCPU_IOCTL_RUN, - NULL, 0, NULL, 0, &dSize, (LPOVERLAPPED) NULL); - if (!ret) { - return -EFAULT; - } else { - return 0; - } -} - -int hax_sync_fpu(CPUArchState *env, struct fx_layout *fl, int set) -{ - int ret; - hax_fd fd; - HANDLE hDeviceVCPU; - DWORD dSize =3D 0; - - fd =3D hax_vcpu_get_fd(env); - if (hax_invalid_fd(fd)) { - return -1; - } - - hDeviceVCPU =3D fd; - - if (set) { - ret =3D DeviceIoControl(hDeviceVCPU, - HAX_VCPU_IOCTL_SET_FPU, - fl, sizeof(*fl), NULL, 0, &dSize, - (LPOVERLAPPED) NULL); - } else { - ret =3D DeviceIoControl(hDeviceVCPU, - HAX_VCPU_IOCTL_GET_FPU, - NULL, 0, fl, sizeof(*fl), &dSize, - (LPOVERLAPPED) NULL); - } - if (!ret) { - return -EFAULT; - } else { - return 0; - } -} - -int hax_sync_msr(CPUArchState *env, struct hax_msr_data *msrs, int set) -{ - int ret; - hax_fd fd; - HANDLE hDeviceVCPU; - DWORD dSize =3D 0; - - fd =3D hax_vcpu_get_fd(env); - if (hax_invalid_fd(fd)) { - return -1; - } - hDeviceVCPU =3D fd; - - if (set) { - ret =3D DeviceIoControl(hDeviceVCPU, - HAX_VCPU_IOCTL_SET_MSRS, - msrs, sizeof(*msrs), - msrs, sizeof(*msrs), &dSize, (LPOVERLAPPED) = NULL); - } else { - ret =3D DeviceIoControl(hDeviceVCPU, - HAX_VCPU_IOCTL_GET_MSRS, - msrs, sizeof(*msrs), - msrs, sizeof(*msrs), &dSize, (LPOVERLAPPED) = NULL); - } - if (!ret) { - return -EFAULT; - } else { - return 0; - } -} - -int hax_sync_vcpu_state(CPUArchState *env, struct vcpu_state_t *state, int= set) -{ - int ret; - hax_fd fd; - HANDLE hDeviceVCPU; - DWORD dSize; - - fd =3D hax_vcpu_get_fd(env); - if (hax_invalid_fd(fd)) { - return -1; - } - - hDeviceVCPU =3D fd; - - if (set) { - ret =3D DeviceIoControl(hDeviceVCPU, - HAX_VCPU_SET_REGS, - state, sizeof(*state), - NULL, 0, &dSize, (LPOVERLAPPED) NULL); - } else { - ret =3D DeviceIoControl(hDeviceVCPU, - HAX_VCPU_GET_REGS, - NULL, 0, - state, sizeof(*state), &dSize, - (LPOVERLAPPED) NULL); - } - if (!ret) { - return -EFAULT; - } else { - return 0; - } -} - -int hax_inject_interrupt(CPUArchState *env, int vector) -{ - int ret; - hax_fd fd; - HANDLE hDeviceVCPU; - DWORD dSize; - - fd =3D hax_vcpu_get_fd(env); - if (hax_invalid_fd(fd)) { - return -1; - } - - hDeviceVCPU =3D fd; - - ret =3D DeviceIoControl(hDeviceVCPU, - HAX_VCPU_IOCTL_INTERRUPT, - &vector, sizeof(vector), NULL, 0, &dSize, - (LPOVERLAPPED) NULL); - if (!ret) { - return -EFAULT; - } else { - return 0; - } -} - -static void CALLBACK dummy_apc_func(ULONG_PTR unused) -{ -} - -void hax_kick_vcpu_thread(CPUState *cpu) -{ - /* - * FIXME: race condition with the exit_request check in - * hax_vcpu_hax_exec - */ - cpu->exit_request =3D 1; - if (!qemu_cpu_is_self(cpu)) { - if (!QueueUserAPC(dummy_apc_func, cpu->accel->hThread, 0)) { - fprintf(stderr, "%s: QueueUserAPC failed with error %lu\n", - __func__, GetLastError()); - exit(1); - } - } -} diff --git a/accel/Kconfig b/accel/Kconfig index 8bdedb7d15..a30cf2eb48 100644 --- a/accel/Kconfig +++ b/accel/Kconfig @@ -4,9 +4,6 @@ config WHPX config NVMM bool =20 -config HAX - bool - config HVF bool =20 diff --git a/accel/stubs/meson.build b/accel/stubs/meson.build index f7a9486e06..6b0f200efe 100644 --- a/accel/stubs/meson.build +++ b/accel/stubs/meson.build @@ -1,5 +1,4 @@ sysemu_stubs_ss =3D ss.source_set() -sysemu_stubs_ss.add(when: 'CONFIG_HAX', if_false: files('hax-stub.c')) sysemu_stubs_ss.add(when: 'CONFIG_XEN', if_false: files('xen-stub.c')) sysemu_stubs_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) sysemu_stubs_ss.add(when: 'CONFIG_TCG', if_false: files('tcg-stub.c')) diff --git a/meson_options.txt b/meson_options.txt index aaea5ddd77..4f3b1ecab0 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -69,8 +69,6 @@ option('malloc', type : 'combo', choices : ['system', 'tc= malloc', 'jemalloc'], =20 option('kvm', type: 'feature', value: 'auto', description: 'KVM acceleration support') -option('hax', type: 'feature', value: 'auto', - description: 'HAX acceleration support') option('whpx', type: 'feature', value: 'auto', description: 'WHPX acceleration support') option('hvf', type: 'feature', value: 'auto', diff --git a/qemu-options.hx b/qemu-options.hx index 29b98c3d4c..463f520c57 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -26,7 +26,7 @@ DEF("machine", HAS_ARG, QEMU_OPTION_machine, \ "-machine [type=3D]name[,prop[=3Dvalue][,...]]\n" " selects emulated machine ('-machine help' for list)\n" " property accel=3Daccel1[:accel2[:...]] selects accele= rator\n" - " supported accelerators are kvm, xen, hax, hvf, nvmm, = whpx or tcg (default: tcg)\n" + " supported accelerators are kvm, xen, hvf, nvmm, whpx = or tcg (default: tcg)\n" " vmport=3Don|off|auto controls emulation of vmport (de= fault: auto)\n" " dump-guest-core=3Don|off include guest memory in a co= re dump (default=3Don)\n" " mem-merge=3Don|off controls memory merge support (def= ault: on)\n" @@ -59,7 +59,7 @@ SRST =20 ``accel=3Daccels1[:accels2[:...]]`` This is used to enable an accelerator. Depending on the target - architecture, kvm, xen, hax, hvf, nvmm, whpx or tcg can be availab= le. + architecture, kvm, xen, hvf, nvmm, whpx or tcg can be available. By default, tcg is used. If there is more than one accelerator specified, the next one is used if the previous one fails to initialize. @@ -178,7 +178,7 @@ ERST =20 DEF("accel", HAS_ARG, QEMU_OPTION_accel, "-accel [accel=3D]accelerator[,prop[=3Dvalue][,...]]\n" - " select accelerator (kvm, xen, hax, hvf, nvmm, whpx or= tcg; use 'help' for a list)\n" + " select accelerator (kvm, xen, hvf, nvmm, whpx or tcg;= use 'help' for a list)\n" " igd-passthru=3Don|off (enable Xen integrated Intel gr= aphics passthrough, default=3Doff)\n" " kernel-irqchip=3Don|off|split controls accelerated ir= qchip support (default=3Don)\n" " kvm-shadow-mem=3Dsize of KVM shadow MMU in bytes\n" @@ -191,7 +191,7 @@ DEF("accel", HAS_ARG, QEMU_OPTION_accel, SRST ``-accel name[,prop=3Dvalue[,...]]`` This is used to enable an accelerator. Depending on the target - architecture, kvm, xen, hax, hvf, nvmm, whpx or tcg can be available. = By + architecture, kvm, xen, hvf, nvmm, whpx or tcg can be available. By default, tcg is used. If there is more than one accelerator specified, the next one is used if the previous one fails to initialize. diff --git a/scripts/ci/org.centos/stream/8/x86_64/configure b/scripts/ci/o= rg.centos/stream/8/x86_64/configure index d02b09a4b9..131f8ee5f3 100755 --- a/scripts/ci/org.centos/stream/8/x86_64/configure +++ b/scripts/ci/org.centos/stream/8/x86_64/configure @@ -68,7 +68,6 @@ --disable-gtk \ --disable-guest-agent \ --disable-guest-agent-msi \ ---disable-hax \ --disable-hvf \ --disable-iconv \ --disable-kvm \ diff --git a/scripts/meson-buildoptions.sh b/scripts/meson-buildoptions.sh index 9da3fe299b..504a61ad01 100644 --- a/scripts/meson-buildoptions.sh +++ b/scripts/meson-buildoptions.sh @@ -110,7 +110,6 @@ meson_options_help() { printf "%s\n" ' gtk-clipboard clipboard support for the gtk UI (EXPER= IMENTAL, MAY HANG)' printf "%s\n" ' guest-agent Build QEMU Guest Agent' printf "%s\n" ' guest-agent-msi Build MSI package for the QEMU Guest Ag= ent' - printf "%s\n" ' hax HAX acceleration support' printf "%s\n" ' hvf HVF acceleration support' printf "%s\n" ' iconv Font glyph conversion support' printf "%s\n" ' jack JACK sound support' @@ -312,8 +311,6 @@ _meson_option_parse() { --disable-guest-agent) printf "%s" -Dguest_agent=3Ddisabled ;; --enable-guest-agent-msi) printf "%s" -Dguest_agent_msi=3Denabled ;; --disable-guest-agent-msi) printf "%s" -Dguest_agent_msi=3Ddisabled ;; - --enable-hax) printf "%s" -Dhax=3Denabled ;; - --disable-hax) printf "%s" -Dhax=3Ddisabled ;; --enable-hexagon-idef-parser) printf "%s" -Dhexagon_idef_parser=3Dtrue= ;; --disable-hexagon-idef-parser) printf "%s" -Dhexagon_idef_parser=3Dfal= se ;; --enable-hvf) printf "%s" -Dhvf=3Denabled ;; diff --git a/target/i386/hax/meson.build b/target/i386/hax/meson.build deleted file mode 100644 index 6ac314aa35..0000000000 --- a/target/i386/hax/meson.build +++ /dev/null @@ -1,7 +0,0 @@ -i386_system_ss.add(when: 'CONFIG_HAX', if_true: files( - 'hax-all.c', - 'hax-mem.c', - 'hax-accel-ops.c', -)) -i386_system_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('h= ax-posix.c')) -i386_system_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('h= ax-windows.c')) diff --git a/target/i386/meson.build b/target/i386/meson.build index 1effe1ed9a..6f1036d469 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -25,7 +25,6 @@ i386_system_ss.add(when: 'CONFIG_SEV', if_true: files('se= v.c'), if_false: files( i386_user_ss =3D ss.source_set() =20 subdir('kvm') -subdir('hax') subdir('whpx') subdir('nvmm') subdir('hvf') --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 31 Aug 2023 05:57:00 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, Michael Tokarev , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini , Alexandre Iooss , Mahmoud Mandour , Riku Voipio , Laurent Vivier , Peter Xu , David Hildenbrand Subject: [PULL 02/41] accel/tcg: spelling fixes Date: Thu, 31 Aug 2023 14:56:04 +0200 Message-ID: <20230831125646.67855-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693486937599100001 From: Michael Tokarev Signed-off-by: Michael Tokarev Message-ID: <20230823065335.1919380-18-mjt@tls.msk.ru> Reviewed-by: Alex Benn=C3=A9e Message-ID: <20230823065335.1919380-19-mjt@tls.msk.ru> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/tcg-cpu-ops.h | 2 +- include/tcg/helper-info.h | 2 +- include/tcg/tcg.h | 4 ++-- include/user/safe-syscall.h | 2 +- accel/tcg/tb-maint.c | 2 +- contrib/plugins/cache.c | 2 +- contrib/plugins/lockstep.c | 2 +- linux-user/flatload.c | 2 +- linux-user/syscall.c | 4 ++-- semihosting/config.c | 2 +- semihosting/syscalls.c | 4 ++-- softmmu/icount.c | 2 +- softmmu/ioport.c | 2 +- 13 files changed, 16 insertions(+), 16 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 3e8b1b737a..479713a36e 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -14,7 +14,7 @@ =20 struct TCGCPUOps { /** - * @initialize: Initalize TCG state + * @initialize: Initialize TCG state * * Called when the first CPU is realized. */ diff --git a/include/tcg/helper-info.h b/include/tcg/helper-info.h index 4b6c9b43e8..7c27d6164a 100644 --- a/include/tcg/helper-info.h +++ b/include/tcg/helper-info.h @@ -1,5 +1,5 @@ /* - * TCG Helper Infomation Structure + * TCG Helper Information Structure * * Copyright (c) 2023 Linaro Ltd * diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 61d7c81b44..c9c6d770d0 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -879,7 +879,7 @@ enum { /* Instruction operands are 64-bits (otherwise 32-bits). */ TCG_OPF_64BIT =3D 0x10, /* Instruction is optional and not implemented by the host, or insn - is generic and should not be implemened by the host. */ + is generic and should not be implemented by the host. */ TCG_OPF_NOT_PRESENT =3D 0x20, /* Instruction operands are vectors. */ TCG_OPF_VECTOR =3D 0x40, @@ -1123,7 +1123,7 @@ static inline int tcg_can_emit_vec_op(TCGOpcode o, TC= GType t, unsigned ve) /* Expand the tuple (opc, type, vece) on the given arguments. */ void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...); =20 -/* Replicate a constant C accoring to the log2 of the element size. */ +/* Replicate a constant C according to the log2 of the element size. */ uint64_t dup_const(unsigned vece, uint64_t c); =20 #define dup_const(VECE, C) \ diff --git a/include/user/safe-syscall.h b/include/user/safe-syscall.h index ddceef12e2..195cedac04 100644 --- a/include/user/safe-syscall.h +++ b/include/user/safe-syscall.h @@ -91,7 +91,7 @@ * * The basic setup is that we make the host syscall via a known * section of host native assembly. If a signal occurs, our signal - * handler checks the interrupted host PC against the addresse of that + * handler checks the interrupted host PC against the address of that * known section. If the PC is before or at the address of the syscall * instruction then we change the PC to point at a "return * -QEMU_ERESTARTSYS" code path instead, and then exit the signal handler diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index c406b2f7b7..32ae8af61c 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -1,5 +1,5 @@ /* - * Translation Block Maintaince + * Translation Block Maintenance * * Copyright (c) 2003 Fabrice Bellard * diff --git a/contrib/plugins/cache.c b/contrib/plugins/cache.c index 5036213f1b..dea4a56c8d 100644 --- a/contrib/plugins/cache.c +++ b/contrib/plugins/cache.c @@ -350,7 +350,7 @@ static int in_cache(Cache *cache, uint64_t addr) * @cache: The cache under simulation * @addr: The address of the requested memory location * - * Returns true if the requsted data is hit in the cache and false when mi= ssed. + * Returns true if the requested data is hit in the cache and false when m= issed. * The cache is updated on miss for the next access. */ static bool access_cache(Cache *cache, uint64_t addr) diff --git a/contrib/plugins/lockstep.c b/contrib/plugins/lockstep.c index 3614c3564c..850f7b2941 100644 --- a/contrib/plugins/lockstep.c +++ b/contrib/plugins/lockstep.c @@ -108,7 +108,7 @@ static void report_divergance(ExecState *us, ExecState = *them) =20 /* * If we have diverged before did we get back on track or are we - * totally loosing it? + * totally losing it? */ if (divergence_log) { DivergeState *last =3D (DivergeState *) divergence_log->data; diff --git a/linux-user/flatload.c b/linux-user/flatload.c index 8f5e9f489b..4331a11bf0 100644 --- a/linux-user/flatload.c +++ b/linux-user/flatload.c @@ -780,7 +780,7 @@ int load_flt_binary(struct linux_binprm *bprm, struct i= mage_info *info) /* Enforce final stack alignment of 16 bytes. This is sufficient for all current targets, and excess alignment is harmless. */ stack_len =3D bprm->envc + bprm->argc + 2; - stack_len +=3D flat_argvp_envp_on_stack() ? 2 : 0; /* arvg, argp */ + stack_len +=3D flat_argvp_envp_on_stack() ? 2 : 0; /* argv, argp */ stack_len +=3D 1; /* argc */ stack_len *=3D sizeof(abi_ulong); sp -=3D (sp - stack_len) & 15; diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 9353268cc1..7ccd3affbe 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -1809,7 +1809,7 @@ static inline abi_long target_to_host_cmsg(struct msg= hdr *msgh, uint32_t *dst =3D (uint32_t *)data; =20 memcpy(dst, target_data, len); - /* fix endianess of first 32-bit word */ + /* fix endianness of first 32-bit word */ if (len >=3D sizeof(uint32_t)) { *dst =3D tswap32(*dst); } @@ -2920,7 +2920,7 @@ get_timeout: unlock_user(results, optval_addr, 0); return ret; } - /* swap host endianess to target endianess. */ + /* swap host endianness to target endianness. */ for (i =3D 0; i < (len / sizeof(uint32_t)); i++) { results[i] =3D tswap32(results[i]); } diff --git a/semihosting/config.c b/semihosting/config.c index 89a1759687..8ca569735d 100644 --- a/semihosting/config.c +++ b/semihosting/config.c @@ -8,7 +8,7 @@ * targets that support it. Architecture specific handling is handled * in target/HW/HW-semi.c * - * Semihosting is sightly strange in that it is also supported by some + * Semihosting is slightly strange in that it is also supported by some * linux-user targets. However in that use case no configuration of * the outputs and command lines is supported. * diff --git a/semihosting/syscalls.c b/semihosting/syscalls.c index 68899ebb1c..d27574a1e2 100644 --- a/semihosting/syscalls.c +++ b/semihosting/syscalls.c @@ -720,7 +720,7 @@ void semihost_sys_read_gf(CPUState *cs, gdb_syscall_com= plete_cb complete, GuestFD *gf, target_ulong buf, target_ulong len) { /* - * Bound length for 64-bit guests on 32-bit hosts, not overlowing ssiz= e_t. + * Bound length for 64-bit guests on 32-bit hosts, not overflowing ssi= ze_t. * Note the Linux kernel does this with MAX_RW_COUNT, so it's not a bad * idea to do this unconditionally. */ @@ -761,7 +761,7 @@ void semihost_sys_write_gf(CPUState *cs, gdb_syscall_co= mplete_cb complete, GuestFD *gf, target_ulong buf, target_ulong len) { /* - * Bound length for 64-bit guests on 32-bit hosts, not overlowing ssiz= e_t. + * Bound length for 64-bit guests on 32-bit hosts, not overflowing ssi= ze_t. * Note the Linux kernel does this with MAX_RW_COUNT, so it's not a bad * idea to do this unconditionally. */ diff --git a/softmmu/icount.c b/softmmu/icount.c index a5cef9c60a..144e24829c 100644 --- a/softmmu/icount.c +++ b/softmmu/icount.c @@ -325,7 +325,7 @@ void icount_start_warp_timer(void) * vCPU is sleeping and warp can't be started. * It is probably a race condition: notification sent * to vCPU was processed in advance and vCPU went to sleep. - * Therefore we have to wake it up for doing someting. + * Therefore we have to wake it up for doing something. */ if (replay_has_event()) { qemu_clock_notify(QEMU_CLOCK_VIRTUAL); diff --git a/softmmu/ioport.c b/softmmu/ioport.c index b66e0a5a8e..1824aa808c 100644 --- a/softmmu/ioport.c +++ b/softmmu/ioport.c @@ -22,7 +22,7 @@ * THE SOFTWARE. */ /* - * splitted out ioport related stuffs from vl.c. + * split out ioport related stuffs from vl.c. */ =20 #include "qemu/osdep.h" --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693486862; cv=none; d=zohomail.com; s=zohoarc; b=lWRTNFCneWWxPVVqkFpY8RZOZSwHTQ4p1VXTpWqvUtIWj/Qhg0OTceD/MvrJteNcrxwo+bQSV/mnu8wewfAqDtTXzoX60iKAsWEIhzghKcUbrbbSMysBb0Zq5aohyrFOMTAnJZBSOS7cNQ4YVwgDIL7z6YzAvdr7RWOTaVozVv0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693486862; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Thu, 31 Aug 2023 05:57:06 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PULL 03/41] qemu/uri: Use QueryParams type definition Date: Thu, 31 Aug 2023 14:56:05 +0200 Message-ID: <20230831125646.67855-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693486879765100001 Follow QEMU CODING_STYLE, use the type definition, making that prototype match the following two. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Message-Id: <20230605175647.88395-4-philmd@linaro.org> --- include/qemu/uri.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/qemu/uri.h b/include/qemu/uri.h index b43f35a6a6..2875c51417 100644 --- a/include/qemu/uri.h +++ b/include/qemu/uri.h @@ -96,7 +96,7 @@ typedef struct QueryParams { QueryParam *p; /* array of parameters */ } QueryParams; =20 -struct QueryParams *query_params_new (int init_alloc); +QueryParams *query_params_new (int init_alloc); extern QueryParams *query_params_parse (const char *query); extern void query_params_free (QueryParams *ps); =20 --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; 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Thu, 31 Aug 2023 05:57:13 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Warner Losh , Kyle Evans , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Stefano Stabellini , Anthony Perard , Paul Durrant , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Andrew Jeffery , Joel Stanley , Tyrone Ting , Hao Wu , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Stefan Weil , Riku Voipio , Marcelo Tosatti , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , xen-devel@lists.xenproject.org, kvm@vger.kernel.org Subject: [PULL 04/41] bulk: Do not declare function prototypes using 'extern' keyword Date: Thu, 31 Aug 2023 14:56:06 +0200 Message-ID: <20230831125646.67855-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693486678621100001 By default, C function prototypes declared in headers are visible, so there is no need to declare them as 'extern' functions. Remove this redundancy in a single bulk commit; do not modify: - meson.build (used to check function availability at runtime) - pc-bios/ - libdecnumber/ - tests/ - *.c Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Message-Id: <20230605175647.88395-5-philmd@linaro.org> --- bsd-user/bsd-file.h | 6 ++--- crypto/hmacpriv.h | 13 +++++------ hw/xen/xen_pt.h | 8 +++---- include/crypto/secret_common.h | 14 +++++------- include/exec/page-vary.h | 4 ++-- include/hw/misc/aspeed_scu.h | 2 +- include/hw/nvram/npcm7xx_otp.h | 4 ++-- include/hw/qdev-core.h | 4 ++-- include/qemu/crc-ccitt.h | 4 ++-- include/qemu/osdep.h | 4 ++-- include/qemu/rcu.h | 14 ++++++------ include/qemu/sys_membarrier.h | 4 ++-- include/qemu/uri.h | 6 ++--- include/sysemu/accel-blocker.h | 14 ++++++------ include/sysemu/os-win32.h | 4 ++-- include/user/safe-syscall.h | 4 ++-- target/i386/sev.h | 6 ++--- target/mips/cpu.h | 4 ++-- tcg/tcg-internal.h | 4 ++-- include/exec/memory_ldst.h.inc | 42 +++++++++++++++++----------------- 20 files changed, 79 insertions(+), 86 deletions(-) diff --git a/bsd-user/bsd-file.h b/bsd-user/bsd-file.h index 588e0c50d4..3c00dc0056 100644 --- a/bsd-user/bsd-file.h +++ b/bsd-user/bsd-file.h @@ -51,10 +51,8 @@ do { \ unlock_user(p1, arg1, 0); \ } while (0) =20 -extern struct iovec *lock_iovec(int type, abi_ulong target_addr, int count, - int copy); -extern void unlock_iovec(struct iovec *vec, abi_ulong target_addr, int cou= nt, - int copy); +struct iovec *lock_iovec(int type, abi_ulong target_addr, int count, int c= opy); +void unlock_iovec(struct iovec *vec, abi_ulong target_addr, int count, int= copy); =20 int safe_open(const char *path, int flags, mode_t mode); int safe_openat(int fd, const char *path, int flags, mode_t mode); diff --git a/crypto/hmacpriv.h b/crypto/hmacpriv.h index 4387ca2587..62dfe8257a 100644 --- a/crypto/hmacpriv.h +++ b/crypto/hmacpriv.h @@ -28,19 +28,18 @@ struct QCryptoHmacDriver { void (*hmac_free)(QCryptoHmac *hmac); }; =20 -extern void *qcrypto_hmac_ctx_new(QCryptoHashAlgorithm alg, - const uint8_t *key, size_t nkey, - Error **errp); +void *qcrypto_hmac_ctx_new(QCryptoHashAlgorithm alg, + const uint8_t *key, size_t nkey, + Error **errp); extern QCryptoHmacDriver qcrypto_hmac_lib_driver; =20 #ifdef CONFIG_AF_ALG =20 #include "afalgpriv.h" =20 -extern QCryptoAFAlg * -qcrypto_afalg_hmac_ctx_new(QCryptoHashAlgorithm alg, - const uint8_t *key, size_t nkey, - Error **errp); +QCryptoAFAlg *qcrypto_afalg_hmac_ctx_new(QCryptoHashAlgorithm alg, + const uint8_t *key, size_t nkey, + Error **errp); extern QCryptoHmacDriver qcrypto_hmac_afalg_driver; =20 #endif diff --git a/hw/xen/xen_pt.h b/hw/xen/xen_pt.h index b20744f7c7..31bcfdf705 100644 --- a/hw/xen/xen_pt.h +++ b/hw/xen/xen_pt.h @@ -340,11 +340,9 @@ static inline bool xen_pt_has_msix_mapping(XenPCIPasst= hroughState *s, int bar) return s->msix && s->msix->bar_index =3D=3D bar; } =20 -extern void *pci_assign_dev_load_option_rom(PCIDevice *dev, - int *size, - unsigned int domain, - unsigned int bus, unsigned int= slot, - unsigned int function); +void *pci_assign_dev_load_option_rom(PCIDevice *dev, int *size, + unsigned int domain, unsigned int bus, + unsigned int slot, unsigned int funct= ion); static inline bool is_igd_vga_passthrough(XenHostPCIDevice *dev) { return (xen_igd_gfx_pt_enabled() diff --git a/include/crypto/secret_common.h b/include/crypto/secret_common.h index 42c7ff7af6..a0a22e1abd 100644 --- a/include/crypto/secret_common.h +++ b/include/crypto/secret_common.h @@ -48,13 +48,11 @@ struct QCryptoSecretCommonClass { }; =20 =20 -extern int qcrypto_secret_lookup(const char *secretid, - uint8_t **data, - size_t *datalen, - Error **errp); -extern char *qcrypto_secret_lookup_as_utf8(const char *secretid, - Error **errp); -extern char *qcrypto_secret_lookup_as_base64(const char *secretid, - Error **errp); +int qcrypto_secret_lookup(const char *secretid, + uint8_t **data, + size_t *datalen, + Error **errp); +char *qcrypto_secret_lookup_as_utf8(const char *secretid, Error **errp); +char *qcrypto_secret_lookup_as_base64(const char *secretid, Error **errp); =20 #endif /* QCRYPTO_SECRET_COMMON_H */ diff --git a/include/exec/page-vary.h b/include/exec/page-vary.h index ebbe9b169b..54ddde308a 100644 --- a/include/exec/page-vary.h +++ b/include/exec/page-vary.h @@ -27,8 +27,8 @@ typedef struct { } TargetPageBits; =20 #ifdef IN_PAGE_VARY -extern bool set_preferred_target_page_bits_common(int bits); -extern void finalize_target_page_bits_common(int min); +bool set_preferred_target_page_bits_common(int bits); +void finalize_target_page_bits_common(int min); #endif =20 /** diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index 5c7c04eedf..7cb6018dbc 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -51,7 +51,7 @@ struct AspeedSCUState { =20 #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) =3D=3D 0x= 04) =20 -extern bool is_supported_silicon_rev(uint32_t silicon_rev); +bool is_supported_silicon_rev(uint32_t silicon_rev); =20 =20 struct AspeedSCUClass { diff --git a/include/hw/nvram/npcm7xx_otp.h b/include/hw/nvram/npcm7xx_otp.h index 156bbd151a..ea4b5d0731 100644 --- a/include/hw/nvram/npcm7xx_otp.h +++ b/include/hw/nvram/npcm7xx_otp.h @@ -73,7 +73,7 @@ typedef struct NPCM7xxOTPClass NPCM7xxOTPClass; * Each nibble of data is encoded into a byte, so the number of bytes writ= ten * to the array will be @len * 2. */ -extern void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data, - unsigned int offset, unsigned int len); +void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data, + unsigned int offset, unsigned int len); =20 #endif /* NPCM7XX_OTP_H */ diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 884c726a87..151d968238 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -1086,7 +1086,7 @@ typedef enum MachineInitPhase { PHASE_MACHINE_READY, } MachineInitPhase; =20 -extern bool phase_check(MachineInitPhase phase); -extern void phase_advance(MachineInitPhase phase); +bool phase_check(MachineInitPhase phase); +void phase_advance(MachineInitPhase phase); =20 #endif diff --git a/include/qemu/crc-ccitt.h b/include/qemu/crc-ccitt.h index d6eb49146d..8918dafe07 100644 --- a/include/qemu/crc-ccitt.h +++ b/include/qemu/crc-ccitt.h @@ -17,8 +17,8 @@ extern uint16_t const crc_ccitt_table[256]; extern uint16_t const crc_ccitt_false_table[256]; =20 -extern uint16_t crc_ccitt(uint16_t crc, const uint8_t *buffer, size_t len); -extern uint16_t crc_ccitt_false(uint16_t crc, const uint8_t *buffer, size_= t len); +uint16_t crc_ccitt(uint16_t crc, const uint8_t *buffer, size_t len); +uint16_t crc_ccitt_false(uint16_t crc, const uint8_t *buffer, size_t len); =20 static inline uint16_t crc_ccitt_byte(uint16_t crc, const uint8_t c) { diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 2cae135280..2897720fac 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -250,7 +250,7 @@ extern "C" { * supports QEMU_ERROR, this will be reported at compile time; otherwise * this will be reported at link time due to the missing symbol. */ -G_NORETURN extern +G_NORETURN void QEMU_ERROR("code path is reachable") qemu_build_not_reached_always(void); #if defined(__OPTIMIZE__) && !defined(__NO_INLINE__) @@ -506,7 +506,7 @@ void qemu_anon_ram_free(void *ptr, size_t size); * See MySQL bug #7156 (http://bugs.mysql.com/bug.php?id=3D7156) for discu= ssion * about Solaris missing the madvise() prototype. */ -extern int madvise(char *, size_t, int); +int madvise(char *, size_t, int); #endif =20 #if defined(CONFIG_LINUX) diff --git a/include/qemu/rcu.h b/include/qemu/rcu.h index 661c1a1468..fea058aa9f 100644 --- a/include/qemu/rcu.h +++ b/include/qemu/rcu.h @@ -118,19 +118,19 @@ static inline void rcu_read_unlock(void) } } =20 -extern void synchronize_rcu(void); +void synchronize_rcu(void); =20 /* * Reader thread registration. */ -extern void rcu_register_thread(void); -extern void rcu_unregister_thread(void); +void rcu_register_thread(void); +void rcu_unregister_thread(void); =20 /* * Support for fork(). fork() support is enabled at startup. */ -extern void rcu_enable_atfork(void); -extern void rcu_disable_atfork(void); +void rcu_enable_atfork(void); +void rcu_disable_atfork(void); =20 struct rcu_head; typedef void RCUCBFunc(struct rcu_head *head); @@ -140,8 +140,8 @@ struct rcu_head { RCUCBFunc *func; }; =20 -extern void call_rcu1(struct rcu_head *head, RCUCBFunc *func); -extern void drain_call_rcu(void); +void call_rcu1(struct rcu_head *head, RCUCBFunc *func); +void drain_call_rcu(void); =20 /* The operands of the minus operator must have the same type, * which must be the one that we specify in the cast. diff --git a/include/qemu/sys_membarrier.h b/include/qemu/sys_membarrier.h index b5bfa21d52..e7774891f8 100644 --- a/include/qemu/sys_membarrier.h +++ b/include/qemu/sys_membarrier.h @@ -14,8 +14,8 @@ * side. The slow side forces processor-level ordering on all other cores * through a system call. */ -extern void smp_mb_global_init(void); -extern void smp_mb_global(void); +void smp_mb_global_init(void); +void smp_mb_global(void); #define smp_mb_placeholder() barrier() #else /* Keep it simple, execute a real memory barrier on both sides. */ diff --git a/include/qemu/uri.h b/include/qemu/uri.h index 2875c51417..1855b764f2 100644 --- a/include/qemu/uri.h +++ b/include/qemu/uri.h @@ -96,8 +96,8 @@ typedef struct QueryParams { QueryParam *p; /* array of parameters */ } QueryParams; =20 -QueryParams *query_params_new (int init_alloc); -extern QueryParams *query_params_parse (const char *query); -extern void query_params_free (QueryParams *ps); +QueryParams *query_params_new(int init_alloc); +QueryParams *query_params_parse(const char *query); +void query_params_free(QueryParams *ps); =20 #endif /* QEMU_URI_H */ diff --git a/include/sysemu/accel-blocker.h b/include/sysemu/accel-blocker.h index 0733783bcc..f07f368358 100644 --- a/include/sysemu/accel-blocker.h +++ b/include/sysemu/accel-blocker.h @@ -16,7 +16,7 @@ =20 #include "sysemu/cpus.h" =20 -extern void accel_blocker_init(void); +void accel_blocker_init(void); =20 /* * accel_{cpu_}ioctl_begin/end: @@ -26,10 +26,10 @@ extern void accel_blocker_init(void); * called, preventing new ioctls to run. They will continue only after * accel_ioctl_inibith_end(). */ -extern void accel_ioctl_begin(void); -extern void accel_ioctl_end(void); -extern void accel_cpu_ioctl_begin(CPUState *cpu); -extern void accel_cpu_ioctl_end(CPUState *cpu); +void accel_ioctl_begin(void); +void accel_ioctl_end(void); +void accel_cpu_ioctl_begin(CPUState *cpu); +void accel_cpu_ioctl_end(CPUState *cpu); =20 /* * accel_ioctl_inhibit_begin: start critical section @@ -42,7 +42,7 @@ extern void accel_cpu_ioctl_end(CPUState *cpu); * This allows the caller to access shared data or perform operations with= out * worrying of concurrent vcpus accesses. */ -extern void accel_ioctl_inhibit_begin(void); +void accel_ioctl_inhibit_begin(void); =20 /* * accel_ioctl_inhibit_end: end critical section started by @@ -50,6 +50,6 @@ extern void accel_ioctl_inhibit_begin(void); * * This function allows blocked accel_{cpu_}ioctl_begin() to continue. */ -extern void accel_ioctl_inhibit_end(void); +void accel_ioctl_inhibit_end(void); =20 #endif /* ACCEL_BLOCKER_H */ diff --git a/include/sysemu/os-win32.h b/include/sysemu/os-win32.h index 91aa0d7ec0..83104e332f 100644 --- a/include/sysemu/os-win32.h +++ b/include/sysemu/os-win32.h @@ -66,8 +66,8 @@ extern "C" { * setjmp to _setjmpex instead. However, they are still defined in libming= wex.a, * which gets linked automatically. */ -extern int __mingw_setjmp(jmp_buf); -extern void __attribute__((noreturn)) __mingw_longjmp(jmp_buf, int); +int __mingw_setjmp(jmp_buf); +void __attribute__((noreturn)) __mingw_longjmp(jmp_buf, int); #define setjmp(env) __mingw_setjmp(env) #define longjmp(env, val) __mingw_longjmp(env, val) #elif defined(_WIN64) diff --git a/include/user/safe-syscall.h b/include/user/safe-syscall.h index 195cedac04..27b71cdbd8 100644 --- a/include/user/safe-syscall.h +++ b/include/user/safe-syscall.h @@ -126,8 +126,8 @@ */ =20 /* The core part of this function is implemented in assembly */ -extern long safe_syscall_base(int *pending, long number, ...); -extern long safe_syscall_set_errno_tail(int value); +long safe_syscall_base(int *pending, long number, ...); +long safe_syscall_set_errno_tail(int value); =20 /* These are defined by the safe-syscall.inc.S file */ extern char safe_syscall_start[]; diff --git a/target/i386/sev.h b/target/i386/sev.h index 7b1528248a..e7499c95b1 100644 --- a/target/i386/sev.h +++ b/target/i386/sev.h @@ -46,9 +46,9 @@ bool sev_es_enabled(void); #define sev_es_enabled() 0 #endif =20 -extern uint32_t sev_get_cbit_position(void); -extern uint32_t sev_get_reduced_phys_bits(void); -extern bool sev_add_kernel_loader_hashes(SevKernelLoaderContext *ctx, Erro= r **errp); +uint32_t sev_get_cbit_position(void); +uint32_t sev_get_reduced_phys_bits(void); +bool sev_add_kernel_loader_hashes(SevKernelLoaderContext *ctx, Error **err= p); =20 int sev_encrypt_flash(uint8_t *ptr, uint64_t len, Error **errp); int sev_inject_launch_secret(const char *hdr, const char *secret, diff --git a/target/mips/cpu.h b/target/mips/cpu.h index f81bd06f5e..6d6af1f2a8 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1224,8 +1224,8 @@ void mips_cpu_list(void); =20 #define cpu_list mips_cpu_list =20 -extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); -extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); +void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); +uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); =20 /* * MMU modes definitions. We carefully match the indices with our diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index fbe62b31b8..40a69e6e6e 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -64,8 +64,8 @@ static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) return temp_tcgv_i32(tcgv_i64_temp(t) + !HOST_BIG_ENDIAN); } #else -extern TCGv_i32 TCGV_LOW(TCGv_i64) QEMU_ERROR("32-bit code path is reachab= le"); -extern TCGv_i32 TCGV_HIGH(TCGv_i64) QEMU_ERROR("32-bit code path is reacha= ble"); +TCGv_i32 TCGV_LOW(TCGv_i64) QEMU_ERROR("32-bit code path is reachable"); +TCGv_i32 TCGV_HIGH(TCGv_i64) QEMU_ERROR("32-bit code path is reachable"); #endif =20 static inline TCGv_i64 TCGV128_LOW(TCGv_i128 t) diff --git a/include/exec/memory_ldst.h.inc b/include/exec/memory_ldst.h.inc index 7c3a641f7e..92ad74e956 100644 --- a/include/exec/memory_ldst.h.inc +++ b/include/exec/memory_ldst.h.inc @@ -20,48 +20,48 @@ */ =20 #ifdef TARGET_ENDIANNESS -extern uint16_t glue(address_space_lduw, SUFFIX)(ARG1_DECL, +uint16_t glue(address_space_lduw, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL, +uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL, +uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL, +void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stw, SUFFIX)(ARG1_DECL, +void glue(address_space_stw, SUFFIX)(ARG1_DECL, hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stl, SUFFIX)(ARG1_DECL, +void glue(address_space_stl, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stq, SUFFIX)(ARG1_DECL, +void glue(address_space_stq, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result); #else -extern uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, +uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint16_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL, +uint16_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint16_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL, +uint16_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL, +uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint32_t glue(address_space_ldl_be, SUFFIX)(ARG1_DECL, +uint32_t glue(address_space_ldl_be, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL, +uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL, +uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stb, SUFFIX)(ARG1_DECL, +void glue(address_space_stb, SUFFIX)(ARG1_DECL, hwaddr addr, uint8_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stw_le, SUFFIX)(ARG1_DECL, +void glue(address_space_stw_le, SUFFIX)(ARG1_DECL, hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stw_be, SUFFIX)(ARG1_DECL, +void glue(address_space_stw_be, SUFFIX)(ARG1_DECL, hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stl_le, SUFFIX)(ARG1_DECL, +void glue(address_space_stl_le, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stl_be, SUFFIX)(ARG1_DECL, +void glue(address_space_stl_be, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stq_le, SUFFIX)(ARG1_DECL, +void glue(address_space_stq_le, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stq_be, SUFFIX)(ARG1_DECL, +void glue(address_space_stq_be, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result); #endif =20 --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693486738; cv=none; d=zohomail.com; s=zohoarc; b=AZmsfweplB6GsjjxLY1QW+0utR8eNo1O4+ORIC4za60CtKcaYLMvn8ofgmhVdhQ9GepGXhYAeDWshEmwkExhUfhar1Vjq2WZ8apwySG0nsI5ON5qJHU3xsEOFBOoOs6fe5/NRQ5IqOFWEEbGtGIsyYKvJaEuHK5S4weyWoK7bmk= ARC-Message-Signature: i=1; a=rsa-sha256; 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Thu, 31 Aug 2023 05:57:18 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Helge Deller , Jason Wang Subject: [PULL 05/41] hw/net/i82596: Include missing 'exec/address-spaces.h' header Date: Thu, 31 Aug 2023 14:56:07 +0200 Message-ID: <20230831125646.67855-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693486740509100003 hw/net/i82596.c access the global 'address_space_memory' calling the ld/st_phys() API. address_space_memory is declared in "exec/address-spaces.h". Currently this header is indirectly pulled in via another header. Explicitly include it to avoid when refactoring unrelated headers: hw/net/i82596.c:91:23: error: use of undeclared identifier 'address_space= _memory'; did you mean 'address_space_destroy'? return ldub_phys(&address_space_memory, addr); ^~~~~~~~~~~~~~~~~~~~ address_space_destroy Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20230619074153.44268-2-philmd@linaro.org> --- hw/net/i82596.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/net/i82596.c b/hw/net/i82596.c index ab26f8bea1..6defa9d3a1 100644 --- a/hw/net/i82596.c +++ b/hw/net/i82596.c @@ -15,6 +15,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" +#include "exec/address-spaces.h" #include "qemu/module.h" #include "trace.h" #include "i82596.h" --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Iglesias" Subject: [PULL 06/41] hw/dma/etraxfs: Include missing 'exec/memory.h' header Date: Thu, 31 Aug 2023 14:56:08 +0200 Message-ID: <20230831125646.67855-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487091167100001 The 'fs_dma_ctrl' structure has a MemoryRegion 'mmio' field which is initialized in etraxfs_dmac_init() calling memory_region_init_io() and memory_region_add_subregion(). These functions are declared in "exec/memory.h", along with the MemoryRegion structure. Include the missing header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20230619074153.44268-3-philmd@linaro.org> --- hw/dma/etraxfs_dma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/dma/etraxfs_dma.c b/hw/dma/etraxfs_dma.c index a1068b19ea..9c0003de51 100644 --- a/hw/dma/etraxfs_dma.c +++ b/hw/dma/etraxfs_dma.c @@ -28,6 +28,7 @@ #include "qemu/main-loop.h" #include "sysemu/runstate.h" #include "exec/address-spaces.h" +#include "exec/memory.h" =20 #include "hw/cris/etraxfs_dma.h" =20 --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693487504; cv=none; d=zohomail.com; s=zohoarc; b=GEDV/OeevvDxri2qeZxfFsRa+hksaWRodFoaNpejly/8CcICTTI3masBDHWQRd90xMRxxts+uXv9J6f9jFFKamFE/N6PLwzgtiVtaS0xRiQTNa0RHeJAtmYlEfLPP3ixLifRPNTSbSyCsZnH0ULzziRMFxrL+j3QJ8CdYVg1o0s= ARC-Message-Signature: i=1; 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Thu, 31 Aug 2023 05:57:29 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 07/41] exec/address-spaces.h: Remove unuseful 'exec/memory.h' include Date: Thu, 31 Aug 2023 14:56:09 +0200 Message-ID: <20230831125646.67855-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487565563100001 "exec/address-spaces.h" declares get_system_io() and get_system_memory(), both returning a MemoryRegion pointer. MemoryRegion is forward declared in "qemu/typedefs.h", so we don't need any declaration from "exec/memory.h" here. Remove it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20230619074153.44268-4-philmd@linaro.org> --- include/exec/address-spaces.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/exec/address-spaces.h b/include/exec/address-spaces.h index db8bfa9a92..0d0aa61d68 100644 --- a/include/exec/address-spaces.h +++ b/include/exec/address-spaces.h @@ -19,8 +19,6 @@ * you're one of them. */ =20 -#include "exec/memory.h" - #ifndef CONFIG_USER_ONLY =20 /* Get the root memory region. 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Thu, 31 Aug 2023 05:57:35 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , David Gibson , Greg Kurz , Nicholas Piggin Subject: [PULL 08/41] target/ppc/pmu: Include missing 'qemu/timer.h' header Date: Thu, 31 Aug 2023 14:56:10 +0200 Message-ID: <20230831125646.67855-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693486868585100001 Since commit c2eff582a3 ("target/ppc: PMU basic cycle count for pseries TCG") pmu_update_cycles() uses QEMU_CLOCK_VIRTUAL and calls qemu_clock_get_ns(), both defined in "qemu/timer.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20230828221314.18435-2-philmd@linaro.org> --- target/ppc/power8-pmu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 7bb4bf81f7..2537cded83 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -16,6 +16,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" +#include "qemu/timer.h" #include "qemu/main-loop.h" #include "hw/ppc/ppc.h" #include "power8-pmu.h" --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693487323; cv=none; d=zohomail.com; s=zohoarc; b=QD+P3LGO/C5tXggrjH8hwELetubHJKZfurgXeHgVo3YYXX8bYWJIzJN82zGvSsbw2DP/xvHTKwWixVGDSbXSHJ0tjcA2go82zEPPqfs+JTq3kYtCL/udNGGqTntvzaSG65NHYNsDCO4EeoU8rHloLbhbdbt/gQiHGG/Jfl0FDUs= ARC-Message-Signature: i=1; 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Thu, 31 Aug 2023 05:57:41 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PULL 09/41] target/riscv/pmu: Restrict 'qemu/log.h' include to source Date: Thu, 31 Aug 2023 14:56:11 +0200 Message-ID: <20230831125646.67855-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20230828221314.18435-3-philmd@linaro.org> --- target/riscv/pmu.h | 1 - target/riscv/pmu.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 0c819ca983..d2be06a133 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -16,7 +16,6 @@ * this program. If not, see . */ =20 -#include "qemu/log.h" #include "cpu.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index db06b3882f..36f6307d28 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -17,6 +17,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" #include "cpu.h" #include "pmu.h" #include "sysemu/cpu-timers.h" --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693487511; cv=none; d=zohomail.com; s=zohoarc; b=c8S5rYTozfN+Psu3W0KGG8qUnRIDIZYdfNhJxXtFt0KcdD5PuEl8mDNkNGuDO//GSxAbRh3givANhmsjZWsZGEZw4b4rttskxZHTZUz/fmNY54i/1jq7kkU2UYxgKvZfzrKYVoTdL+PAeCdAWwZnkFzsW9XzpKAptaSi2AIM6P0= ARC-Message-Signature: i=1; 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Thu, 31 Aug 2023 05:57:47 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Michael Rolnik , Paolo Bonzini , Eduardo Habkost , Song Gao , Xiaojuan Yang , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PULL 10/41] target/translate: Include missing 'exec/cpu_ldst.h' header Date: Thu, 31 Aug 2023 14:56:12 +0200 Message-ID: <20230831125646.67855-11-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487526326100001 All these files access the CPU LD/ST API declared in "exec/cpu_ldst.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20230828221314.18435-4-philmd@linaro.org> --- target/avr/helper.c | 1 + target/i386/tcg/fpu_helper.c | 1 + target/i386/tcg/sysemu/excp_helper.c | 1 + target/loongarch/cpu.c | 1 + target/mips/tcg/ldst_helper.c | 1 + target/mips/tcg/msa_helper.c | 1 + target/riscv/op_helper.c | 1 + target/riscv/vector_helper.c | 1 + 8 files changed, 8 insertions(+) diff --git a/target/avr/helper.c b/target/avr/helper.c index e6e7d51487..fdc9884ea0 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -24,6 +24,7 @@ #include "cpu.h" #include "hw/core/tcg-cpu-ops.h" #include "exec/exec-all.h" +#include "exec/cpu_ldst.h" #include "exec/address-spaces.h" #include "exec/helper-proto.h" =20 diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 6f3741b635..4430d3d380 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -21,6 +21,7 @@ #include #include "cpu.h" #include "tcg-cpu.h" +#include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" #include "fpu/softfloat-macros.h" diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index b5f0abffa3..226689a4f2 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "tcg/helper-tcg.h" =20 diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 27fc6e1f33..65f9320e34 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -11,6 +11,7 @@ #include "qapi/error.h" #include "qemu/module.h" #include "sysemu/qtest.h" +#include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "cpu.h" #include "internals.h" diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index c1a8380e34..97056d00a2 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -24,6 +24,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/cpu_ldst.h" #include "exec/memop.h" #include "internal.h" =20 diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 29b31d70fe..c8597b9e30 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -22,6 +22,7 @@ #include "internal.h" #include "tcg/tcg.h" #include "exec/exec-all.h" +#include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "exec/memop.h" #include "fpu/softfloat.h" diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 9cdb9cdd06..7e2f1908ee 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -23,6 +23,7 @@ #include "internals.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" +#include "exec/cpu_ldst.h" #include "exec/helper-proto.h" =20 /* Exceptions processing helpers */ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index bf7e0029a1..bc9e151aa9 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/memop.h" #include "exec/exec-all.h" +#include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" #include "tcg/tcg-gvec-desc.h" --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Iglesias" , Chris Wulff , Marek Vasut , Stafford Horne , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , David Gibson , Greg Kurz , Nicholas Piggin , Yoshinori Sato , Mark Cave-Ayland , Artyom Tarasenko Subject: [PULL 11/41] target/translate: Remove unnecessary 'exec/cpu_ldst.h' header Date: Thu, 31 Aug 2023 14:56:13 +0200 Message-ID: <20230831125646.67855-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487486721100001 All these files only access the translator_ld/st API declared in "exec/translator.h". The CPU ld/st API from declared in "exec/cpu_ldst.h" is not used, remove it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20230828221314.18435-5-philmd@linaro.org> --- target/alpha/translate.c | 1 - target/hexagon/translate.c | 1 - target/hppa/translate.c | 1 - target/m68k/translate.c | 1 - target/microblaze/translate.c | 1 - target/nios2/translate.c | 1 - target/openrisc/translate.c | 1 - target/ppc/translate.c | 1 - target/sh4/translate.c | 1 - target/sparc/translate.c | 1 - 10 files changed, 10 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 0839182a1f..9be912c50c 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -24,7 +24,6 @@ #include "qemu/host-utils.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" -#include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "exec/translator.h" diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 708339198e..c00254e4d5 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -23,7 +23,6 @@ #include "exec/helper-gen.h" #include "exec/helper-proto.h" #include "exec/translation-block.h" -#include "exec/cpu_ldst.h" #include "exec/log.h" #include "internal.h" #include "attribs.h" diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e3af668252..c04dc15228 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -23,7 +23,6 @@ #include "qemu/host-utils.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" -#include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "exec/translator.h" diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 15b3701b8f..9e224fe796 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -25,7 +25,6 @@ #include "tcg/tcg-op.h" #include "qemu/log.h" #include "qemu/qemu-print.h" -#include "exec/cpu_ldst.h" #include "exec/translator.h" =20 #include "exec/helper-proto.h" diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7e7f837c63..d02c16296a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -24,7 +24,6 @@ #include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" #include "exec/helper-gen.h" #include "exec/translator.h" #include "qemu/qemu-print.h" diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 4264c7ec6b..dfc546d3bb 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -29,7 +29,6 @@ #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "exec/log.h" -#include "exec/cpu_ldst.h" #include "exec/translator.h" #include "qemu/qemu-print.h" #include "semihosting/semihost.h" diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 7c6f80daf1..d65758449f 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -26,7 +26,6 @@ #include "qemu/log.h" #include "qemu/bitops.h" #include "qemu/qemu-print.h" -#include "exec/cpu_ldst.h" #include "exec/translator.h" =20 #include "exec/helper-proto.h" diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 74796ec7ba..49b6a757b7 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -27,7 +27,6 @@ #include "tcg/tcg-op-gvec.h" #include "qemu/host-utils.h" #include "qemu/main-loop.h" -#include "exec/cpu_ldst.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 49c87d7a01..c1e590feb3 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -22,7 +22,6 @@ #include "disas/disas.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" -#include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "exec/translator.h" diff --git a/target/sparc/translate.c b/target/sparc/translate.c index fa80a91161..3bf0ab8135 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -25,7 +25,6 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" -#include "exec/cpu_ldst.h" =20 #include "exec/helper-gen.h" =20 --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 31 Aug 2023 05:57:59 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Subject: [PULL 12/41] target/translate: Restrict 'exec/cpu_ldst.h' to user emulation Date: Thu, 31 Aug 2023 14:56:14 +0200 Message-ID: <20230831125646.67855-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20230828221314.18435-6-philmd@linaro.org> --- include/exec/exec-all.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index d02517e95f..b2f5cd4c2a 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -21,7 +21,7 @@ #define EXEC_ALL_H =20 #include "cpu.h" -#ifdef CONFIG_TCG +#if defined(CONFIG_USER_ONLY) #include "exec/cpu_ldst.h" #endif #include "exec/translation-block.h" --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693486858; cv=none; d=zohomail.com; s=zohoarc; b=CHwHEx52/h5xYqpLoQ27CNl8wUBI54IsG3ND3ysUFqQbKAbG+E95IYJ770KvknmHuFnvRxDBA6Kw2a2/TS+a5PEoqMnrzDZLa+Lqn8LoQa8OV0ky5orz+dqK90j8nZnT8e5MEdS3DEEto9Nmiigg3q6TMutwm5uhhNIkqMQ0bZo= ARC-Message-Signature: i=1; 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Thu, 31 Aug 2023 05:58:05 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , "Edgar E. Iglesias" , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Max Filippov Subject: [PULL 13/41] target/helpers: Remove unnecessary 'exec/cpu_ldst.h' header Date: Thu, 31 Aug 2023 14:56:15 +0200 Message-ID: <20230831125646.67855-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693486876838100001 These files don't use the CPU ld/st API, remove the unnecessary "exec/cpu_ldst.h" header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20230828221314.18435-7-philmd@linaro.org> --- target/riscv/pmu.h | 1 - target/cris/op_helper.c | 1 - target/mips/tcg/fpu_helper.c | 1 - target/mips/tcg/sysemu/lcsr_helper.c | 1 - target/s390x/tcg/excp_helper.c | 1 - target/s390x/tcg/fpu_helper.c | 1 - target/xtensa/mmu_helper.c | 1 - target/xtensa/op_helper.c | 1 - 8 files changed, 8 deletions(-) diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index d2be06a133..60fdd6f42c 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -18,7 +18,6 @@ =20 #include "cpu.h" #include "qemu/main-loop.h" -#include "exec/exec-all.h" =20 bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, uint32_t target_ctr); diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c index 40cb74ce73..98a9aaf504 100644 --- a/target/cris/op_helper.c +++ b/target/cris/op_helper.c @@ -24,7 +24,6 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" =20 //#define CRIS_OP_HELPER_DEBUG =20 diff --git a/target/mips/tcg/fpu_helper.c b/target/mips/tcg/fpu_helper.c index 8ce56ed7c8..45d593de48 100644 --- a/target/mips/tcg/fpu_helper.c +++ b/target/mips/tcg/fpu_helper.c @@ -25,7 +25,6 @@ #include "internal.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" #include "fpu/softfloat.h" #include "fpu_helper.h" =20 diff --git a/target/mips/tcg/sysemu/lcsr_helper.c b/target/mips/tcg/sysemu/= lcsr_helper.c index 942143d209..8f97d04313 100644 --- a/target/mips/tcg/sysemu/lcsr_helper.c +++ b/target/mips/tcg/sysemu/lcsr_helper.c @@ -13,7 +13,6 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" =20 #define GET_MEMTXATTRS(cas) \ ((MemTxAttrs){.requester_id =3D env_cpu(cas)->cpu_index}) diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index b7116d0577..b875bf14e5 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -23,7 +23,6 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" #include "s390x-internal.h" #include "tcg_s390x.h" #ifndef CONFIG_USER_ONLY diff --git a/target/s390x/tcg/fpu_helper.c b/target/s390x/tcg/fpu_helper.c index c329b31261..d8bd5748fa 100644 --- a/target/s390x/tcg/fpu_helper.c +++ b/target/s390x/tcg/fpu_helper.c @@ -23,7 +23,6 @@ #include "s390x-internal.h" #include "tcg_s390x.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" =20 diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index fa66e8e867..57b75882c4 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -34,7 +34,6 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" =20 #define XTENSA_MPU_SEGMENT_MASK 0x0000001f #define XTENSA_MPU_ACC_RIGHTS_MASK 0x00000f00 diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index 1af7becc54..10a2b51f91 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -31,7 +31,6 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" #include "qemu/timer.h" =20 #ifndef CONFIG_USER_ONLY --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 31 Aug 2023 05:58:11 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Song Gao , Xiaojuan Yang , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , David Gibson , Greg Kurz , Nicholas Piggin , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Max Filippov Subject: [PULL 14/41] target/helpers: Remove unnecessary 'qemu/main-loop.h' header Date: Thu, 31 Aug 2023 14:56:16 +0200 Message-ID: <20230831125646.67855-15-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487593980100001 "qemu/main-loop.h" declares functions related to QEMU's main loop mutex, which these files don't access. Remove the unused "qemu/main-loop.h" header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20230828221314.18435-8-philmd@linaro.org> --- target/riscv/pmu.h | 1 - target/loongarch/iocsr_helper.c | 1 - target/loongarch/op_helper.c | 1 - target/mips/tcg/sysemu/lcsr_helper.c | 1 - target/nios2/op_helper.c | 1 - target/ppc/int_helper.c | 1 - target/ppc/machine.c | 1 - target/ppc/mem_helper.c | 1 - target/ppc/mmu_common.c | 1 - target/ppc/mmu_helper.c | 1 - target/ppc/power8-pmu.c | 1 - target/ppc/translate.c | 1 - target/riscv/csr.c | 1 - target/riscv/m128_helper.c | 1 - target/riscv/op_helper.c | 1 - target/s390x/tcg/crypto_helper.c | 1 - target/s390x/tcg/misc_helper.c | 1 - target/xtensa/dbg_helper.c | 1 - target/xtensa/fpu_helper.c | 1 - target/xtensa/mmu_helper.c | 1 - target/xtensa/op_helper.c | 1 - target/xtensa/win_helper.c | 1 - 22 files changed, 22 deletions(-) diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 60fdd6f42c..2bfb71ba87 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -17,7 +17,6 @@ */ =20 #include "cpu.h" -#include "qemu/main-loop.h" =20 bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, uint32_t target_ctr); diff --git a/target/loongarch/iocsr_helper.c b/target/loongarch/iocsr_helpe= r.c index dda9845d6c..6cd01d5f09 100644 --- a/target/loongarch/iocsr_helper.c +++ b/target/loongarch/iocsr_helper.c @@ -6,7 +6,6 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c index cf84f20aba..fe79c62fa4 100644 --- a/target/loongarch/op_helper.c +++ b/target/loongarch/op_helper.c @@ -7,7 +7,6 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" diff --git a/target/mips/tcg/sysemu/lcsr_helper.c b/target/mips/tcg/sysemu/= lcsr_helper.c index 8f97d04313..fb57bcbb78 100644 --- a/target/mips/tcg/sysemu/lcsr_helper.c +++ b/target/mips/tcg/sysemu/lcsr_helper.c @@ -7,7 +7,6 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "internal.h" #include "qemu/host-utils.h" diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index 0aaf33ffc2..5017457c5e 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -22,7 +22,6 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "qemu/main-loop.h" =20 void helper_raise_exception(CPUNios2State *env, uint32_t index) { diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 834da80fe3..96cdb3c7e3 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -21,7 +21,6 @@ #include "cpu.h" #include "internal.h" #include "qemu/host-utils.h" -#include "qemu/main-loop.h" #include "qemu/log.h" #include "exec/helper-proto.h" #include "crypto/aes.h" diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 134b16c625..1270a1f7fc 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -7,7 +7,6 @@ #include "mmu-hash64.h" #include "migration/cpu.h" #include "qapi/error.h" -#include "qemu/main-loop.h" #include "kvm_ppc.h" #include "power8-pmu.h" =20 diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 46eae65819..c7535481d6 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -21,7 +21,6 @@ #include "cpu.h" #include "exec/exec-all.h" #include "qemu/host-utils.h" -#include "qemu/main-loop.h" #include "exec/helper-proto.h" #include "helper_regs.h" #include "exec/cpu_ldst.h" diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 8c000e250d..6ca5d12207 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -28,7 +28,6 @@ #include "exec/log.h" #include "helper_regs.h" #include "qemu/error-report.h" -#include "qemu/main-loop.h" #include "qemu/qemu-print.h" #include "internal.h" #include "mmu-book3s-v3.h" diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index d3ea7588f9..f87d35379a 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -28,7 +28,6 @@ #include "exec/log.h" #include "helper_regs.h" #include "qemu/error-report.h" -#include "qemu/main-loop.h" #include "qemu/qemu-print.h" #include "internal.h" #include "mmu-book3s-v3.h" diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 2537cded83..cbc5889d91 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -17,7 +17,6 @@ #include "exec/helper-proto.h" #include "qemu/error-report.h" #include "qemu/timer.h" -#include "qemu/main-loop.h" #include "hw/ppc/ppc.h" #include "power8-pmu.h" =20 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 49b6a757b7..7111b34030 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -26,7 +26,6 @@ #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "qemu/host-utils.h" -#include "qemu/main-loop.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ea7585329e..de31818daa 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -23,7 +23,6 @@ #include "cpu.h" #include "pmu.h" #include "time_helper.h" -#include "qemu/main-loop.h" #include "exec/exec-all.h" #include "exec/tb-flush.h" #include "sysemu/cpu-timers.h" diff --git a/target/riscv/m128_helper.c b/target/riscv/m128_helper.c index e6a4f6120a..ec14aaa901 100644 --- a/target/riscv/m128_helper.c +++ b/target/riscv/m128_helper.c @@ -19,7 +19,6 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "qemu/main-loop.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" =20 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 7e2f1908ee..5355225d56 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -21,7 +21,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internals.h" -#include "qemu/main-loop.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" diff --git a/target/s390x/tcg/crypto_helper.c b/target/s390x/tcg/crypto_hel= per.c index 762b277884..93aabd236f 100644 --- a/target/s390x/tcg/crypto_helper.c +++ b/target/s390x/tcg/crypto_helper.c @@ -13,7 +13,6 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/main-loop.h" #include "qemu/guest-random.h" #include "s390x-internal.h" #include "tcg_s390x.h" diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index 576157b1f3..e85658ce22 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -20,7 +20,6 @@ =20 #include "qemu/osdep.h" #include "qemu/cutils.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "s390x-internal.h" #include "qemu/host-utils.h" diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index ce2a820c60..3e0c9e8e8b 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -27,7 +27,6 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index d2a10cc797..381e83ded8 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -27,7 +27,6 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 57b75882c4..12552a3347 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -27,7 +27,6 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" -#include "qemu/main-loop.h" #include "qemu/qemu-print.h" #include "qemu/units.h" #include "cpu.h" diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index 10a2b51f91..03e2c1889a 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -26,7 +26,6 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" diff --git a/target/xtensa/win_helper.c b/target/xtensa/win_helper.c index 5a1555360a..ec9ff44db0 100644 --- a/target/xtensa/win_helper.c +++ b/target/xtensa/win_helper.c @@ -27,7 +27,6 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693487351; cv=none; d=zohomail.com; s=zohoarc; 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To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PULL 15/41] target/mips: Remove unused headers in lcsr_helper.c Date: Thu, 31 Aug 2023 14:56:17 +0200 Message-ID: <20230831125646.67855-16-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487385489100002 This files only access the address_space_ld/st API, declared in "exec/cpu-all.h", already included by "cpu.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20230828221314.18435-9-philmd@linaro.org> --- target/mips/tcg/sysemu/lcsr_helper.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/mips/tcg/sysemu/lcsr_helper.c b/target/mips/tcg/sysemu/= lcsr_helper.c index fb57bcbb78..25e03572fe 100644 --- a/target/mips/tcg/sysemu/lcsr_helper.c +++ b/target/mips/tcg/sysemu/lcsr_helper.c @@ -8,10 +8,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "internal.h" -#include "qemu/host-utils.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" =20 #define GET_MEMTXATTRS(cas) \ ((MemTxAttrs){.requester_id =3D env_cpu(cas)->cpu_index}) --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487553949100001 Since commit fa92bd4af7 ("target/xtensa: fix access to the INTERRUPT SR") these files use QEMU atomic API. Explicit the header inclusion instead of relying on implicit and indirect inclusion. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20230828221314.18435-10-philmd@linaro.org> --- hw/xtensa/pic_cpu.c | 1 + target/xtensa/exc_helper.c | 1 + target/xtensa/op_helper.c | 1 + 3 files changed, 3 insertions(+) diff --git a/hw/xtensa/pic_cpu.c b/hw/xtensa/pic_cpu.c index 6c9447565d..8cef88c61b 100644 --- a/hw/xtensa/pic_cpu.c +++ b/hw/xtensa/pic_cpu.c @@ -30,6 +30,7 @@ #include "hw/irq.h" #include "qemu/log.h" #include "qemu/timer.h" +#include "qemu/atomic.h" =20 void check_interrupts(CPUXtensaState *env) { diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index 43f6a862de..91354884f7 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -31,6 +31,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" +#include "qemu/atomic.h" #include "exec/exec-all.h" =20 void HELPER(exception)(CPUXtensaState *env, uint32_t excp) diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index 03e2c1889a..7bb8cd6726 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -30,6 +30,7 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" +#include "qemu/atomic.h" #include "qemu/timer.h" =20 #ifndef CONFIG_USER_ONLY --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 31 Aug 2023 05:58:28 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 17/41] qemu/processor: Remove unused 'qemu/atomic.h' header Date: Thu, 31 Aug 2023 14:56:19 +0200 Message-ID: <20230831125646.67855-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487531491100007 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20230828221314.18435-11-philmd@linaro.org> --- include/qemu/processor.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/qemu/processor.h b/include/qemu/processor.h index 8e16c9277d..9f0dcdf28f 100644 --- a/include/qemu/processor.h +++ b/include/qemu/processor.h @@ -7,8 +7,6 @@ #ifndef QEMU_PROCESSOR_H #define QEMU_PROCESSOR_H =20 -#include "qemu/atomic.h" - #if defined(__i386__) || defined(__x86_64__) # define cpu_relax() asm volatile("rep; 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Thu, 31 Aug 2023 05:58:33 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 18/41] exec/translation-block: Clean up includes Date: Thu, 31 Aug 2023 14:56:20 +0200 Message-ID: <20230831125646.67855-19-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487521829100001 'qemu/atomic.h' and 'exec/target_page.h' are not used. 'qemu/interval-tree.h' is only required for user emulation. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20230828221314.18435-12-philmd@linaro.org> --- include/exec/translation-block.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/exec/translation-block.h b/include/exec/translation-bl= ock.h index 5119924927..b785751774 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -7,11 +7,11 @@ #ifndef EXEC_TRANSLATION_BLOCK_H #define EXEC_TRANSLATION_BLOCK_H =20 -#include "qemu/atomic.h" #include "qemu/thread.h" -#include "qemu/interval-tree.h" #include "exec/cpu-common.h" -#include "exec/target_page.h" +#ifdef CONFIG_USER_ONLY +#include "qemu/interval-tree.h" +#endif =20 /* * Page tracking code uses ram addresses in system mode, and virtual --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487554208100003 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Marc-Andr=C3=A9 Lureau Message-Id: <20230705133139.54419-4-philmd@linaro.org> --- include/chardev/char-fe.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/chardev/char-fe.h b/include/chardev/char-fe.h index 8c420fa36e..0109602d63 100644 --- a/include/chardev/char-fe.h +++ b/include/chardev/char-fe.h @@ -175,6 +175,20 @@ void qemu_chr_fe_printf(CharBackend *be, const char *f= mt, ...) G_GNUC_PRINTF(2, 3); =20 =20 +/** + * FEWatchFunc: a #GSourceFunc called when any conditions requested by + * qemu_chr_fe_add_watch() is satisfied. + * @do_not_use: depending on the underlying chardev, a GIOChannel or a + * QIOChannel. DO NOT USE! + * @cond: bitwise combination of conditions watched and satisfied + * before calling this callback. + * @data: user data passed at creation to qemu_chr_fe_add_watch(). Can + * be NULL. + * + * Returns: G_SOURCE_REMOVE if the GSource should be removed from the + * main loop, or G_SOURCE_CONTINUE to leave the GSource in + * the main loop. + */ typedef gboolean (*FEWatchFunc)(void *do_not_use, GIOCondition condition, = void *data); =20 /** --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693487932; cv=none; d=zohomail.com; s=zohoarc; b=gFS3alL/nbFehQYlk3CH1knDgdhC9ymaLxidMOWELZsVK7K68f7JEZnmii1QR1No7Bpb6780BxtUrNYIJaSXwjNs7rs4Y5WBd+lJBVgmLrfIQZKqqzDxXL7FEwWALINYOeARx/6+nrhhYs/dfj/x/6Oz4T/5NumGJCyX6z4SXrE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693487932; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ltDvR2BAZ2X9usEMn+DOp5maTDaOUlNKujgVGnXvoz0=; b=V6RNNtBn/ft/9gy/+eiHfw7wmRIppZHXUZ5T852litgU69oM/Oc/tc5LjcFpnZwPrceZTXSFXPoSXWxGDd7TJ1lOfQGtUfKjx2318jE50lK2VzRAh9TxF9YlGsuFnY1vr/JPLpvYn71n9bRmTvcIRBMWbo8jwRqasIgRXs7Keag= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693487932395528.9886725405944; Thu, 31 Aug 2023 06:18:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbhKV-00071C-Lj; Thu, 31 Aug 2023 09:03:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbhG8-0003vb-2C for qemu-devel@nongnu.org; Thu, 31 Aug 2023 08:58:53 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbhG2-0005hn-Qf for qemu-devel@nongnu.org; Thu, 31 Aug 2023 08:58:50 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-40078c4855fso7030295e9.3 for ; Thu, 31 Aug 2023 05:58:46 -0700 (PDT) Received: from m1x-phil.lan ([176.187.199.245]) by smtp.gmail.com with ESMTPSA id z8-20020a05600c220800b003fe29dc0ff2sm1930778wml.21.2023.08.31.05.58.43 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 31 Aug 2023 05:58:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693486725; x=1694091525; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ltDvR2BAZ2X9usEMn+DOp5maTDaOUlNKujgVGnXvoz0=; b=RQWvn9mTH7BAPI1Z4djAcIBodSx0Bth8vAMbZI/6sVBPZ5U9CdNkWHKcImlsBO1zci v080mo36q2Yotz9lXXdR3ddHOlZQ74jLaPCul3VAGq2flLVkumw3Oi0IQBMxgB6inTSN AYmVf6E5nT/cMM0hRzOq8FzAZwKJc7TmAh3mquts90ZIKdOqPa/IT9lsJpiapoKmbR/p TaoqjZgf9xg7iLlo1g2Q0mg1avNIq9e2Tcry2qsZ60Q1Bgw5elHQcfPpWwM9EP5YLgPr 1X7rAOLfLH/GE1+IXSB+pq9M0QnHAqQK5Yj9dwbhl32JPNniEIeuHO8t5iQY9vyMtZTA AbYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693486725; x=1694091525; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ltDvR2BAZ2X9usEMn+DOp5maTDaOUlNKujgVGnXvoz0=; b=M12EuXhMjYvDb/jkjL9EtSkk1WMYIv6DbnkaIQSZqwMves26l36u67M34dr5aTq/Ya 7VadhJDLZzimlc7cuOU3hx11VXaCk0a4TkUTgMMkI7VL9kocTHeRdUh0BtzJImk+u6Th krKXqOLl7T1+6ZNfE3rL+jH22FkDsZ34DOdWPCmwsj2ZBxzxYois4gmHFPBLSCU1eJ40 fKpeBYz+1edI8/TDqQL6qyInmbqf+1TXbCrCZ4F2cUe6fHCFrGDksgVD/7OTwmZGSIjC 4JxrOhmb0Rim2vufikicKc/ItbvcH/oz/aENtjM+MYoZ1VyH0BH/M4REDBxnc/KWqeYm t1Qg== X-Gm-Message-State: AOJu0YwWaNFjgWJtTTP/o2JKUfikvzS486tYbqMCOzbMaCfLUTgd7igH fAcI+uyyIwtNXW+3BftBys7zIx+G5oUIGFDRg9Q= X-Google-Smtp-Source: AGHT+IEktC/XR1HDchvJ85U0x+gj0dvszfMCRszftWD97X6BEkX+Ym9N9rrEfHbWtF5SqNfZUVi6BQ== X-Received: by 2002:a7b:c3d2:0:b0:401:d947:c8a4 with SMTP id t18-20020a7bc3d2000000b00401d947c8a4mr3797191wmj.29.1693486724996; Thu, 31 Aug 2023 05:58:44 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , "Edgar E. Iglesias" , Alistair Francis , Peter Maydell , Paolo Bonzini , Joel Stanley , "Michael S. Tsirkin" , Laurent Vivier , Amit Shah , Gerd Hoffmann , "Dr. David Alan Gilbert" , Markus Armbruster , Jason Wang Subject: [PULL 20/41] hw/char: Have FEWatchFunc handlers return G_SOURCE_CONTINUE/REMOVE Date: Thu, 31 Aug 2023 14:56:22 +0200 Message-ID: <20230831125646.67855-21-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487933335100005 GLib recommend to use G_SOURCE_REMOVE / G_SOURCE_CONTINUE for GSourceFunc callbacks. Our FEWatchFunc is a GSourceFunc returning such value. Use such definitions which are "more memorable" [*]. [*] https://docs.gtk.org/glib/callback.SourceFunc.html#return-value Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Marc-Andr=C3=A9 Lureau Message-Id: <20230705133139.54419-5-philmd@linaro.org> --- hw/char/cadence_uart.c | 8 ++++---- hw/char/cmsdk-apb-uart.c | 6 +++--- hw/char/ibex_uart.c | 8 ++++---- hw/char/nrf51_uart.c | 4 ++-- hw/char/serial.c | 2 +- hw/char/virtio-console.c | 2 +- hw/usb/redirect.c | 2 +- monitor/monitor.c | 2 +- net/vhost-user.c | 2 +- 9 files changed, 18 insertions(+), 18 deletions(-) diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 807e398541..eff0304a18 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -307,11 +307,11 @@ static gboolean cadence_uart_xmit(void *do_not_use, G= IOCondition cond, /* instant drain the fifo when there's no back-end */ if (!qemu_chr_fe_backend_connected(&s->chr)) { s->tx_count =3D 0; - return FALSE; + return G_SOURCE_REMOVE; } =20 if (!s->tx_count) { - return FALSE; + return G_SOURCE_REMOVE; } =20 ret =3D qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count); @@ -326,12 +326,12 @@ static gboolean cadence_uart_xmit(void *do_not_use, G= IOCondition cond, cadence_uart_xmit, s); if (!r) { s->tx_count =3D 0; - return FALSE; + return G_SOURCE_REMOVE; } } =20 uart_update_status(s); - return FALSE; + return G_SOURCE_REMOVE; } =20 static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf, diff --git a/hw/char/cmsdk-apb-uart.c b/hw/char/cmsdk-apb-uart.c index f8dc89ee3d..d466cd93de 100644 --- a/hw/char/cmsdk-apb-uart.c +++ b/hw/char/cmsdk-apb-uart.c @@ -199,7 +199,7 @@ static gboolean uart_transmit(void *do_not_use, GIOCond= ition cond, void *opaque) s->watch_tag =3D 0; =20 if (!(s->ctrl & R_CTRL_TX_EN_MASK) || !(s->state & R_STATE_TXFULL_MASK= )) { - return FALSE; + return G_SOURCE_REMOVE; } =20 ret =3D qemu_chr_fe_write(&s->chr, &s->txbuf, 1); @@ -215,7 +215,7 @@ static gboolean uart_transmit(void *do_not_use, GIOCond= ition cond, void *opaque) } /* Transmit pending */ trace_cmsdk_apb_uart_tx_pending(); - return FALSE; + return G_SOURCE_REMOVE; } =20 buffer_drained: @@ -227,7 +227,7 @@ buffer_drained: s->intstatus |=3D R_INTSTATUS_TX_MASK; } cmsdk_apb_uart_update(s); - return FALSE; + return G_SOURCE_REMOVE; } =20 static void uart_cancel_transmit(CMSDKAPBUART *s) diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c index f70adb5308..51708c0836 100644 --- a/hw/char/ibex_uart.c +++ b/hw/char/ibex_uart.c @@ -147,7 +147,7 @@ static gboolean ibex_uart_xmit(void *do_not_use, GIOCon= dition cond, /* instant drain the fifo when there's no back-end */ if (!qemu_chr_fe_backend_connected(&s->chr)) { s->tx_level =3D 0; - return FALSE; + return G_SOURCE_REMOVE; } =20 if (!s->tx_level) { @@ -156,7 +156,7 @@ static gboolean ibex_uart_xmit(void *do_not_use, GIOCon= dition cond, s->uart_intr_state |=3D R_INTR_STATE_TX_EMPTY_MASK; s->uart_intr_state &=3D ~R_INTR_STATE_TX_WATERMARK_MASK; ibex_uart_update_irqs(s); - return FALSE; + return G_SOURCE_REMOVE; } =20 ret =3D qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_level); @@ -171,7 +171,7 @@ static gboolean ibex_uart_xmit(void *do_not_use, GIOCon= dition cond, ibex_uart_xmit, s); if (!r) { s->tx_level =3D 0; - return FALSE; + return G_SOURCE_REMOVE; } } =20 @@ -192,7 +192,7 @@ static gboolean ibex_uart_xmit(void *do_not_use, GIOCon= dition cond, } =20 ibex_uart_update_irqs(s); - return FALSE; + return G_SOURCE_REMOVE; } =20 static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf, diff --git a/hw/char/nrf51_uart.c b/hw/char/nrf51_uart.c index 3c6f982de9..dfe2276d71 100644 --- a/hw/char/nrf51_uart.c +++ b/hw/char/nrf51_uart.c @@ -93,13 +93,13 @@ static gboolean uart_transmit(void *do_not_use, GIOCond= ition cond, void *opaque) */ goto buffer_drained; } - return FALSE; + return G_SOURCE_REMOVE; } =20 buffer_drained: s->reg[R_UART_TXDRDY] =3D 1; s->pending_tx_byte =3D false; - return FALSE; + return G_SOURCE_REMOVE; } =20 static void uart_cancel_transmit(NRF51UARTState *s) diff --git a/hw/char/serial.c b/hw/char/serial.c index 270e1b1094..f3094f860f 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -226,7 +226,7 @@ static gboolean serial_watch_cb(void *do_not_use, GIOCo= ndition cond, SerialState *s =3D opaque; s->watch_tag =3D 0; serial_xmit(s); - return FALSE; + return G_SOURCE_REMOVE; } =20 static void serial_xmit(SerialState *s) diff --git a/hw/char/virtio-console.c b/hw/char/virtio-console.c index dd5a02e339..dbe0b28e60 100644 --- a/hw/char/virtio-console.c +++ b/hw/char/virtio-console.c @@ -45,7 +45,7 @@ static gboolean chr_write_unblocked(void *do_not_use, GIO= Condition cond, =20 vcon->watch =3D 0; virtio_serial_throttle_port(VIRTIO_SERIAL_PORT(vcon), false); - return FALSE; + return G_SOURCE_REMOVE; } =20 /* Callback function that's called when the guest sends us data */ diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c index 39fbaaab16..4bbf8afb33 100644 --- a/hw/usb/redirect.c +++ b/hw/usb/redirect.c @@ -278,7 +278,7 @@ static gboolean usbredir_write_unblocked(void *do_not_u= se, GIOCondition cond, dev->watch =3D 0; usbredirparser_do_write(dev->parser); =20 - return FALSE; + return G_SOURCE_REMOVE; } =20 static int usbredir_write(void *priv, uint8_t *data, int count) diff --git a/monitor/monitor.c b/monitor/monitor.c index dc352f9e9d..941f87815a 100644 --- a/monitor/monitor.c +++ b/monitor/monitor.c @@ -144,7 +144,7 @@ static gboolean monitor_unblocked(void *do_not_use, GIO= Condition cond, QEMU_LOCK_GUARD(&mon->mon_lock); mon->out_watch =3D 0; monitor_flush_locked(mon); - return FALSE; + return G_SOURCE_REMOVE; } =20 /* Caller must hold mon->mon_lock */ diff --git a/net/vhost-user.c b/net/vhost-user.c index 5993e4afca..12555518e8 100644 --- a/net/vhost-user.c +++ b/net/vhost-user.c @@ -239,7 +239,7 @@ static gboolean net_vhost_user_watch(void *do_not_use, = GIOCondition cond, =20 qemu_chr_fe_disconnect(&s->chr); =20 - return TRUE; + return G_SOURCE_CONTINUE; } =20 static void net_vhost_user_event(void *opaque, QEMUChrEvent event); --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693487438; cv=none; d=zohomail.com; s=zohoarc; b=Cy2BiyMvCZOzd+zshIf2J7YhWZ8tW2QuHWhyvOU7SMHbiVokIYHDJ99XzKTHYw1XpS0FwpvgM/cCN7cXRFTjfdLHhf6LRK3efW2072RYFCE4qbIpuoLiqzwn5ww4qc0Z0A+JG0RcnroRMtL/3eCZwl/V4nvsJBzNacjF/FFfqos= ARC-Message-Signature: i=1; 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Thu, 31 Aug 2023 05:58:52 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Peter Maydell , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini Subject: [PULL 21/41] hw/char/pl011: Restrict MemoryRegionOps implementation access sizes Date: Thu, 31 Aug 2023 14:56:23 +0200 Message-ID: <20230831125646.67855-22-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::734; envelope-from=philmd@linaro.org; helo=mail-qk1-x734.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487449117100001 The pl011_read() and pl011_write() handlers shift the offset argument by 2, so are implemented on a 32-bit boundary. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20230710175102.32429-2-philmd@linaro.org> --- hw/char/pl011.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 77bbc2a982..73f1a3aea2 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -358,6 +358,8 @@ static const MemoryRegionOps pl011_ops =3D { .read =3D pl011_read, .write =3D pl011_write, .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, }; =20 static bool pl011_clock_needed(void *opaque) --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693487620; cv=none; d=zohomail.com; s=zohoarc; b=A3dDh+KeCWDd6exXpY6zcF4bCOD/QTQE4RH0Suy1ui/7aoTAL6OZTRHbu+DYFwAJ2Bo7IISdb33RqJ87admF3o/1I/wJlYs46syZ/CEM+rXb5GNd/1Sb9LHiDXD95i6rITrwYLUSVSciaaq5umhk/UJcSxzmzWVO+HKaOYT6+QE= ARC-Message-Signature: i=1; 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Thu, 31 Aug 2023 05:59:00 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Peter Maydell , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini Subject: [PULL 22/41] hw/char/pl011: Display register name in trace events Date: Thu, 31 Aug 2023 14:56:24 +0200 Message-ID: <20230831125646.67855-23-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::b35; envelope-from=philmd@linaro.org; helo=mail-yb1-xb35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487636228100003 To avoid knowing the register addresses by heart, display their name along in the trace events. Since the MMIO region is 4K wide (0x1000 bytes), displaying the address with 3 digits is enough, so reduce the address format. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-Id: <20230522153144.30610-5-philmd@linaro.org> --- hw/char/pl011.c | 25 ++++++++++++++++++++++--- hw/char/trace-events | 4 ++-- 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 73f1a3aea2..c3203e5b41 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -51,6 +51,7 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Char= dev *chr) #define PL011_INT_TX 0x20 #define PL011_INT_RX 0x10 =20 +/* Flag Register, UARTFR */ #define PL011_FLAG_TXFE 0x80 #define PL011_FLAG_RXFF 0x40 #define PL011_FLAG_TXFF 0x20 @@ -76,6 +77,24 @@ static const unsigned char pl011_id_arm[8] =3D static const unsigned char pl011_id_luminary[8] =3D { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; =20 +static const char *pl011_regname(hwaddr offset) +{ + static const char *const rname[] =3D { + [0] =3D "DR", [1] =3D "RSR", [6] =3D "FR", [8] =3D "ILPR", [9] =3D= "IBRD", + [10] =3D "FBRD", [11] =3D "LCRH", [12] =3D "CR", [13] =3D "IFLS", = [14] =3D "IMSC", + [15] =3D "RIS", [16] =3D "MIS", [17] =3D "ICR", [18] =3D "DMACR", + }; + unsigned idx =3D offset >> 2; + + if (idx < ARRAY_SIZE(rname) && rname[idx]) { + return rname[idx]; + } + if (idx >=3D 0x3f8 && idx <=3D 0x400) { + return "ID"; + } + return "UNKN"; +} + /* Which bits in the interrupt status matter for each outbound IRQ line ? = */ static const uint32_t irqmask[] =3D { INT_E | INT_MS | INT_RT | INT_TX | INT_RX, /* combined IRQ */ @@ -191,7 +210,7 @@ static uint64_t pl011_read(void *opaque, hwaddr offset, break; } =20 - trace_pl011_read(offset, r); + trace_pl011_read(offset, r, pl011_regname(offset)); return r; } =20 @@ -234,7 +253,7 @@ static void pl011_write(void *opaque, hwaddr offset, PL011State *s =3D (PL011State *)opaque; unsigned char ch; =20 - trace_pl011_write(offset, value); + trace_pl011_write(offset, value, pl011_regname(offset)); =20 switch (offset >> 2) { case 0: /* UARTDR */ @@ -252,7 +271,7 @@ static void pl011_write(void *opaque, hwaddr offset, case 6: /* UARTFR */ /* Writes to Flag register are ignored. */ break; - case 8: /* UARTUARTILPR */ + case 8: /* UARTILPR */ s->ilpr =3D value; break; case 9: /* UARTIBRD */ diff --git a/hw/char/trace-events b/hw/char/trace-events index 2ecb36232e..babf4d35ea 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -54,9 +54,9 @@ escc_sunmouse_event(int dx, int dy, int buttons_state) "d= x=3D%d dy=3D%d buttons=3D0x%0 =20 # pl011.c pl011_irq_state(int level) "irq state %d" -pl011_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" +pl011_read(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03= x value 0x%08x reg %s" pl011_read_fifo(int read_count) "FIFO read, read_count now %d" -pl011_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" +pl011_write(uint32_t addr, uint32_t value, const char *regname) "addr 0x%0= 3x value 0x%08x reg %s" pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_co= unt %d returning %d" pl011_put_fifo(uint32_t c, int read_count) "new char 0x%x read_count now %= d" pl011_put_fifo_full(void) "FIFO now full, RXFF set" --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 31 Aug 2023 05:59:08 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Peter Maydell , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini Subject: [PULL 23/41] hw/char/pl011: Remove duplicated PL011_INT_[RT]X definitions Date: Thu, 31 Aug 2023 14:56:25 +0200 Message-ID: <20230831125646.67855-24-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1132; envelope-from=philmd@linaro.org; helo=mail-yw1-x1132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487895806100005 PL011_INT_TX duplicates INT_TX, and PL011_INT_RX INT_RX. Follow other register fields definitions from this file, keep the shorter form. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-Id: <20230522153144.30610-6-philmd@linaro.org> --- hw/char/pl011.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index c3203e5b41..96675f52cc 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -48,9 +48,6 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Char= dev *chr) return dev; } =20 -#define PL011_INT_TX 0x20 -#define PL011_INT_RX 0x10 - /* Flag Register, UARTFR */ #define PL011_FLAG_TXFE 0x80 #define PL011_FLAG_RXFF 0x40 @@ -157,7 +154,7 @@ static uint64_t pl011_read(void *opaque, hwaddr offset, s->flags |=3D PL011_FLAG_RXFE; } if (s->read_count =3D=3D s->read_trigger - 1) - s->int_level &=3D ~ PL011_INT_RX; + s->int_level &=3D ~ INT_RX; trace_pl011_read_fifo(s->read_count); s->rsr =3D c >> 8; pl011_update(s); @@ -262,7 +259,7 @@ static void pl011_write(void *opaque, hwaddr offset, /* XXX this blocks entire thread. Rewrite to use * qemu_chr_fe_write and background I/O callbacks */ qemu_chr_fe_write_all(&s->chr, &ch, 1); - s->int_level |=3D PL011_INT_TX; + s->int_level |=3D INT_TX; pl011_update(s); break; case 1: /* UARTRSR/UARTECR */ @@ -350,7 +347,7 @@ static void pl011_put_fifo(void *opaque, uint32_t value) s->flags |=3D PL011_FLAG_RXFF; } if (s->read_count =3D=3D s->read_trigger) { - s->int_level |=3D PL011_INT_RX; + s->int_level |=3D INT_RX; pl011_update(s); } } --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693487756; cv=none; d=zohomail.com; s=zohoarc; b=evQSalJNKiiZSvyM3St4U7pR14PLcsqv8EwYvX8al5fiEIWC5tQ+do0ktSC5aT01cqbKjYD+rVicV4wj82uZtgrrd7dY4v13BuQOgDo21Zubef5KpPCnUA4Ym5xC+YHRJX8xinpMFS3d2OhJQlszsK9j+rpDNunTF1AIFKYF36U= ARC-Message-Signature: i=1; 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Thu, 31 Aug 2023 05:59:16 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Peter Maydell , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini Subject: [PULL 24/41] hw/char/pl011: Replace magic values by register field definitions Date: Thu, 31 Aug 2023 14:56:26 +0200 Message-ID: <20230831125646.67855-25-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::731; envelope-from=philmd@linaro.org; helo=mail-qk1-x731.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487757495100003 0x400 is Data Register Break Error (DR_BE), 0x10 is Line Control Register Fifo Enabled (LCR_FEN) and 0x1 is Send Break (LCR_BRK). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-Id: <20230522153144.30610-7-philmd@linaro.org> --- hw/char/pl011.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 96675f52cc..58edeb9ddb 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -54,6 +54,9 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Char= dev *chr) #define PL011_FLAG_TXFF 0x20 #define PL011_FLAG_RXFE 0x10 =20 +/* Data Register, UARTDR */ +#define DR_BE (1 << 10) + /* Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC */ #define INT_OE (1 << 10) #define INT_BE (1 << 9) @@ -69,6 +72,10 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Cha= rdev *chr) #define INT_E (INT_OE | INT_BE | INT_PE | INT_FE) #define INT_MS (INT_RI | INT_DSR | INT_DCD | INT_CTS) =20 +/* Line Control Register, UARTLCR_H */ +#define LCR_FEN (1 << 4) +#define LCR_BRK (1 << 0) + static const unsigned char pl011_id_arm[8] =3D { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; static const unsigned char pl011_id_luminary[8] =3D @@ -116,7 +123,7 @@ static void pl011_update(PL011State *s) =20 static bool pl011_is_fifo_enabled(PL011State *s) { - return (s->lcr & 0x10) !=3D 0; + return (s->lcr & LCR_FEN) !=3D 0; } =20 static inline unsigned pl011_get_fifo_depth(PL011State *s) @@ -218,7 +225,7 @@ static void pl011_set_read_trigger(PL011State *s) the threshold. However linux only reads the FIFO in response to an interrupt. Triggering the interrupt when the FIFO is non-empty see= ms to make things work. */ - if (s->lcr & 0x10) + if (s->lcr & LCR_FEN) s->read_trigger =3D (s->ifl >> 1) & 0x1c; else #endif @@ -281,11 +288,11 @@ static void pl011_write(void *opaque, hwaddr offset, break; case 11: /* UARTLCR_H */ /* Reset the FIFO state on FIFO enable or disable */ - if ((s->lcr ^ value) & 0x10) { + if ((s->lcr ^ value) & LCR_FEN) { pl011_reset_fifo(s); } - if ((s->lcr ^ value) & 0x1) { - int break_enable =3D value & 0x1; + if ((s->lcr ^ value) & LCR_BRK) { + int break_enable =3D value & LCR_BRK; qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, &break_enable); } @@ -359,8 +366,9 @@ static void pl011_receive(void *opaque, const uint8_t *= buf, int size) =20 static void pl011_event(void *opaque, QEMUChrEvent event) { - if (event =3D=3D CHR_EVENT_BREAK) - pl011_put_fifo(opaque, 0x400); + if (event =3D=3D CHR_EVENT_BREAK) { + pl011_put_fifo(opaque, DR_BE); + } } =20 static void pl011_clock_update(void *opaque, ClockEvent event) --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 31 Aug 2023 05:59:22 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bernhard Beschow , Richard Henderson , Titus Rwantare Subject: [PULL 25/41] hw/i2c/pmbus_device: Fix modifying QOM class internals from instance Date: Thu, 31 Aug 2023 14:56:27 +0200 Message-ID: <20230831125646.67855-26-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=philmd@linaro.org; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487429317100001 QOM object instance should not modify its class state (because all other objects instanciated from this class get affected). Instead of modifying the PMBusDeviceClass 'device_num_pages' field the first time a instance is initialized (in pmbus_pages_alloc), introduce a new pmbus_pages_num() helper which returns the page number from the class without modifying the class state. The code logic become slighly simplified. Inspired-by: Bernhard Beschow Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20230523064408.57941-4-philmd@linaro.org> --- hw/i2c/pmbus_device.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c index 44fe4eddbb..8bc9d5108a 100644 --- a/hw/i2c/pmbus_device.c +++ b/hw/i2c/pmbus_device.c @@ -190,15 +190,18 @@ static void pmbus_quick_cmd(SMBusDevice *smd, uint8_t= read) } } =20 +static uint8_t pmbus_pages_num(PMBusDevice *pmdev) +{ + const PMBusDeviceClass *k =3D PMBUS_DEVICE_GET_CLASS(pmdev); + + /* some PMBus devices don't use the PAGE command, so they get 1 page */ + return k->device_num_pages ? : 1; +} + static void pmbus_pages_alloc(PMBusDevice *pmdev) { - /* some PMBus devices don't use the PAGE command, so they get 1 page */ - PMBusDeviceClass *k =3D PMBUS_DEVICE_GET_CLASS(pmdev); - if (k->device_num_pages =3D=3D 0) { - k->device_num_pages =3D 1; - } - pmdev->num_pages =3D k->device_num_pages; - pmdev->pages =3D g_new0(PMBusPage, k->device_num_pages); + pmdev->num_pages =3D pmbus_pages_num(pmdev); + pmdev->pages =3D g_new0(PMBusPage, pmdev->num_pages); } =20 void pmbus_check_limits(PMBusDevice *pmdev) --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693487371; cv=none; d=zohomail.com; s=zohoarc; b=QqxNLhdoaXpjXWwaPxNzNfYbIitjwz/2CbmVhK//TsblYVz5tFYvGXBmvChd0EePp4neqiOxZf/zMhxoa66UlwJUM4XN3Hb8mWiS22KC4kx9ahxdxg+2iBxW62cHSnngRxqUeiNKY2LZIZoXOTBB1o/LFGO+jm6xoX/ktU4jKkw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693487371; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Thu, 31 Aug 2023 05:59:27 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, Michael Tokarev , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Titus Rwantare , Corey Minyard , Tyrone Ting , Hao Wu Subject: [PULL 26/41] hw/i2c: spelling fixes Date: Thu, 31 Aug 2023 14:56:28 +0200 Message-ID: <20230831125646.67855-27-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487468134100001 From: Michael Tokarev Signed-off-by: Michael Tokarev Message-ID: <20230823065335.1919380-14-mjt@tls.msk.ru> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/i2c/npcm7xx_smbus.h | 2 +- include/hw/misc/auxbus.h | 2 +- hw/i2c/pm_smbus.c | 2 +- hw/i2c/pmbus_device.c | 2 +- hw/i2c/smbus_slave.c | 2 +- hw/sensor/isl_pmbus_vr.c | 2 +- hw/sensor/max34451.c | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/hw/i2c/npcm7xx_smbus.h b/include/hw/i2c/npcm7xx_smbus.h index 3555e6836f..dc45963c0e 100644 --- a/include/hw/i2c/npcm7xx_smbus.h +++ b/include/hw/i2c/npcm7xx_smbus.h @@ -58,7 +58,7 @@ typedef enum NPCM7xxSMBusStatus { * @sclht: The SCL high time register. * @fif_ctl: The FIFO control register. * @fif_cts: The FIFO control status register. - * @fair_per: The fair preriod register. + * @fair_per: The fair period register. * @txf_ctl: The transmit FIFO control register. * @t_out: The SMBus timeout register. * @txf_sts: The transmit FIFO status register. diff --git a/include/hw/misc/auxbus.h b/include/hw/misc/auxbus.h index b05799d2f7..03cacdee42 100644 --- a/include/hw/misc/auxbus.h +++ b/include/hw/misc/auxbus.h @@ -106,7 +106,7 @@ void aux_bus_realize(AUXBus *bus); * * Returns the reply of the request. * - * @bus Ths bus where the request happen. + * @bus The bus where the request happen. * @cmd The command requested. * @address The 20bits address of the slave. * @len The length of the read or write. diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c index d7eae548cb..9ad6a47739 100644 --- a/hw/i2c/pm_smbus.c +++ b/hw/i2c/pm_smbus.c @@ -1,6 +1,6 @@ /* * PC SMBus implementation - * splitted from acpi.c + * split from acpi.c * * Copyright (c) 2006 Fabrice Bellard * diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c index 8bc9d5108a..cef51663d0 100644 --- a/hw/i2c/pmbus_device.c +++ b/hw/i2c/pmbus_device.c @@ -1626,7 +1626,7 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t= *buf, uint8_t len) break; =20 passthrough: - /* Unimplimented registers get passed to the device */ + /* Unimplemented registers get passed to the device */ default: if (pmdc->write_data) { ret =3D pmdc->write_data(pmdev, buf, len); diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c index feb3ec6333..2ef2c7c5f6 100644 --- a/hw/i2c/smbus_slave.c +++ b/hw/i2c/smbus_slave.c @@ -2,7 +2,7 @@ * QEMU SMBus device emulation. * * This code is a helper for SMBus device emulation. It implements an - * I2C device inteface and runs the SMBus protocol from the device + * I2C device interface and runs the SMBus protocol from the device * point of view and maps those to simple calls to emulate. * * Copyright (c) 2007 CodeSourcery. diff --git a/hw/sensor/isl_pmbus_vr.c b/hw/sensor/isl_pmbus_vr.c index eb344dd5a9..e51269f6b8 100644 --- a/hw/sensor/isl_pmbus_vr.c +++ b/hw/sensor/isl_pmbus_vr.c @@ -101,7 +101,7 @@ static void isl_pmbus_vr_exit_reset(Object *obj) } } =20 -/* The raa228000 uses different direct mode coefficents from most isl devi= ces */ +/* The raa228000 uses different direct mode coefficients from most isl dev= ices */ static void raa228000_exit_reset(Object *obj) { PMBusDevice *pmdev =3D PMBUS_DEVICE(obj); diff --git a/hw/sensor/max34451.c b/hw/sensor/max34451.c index a91d8bd487..9db52ef677 100644 --- a/hw/sensor/max34451.c +++ b/hw/sensor/max34451.c @@ -734,7 +734,7 @@ static void max34451_init(Object *obj) =20 /* * get and set the temperature of the internal temperature sensor in - * centidegrees Celcius i.e.: 2500 -> 25.00 C, max is 327.67 C + * centidegrees Celsius i.e.: 2500 -> 25.00 C, max is 327.67 C */ for (int i =3D 0; i < MAX34451_NUM_TEMP_DEVICES; i++) { object_property_add(obj, "temperature[*]", "uint16", --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693487894; cv=none; d=zohomail.com; s=zohoarc; b=J7UYBPVLoLbc+8Klsr7jyOMyvpAoSfmBW331VDDQTnLJUBzeujAeiWXz6Ns/tYTLrwYzH+VhDAZ9HZPK/+yGY94XllvaCwbX1HjhWceNQRmc17Y0YAWuCSliGHW6WFEthAAQYdQA1zvfZ1v4E0fzB7yuxNVvuCA0QSvQwngDf3Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693487894; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sCCxv16p0EiY2aKlOpGL2Z1uWvBgdn7GkvBoQqZSuSQ=; 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Thu, 31 Aug 2023 05:59:33 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, Michael Tokarev , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , John Snow Subject: [PULL 27/41] hw/ide: spelling fixes Date: Thu, 31 Aug 2023 14:56:29 +0200 Message-ID: <20230831125646.67855-28-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487896225100007 From: Michael Tokarev Signed-off-by: Michael Tokarev Message-ID: <20230823065335.1919380-14-mjt@tls.msk.ru> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/ide/ahci_internal.h | 4 ++-- hw/ide/cmd646.c | 2 +- hw/ide/core.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/ide/ahci_internal.h b/hw/ide/ahci_internal.h index 2480455372..c244bbd8be 100644 --- a/hw/ide/ahci_internal.h +++ b/hw/ide/ahci_internal.h @@ -61,13 +61,13 @@ enum AHCIHostReg { AHCI_HOST_REG_CTL =3D 1, /* GHC: global host control */ AHCI_HOST_REG_IRQ_STAT =3D 2, /* IS: interrupt status */ AHCI_HOST_REG_PORTS_IMPL =3D 3, /* PI: bitmap of implemented ports */ - AHCI_HOST_REG_VERSION =3D 4, /* VS: AHCI spec. version compliancy = */ + AHCI_HOST_REG_VERSION =3D 4, /* VS: AHCI spec. version compliance = */ AHCI_HOST_REG_CCC_CTL =3D 5, /* CCC_CTL: CCC Control */ AHCI_HOST_REG_CCC_PORTS =3D 6, /* CCC_PORTS: CCC Ports */ AHCI_HOST_REG_EM_LOC =3D 7, /* EM_LOC: Enclosure Mgmt Location */ AHCI_HOST_REG_EM_CTL =3D 8, /* EM_CTL: Enclosure Mgmt Control */ AHCI_HOST_REG_CAP2 =3D 9, /* CAP2: host capabilities, extended = */ - AHCI_HOST_REG_BOHC =3D 10, /* BOHC: firmare/os handoff ctrl & st= atus */ + AHCI_HOST_REG_BOHC =3D 10, /* BOHC: firmware/os handoff ctrl & s= tatus */ AHCI_HOST_REG__COUNT =3D 11 }; =20 diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c index cabe9048b1..c0bcfa4414 100644 --- a/hw/ide/cmd646.c +++ b/hw/ide/cmd646.c @@ -257,7 +257,7 @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Erro= r **errp) =20 pci_conf[CNTRL] =3D CNTRL_EN_CH0; // enable IDE0 if (d->secondary) { - /* XXX: if not enabled, really disable the seconday IDE controller= */ + /* XXX: if not enabled, really disable the secondary IDE controlle= r */ pci_conf[CNTRL] |=3D CNTRL_EN_CH1; /* enable IDE1 */ } =20 diff --git a/hw/ide/core.c b/hw/ide/core.c index de48ff9f86..ee116891ed 100644 --- a/hw/ide/core.c +++ b/hw/ide/core.c @@ -1698,7 +1698,7 @@ static bool cmd_set_features(IDEState *s, uint8_t cmd) put_le16(identify_data + 63, 0x07); put_le16(identify_data + 88, 0x3f); break; - case 0x02: /* sigle word dma mode*/ + case 0x02: /* single word dma mode */ put_le16(identify_data + 62, 0x07 | (1 << (val + 8))); put_le16(identify_data + 63, 0x07); put_le16(identify_data + 88, 0x3f); --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 31 Aug 2023 05:59:38 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, Michael Tokarev , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Alistair Francis , "Edgar E. Iglesias" , Peter Maydell Subject: [PULL 28/41] hw/display: spelling fixes Date: Thu, 31 Aug 2023 14:56:30 +0200 Message-ID: <20230831125646.67855-29-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487615843100001 From: Michael Tokarev Signed-off-by: Michael Tokarev Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20230823065335.1919380-15-mjt@tls.msk.ru> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/display/bochs-display.c | 2 +- hw/display/qxl.c | 2 +- hw/display/ssd0303.c | 2 +- hw/display/ssd0323.c | 2 +- hw/display/xlnx_dp.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/display/bochs-display.c b/hw/display/bochs-display.c index e7ec268184..9138e98c3b 100644 --- a/hw/display/bochs-display.c +++ b/hw/display/bochs-display.c @@ -164,7 +164,7 @@ static int bochs_display_get_mode(BochsDisplayState *s, memset(mode, 0, sizeof(*mode)); switch (vbe[VBE_DISPI_INDEX_BPP]) { case 16: - /* best effort: support native endianess only */ + /* best effort: support native endianness only */ mode->format =3D PIXMAN_r5g6b5; mode->bytepp =3D 2; break; diff --git a/hw/display/qxl.c b/hw/display/qxl.c index f1c0eb7dfc..af941fb0c2 100644 --- a/hw/display/qxl.c +++ b/hw/display/qxl.c @@ -1544,7 +1544,7 @@ static void qxl_create_guest_primary(PCIQXLDevice *qx= l, int loadvm, } } =20 -/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or +/* return 1 if surface destroy was initiated (in QXL_ASYNC case) or * done (in QXL_SYNC case), 0 otherwise. */ static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async) { diff --git a/hw/display/ssd0303.c b/hw/display/ssd0303.c index d67b0ad7b5..32b32a3044 100644 --- a/hw/display/ssd0303.c +++ b/hw/display/ssd0303.c @@ -8,7 +8,7 @@ */ =20 /* The controller can support a variety of different displays, but we only - implement one. Most of the commends relating to brightness and geometry + implement one. Most of the commands relating to brightness and geometry setup are ignored. */ =20 #include "qemu/osdep.h" diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c index ab229d32b7..09b1bbed0a 100644 --- a/hw/display/ssd0323.c +++ b/hw/display/ssd0323.c @@ -8,7 +8,7 @@ */ =20 /* The controller can support a variety of different displays, but we only - implement one. Most of the commends relating to brightness and geometry + implement one. Most of the commands relating to brightness and geometry setup are ignored. */ =20 #include "qemu/osdep.h" diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c index b0828d65aa..822355ecc6 100644 --- a/hw/display/xlnx_dp.c +++ b/hw/display/xlnx_dp.c @@ -380,7 +380,7 @@ static inline void xlnx_dp_audio_mix_buffer(XlnxDPState= *s) static void xlnx_dp_audio_callback(void *opaque, int avail) { /* - * Get some data from the DPDMA and compute these datas. + * Get some data from the DPDMA and compute these data. * Then wait for QEMU's audio subsystem to call this callback. */ XlnxDPState *s =3D XLNX_DP(opaque); --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693487404; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487494514100001 From: Michael Tokarev Signed-off-by: Michael Tokarev Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20230823065335.1919380-7-mjt@tls.msk.ru> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/mips/malta.c | 2 +- target/mips/tcg/msa_helper.c | 12 ++++++------ target/mips/tcg/mxu_translate.c | 6 +++--- target/mips/cpu-defs.c.inc | 2 +- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index f9618fa5f5..16e9c4773f 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -627,7 +627,7 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint= 64_t run_addr, 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ }; =20 - /* Bus endianess is always reversed */ + /* Bus endianness is always reversed */ #if TARGET_BIG_ENDIAN #define cpu_to_gt32(x) (x) #else diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index c8597b9e30..c314a74397 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -803,9 +803,9 @@ void helper_msa_bset_d(CPUMIPSState *env, uint32_t wd, = uint32_t ws, uint32_t wt) * | HADD_S.H | Vector Signed Horizontal Add (halfword) = | * | HADD_S.W | Vector Signed Horizontal Add (word) = | * | HADD_S.D | Vector Signed Horizontal Add (doubleword) = | - * | HADD_U.H | Vector Unigned Horizontal Add (halfword) = | - * | HADD_U.W | Vector Unigned Horizontal Add (word) = | - * | HADD_U.D | Vector Unigned Horizontal Add (doubleword) = | + * | HADD_U.H | Vector Unsigned Horizontal Add (halfword) = | + * | HADD_U.W | Vector Unsigned Horizontal Add (word) = | + * | HADD_U.D | Vector Unsigned Horizontal Add (doubleword) = | * +---------------+------------------------------------------------------= ----+ */ =20 @@ -3452,9 +3452,9 @@ void helper_msa_mulv_d(CPUMIPSState *env, * | HSUB_S.H | Vector Signed Horizontal Subtract (halfword) = | * | HSUB_S.W | Vector Signed Horizontal Subtract (word) = | * | HSUB_S.D | Vector Signed Horizontal Subtract (doubleword) = | - * | HSUB_U.H | Vector Unigned Horizontal Subtract (halfword) = | - * | HSUB_U.W | Vector Unigned Horizontal Subtract (word) = | - * | HSUB_U.D | Vector Unigned Horizontal Subtract (doubleword) = | + * | HSUB_U.H | Vector Unsigned Horizontal Subtract (halfword) = | + * | HSUB_U.W | Vector Unsigned Horizontal Subtract (word) = | + * | HSUB_U.D | Vector Unsigned Horizontal Subtract (doubleword) = | * | SUBS_S.B | Vector Signed Saturated Subtract (of Signed) (byte) = | * | SUBS_S.H | Vector Signed Saturated Subtract (of Signed) (halfwor= d) | * | SUBS_S.W | Vector Signed Saturated Subtract (of Signed) (word) = | diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translat= e.c index e662acd5df..cfcd8ac9bc 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -2977,14 +2977,14 @@ static void gen_mxu_Q8ADD(DisasContext *ctx) * to another one in XRc, with zero extending * to 16-bit and put results as packed 16-bit data * into XRa and XRd. - * aptn2 manages action add or subract of pairs of data. + * aptn2 manages action add or subtract of pairs of data. * * Q8ACCE XRa, XRb, XRc, XRd, aptn2 * Add/subtract quadruple of 8-bit packed in XRb * to another one in XRc, with zero extending * to 16-bit and accumulate results as packed 16-bit data * into XRa and XRd. - * aptn2 manages action add or subract of pairs of data. + * aptn2 manages action add or subtract of pairs of data. */ static void gen_mxu_q8adde(DisasContext *ctx, bool accumulate) { @@ -4056,7 +4056,7 @@ static void gen_mxu_s32sfl(DisasContext *ctx) =20 /* * Q8SAD XRa, XRd, XRb, XRc - * Typical SAD opration for motion estimation. + * Typical SAD operation for motion estimation. */ static void gen_mxu_q8sad(DisasContext *ctx) { diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 03185d9aa0..c0c389c59a 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -1045,7 +1045,7 @@ static void mvp_init(CPUMIPSState *env) return; } =20 - /* MVPConf1 implemented, TLB sharable, no gating storage support, + /* MVPConf1 implemented, TLB shareable, no gating storage support, programmable cache partitioning implemented, number of allocatable and shareable TLB entries, MVP has allocatable TCs, 2 VPEs implemented, 5 TCs implemented. */ --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693487642; cv=none; d=zohomail.com; s=zohoarc; b=ZvjCKkxYQGioc2VW1dkBfUqRaCJCwvPXXcXvH9iXVzQmkugaPw/zgZdvAhN0hizRCUysM899DRwei9pw+nJhebQqKL1V0xfQqvlWUZ8sMDK2VEA/KHIGNvKK+kMc5WRcIYN4zYyNm330M/IaWVisCiGpeo1QRkBpqcbygI4Lnvk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693487642; 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Thu, 31 Aug 2023 05:59:49 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, Michael Tokarev , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PULL 30/41] hw/sd: spelling fixes Date: Thu, 31 Aug 2023 14:56:32 +0200 Message-ID: <20230831125646.67855-31-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487644595100005 From: Michael Tokarev Signed-off-by: Michael Tokarev Message-ID: <20230823065335.1919380-18-mjt@tls.msk.ru> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/sd/sd.c | 2 +- hw/sd/sdhci.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 77a717d355..43c374e829 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -1224,7 +1224,7 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, S= DRequest req) } break; =20 - /* Block read commands (Classs 2) */ + /* Block read commands (Class 2) */ case 16: /* CMD16: SET_BLOCKLEN */ switch (sd->state) { case sd_transfer_state: diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 362c2c86aa..5564765a9b 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1811,7 +1811,7 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val= , unsigned size) * on i.MX, but since it is not used by QEMU we do not care. * * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...) - * here becuase it will result in a call to + * here because it will result in a call to * sdhci_send_command(s) which we don't want. * */ --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Thu, 31 Aug 2023 05:59:55 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, Michael Tokarev , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Stefano Stabellini , Anthony Perard , Paul Durrant , xen-devel@lists.xenproject.org Subject: [PULL 31/41] hw/usb: spelling fixes Date: Thu, 31 Aug 2023 14:56:33 +0200 Message-ID: <20230831125646.67855-32-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693486844055100001 From: Michael Tokarev Signed-off-by: Michael Tokarev Message-ID: <20230823065335.1919380-14-mjt@tls.msk.ru> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/usb/quirks.h | 2 +- hw/usb/ccid-card-emulated.c | 2 +- hw/usb/hcd-ehci.c | 6 +++--- hw/usb/hcd-ohci.c | 2 +- hw/usb/redirect.c | 2 +- hw/usb/xen-usb.c | 2 +- hw/usb/trace-events | 2 +- 7 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/usb/quirks.h b/hw/usb/quirks.h index c3e595f40b..94b2c95341 100644 --- a/hw/usb/quirks.h +++ b/hw/usb/quirks.h @@ -67,7 +67,7 @@ static const struct usb_device_id usbredir_raw_serial_ids= [] =3D { { USB_DEVICE(0x10C4, 0x800A) }, /* SPORTident BSM7-D-USB main station = */ { USB_DEVICE(0x10C4, 0x803B) }, /* Pololu USB-serial converter */ { USB_DEVICE(0x10C4, 0x8044) }, /* Cygnal Debug Adapter */ - { USB_DEVICE(0x10C4, 0x804E) }, /* Software Bisque Paramount ME build-= in converter */ + { USB_DEVICE(0x10C4, 0x804E) }, /* Software Bisque Paramount ME built-= in converter */ { USB_DEVICE(0x10C4, 0x8053) }, /* Enfora EDG1228 */ { USB_DEVICE(0x10C4, 0x8054) }, /* Enfora GSM2228 */ { USB_DEVICE(0x10C4, 0x8066) }, /* Argussoft In-System Programmer */ diff --git a/hw/usb/ccid-card-emulated.c b/hw/usb/ccid-card-emulated.c index c328660075..3ee9c73b87 100644 --- a/hw/usb/ccid-card-emulated.c +++ b/hw/usb/ccid-card-emulated.c @@ -518,7 +518,7 @@ static void emulated_realize(CCIDCardState *base, Error= **errp) goto out2; } =20 - /* TODO: a passthru backened that works on local machine. third card t= ype?*/ + /* TODO: a passthru backend that works on local machine. third card ty= pe?*/ if (card->backend =3D=3D BACKEND_CERTIFICATES) { if (card->cert1 !=3D NULL && card->cert2 !=3D NULL && card->cert3 = !=3D NULL) { ret =3D emulated_initialize_vcard_from_certificates(card); diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c index c930c60921..19b4534c20 100644 --- a/hw/usb/hcd-ehci.c +++ b/hw/usb/hcd-ehci.c @@ -1464,7 +1464,7 @@ static int ehci_process_itd(EHCIState *ehci, usb_handle_packet(dev, &ehci->ipacket); usb_packet_unmap(&ehci->ipacket, &ehci->isgl); } else { - DPRINTF("ISOCH: attempt to addess non-iso endpoint\n"); + DPRINTF("ISOCH: attempt to address non-iso endpoint\n"= ); ehci->ipacket.status =3D USB_RET_NAK; ehci->ipacket.actual_length =3D 0; } @@ -1513,7 +1513,7 @@ static int ehci_process_itd(EHCIState *ehci, =20 =20 /* This state is the entry point for asynchronous schedule - * processing. Entry here consitutes a EHCI start event state (4.8.5) + * processing. Entry here constitutes a EHCI start event state (4.8.5) */ static int ehci_state_waitlisthead(EHCIState *ehci, int async) { @@ -2458,7 +2458,7 @@ static void usb_ehci_vm_state_change(void *opaque, bo= ol running, RunState state) /* * The schedule rebuilt from guest memory could cause the migration de= st * to miss a QH unlink, and fail to cancel packets, since the unlinked= QH - * will never have existed on the destination. Therefor we must flush = the + * will never have existed on the destination. Therefore we must flush= the * async schedule on savevm to catch any not yet noticed unlinks. */ if (state =3D=3D RUN_STATE_SAVE_VM) { diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c index cc5cde6983..7ff1b65ced 100644 --- a/hw/usb/hcd-ohci.c +++ b/hw/usb/hcd-ohci.c @@ -1355,7 +1355,7 @@ static uint32_t ohci_get_frame_remaining(OHCIState *o= hci) if ((ohci->ctl & OHCI_CTL_HCFS) !=3D OHCI_USB_OPERATIONAL) { return ohci->frt << 31; } - /* Being in USB operational state guarnatees sof_time was set already.= */ + /* Being in USB operational state guarantees sof_time was set already.= */ tks =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ohci->sof_time; if (tks < 0) { tks =3D 0; diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c index 4bbf8afb33..c9893df867 100644 --- a/hw/usb/redirect.c +++ b/hw/usb/redirect.c @@ -471,7 +471,7 @@ static int bufp_alloc(USBRedirDevice *dev, uint8_t *dat= a, uint16_t len, DPRINTF("bufpq overflow, dropping packets ep %02X\n", ep); dev->endpoint[EP2I(ep)].bufpq_dropping_packets =3D 1; } - /* Since we're interupting the stream anyways, drop enough packets to = get + /* Since we're interrupting the stream anyways, drop enough packets to= get back to our target buffer size */ if (dev->endpoint[EP2I(ep)].bufpq_dropping_packets) { if (dev->endpoint[EP2I(ep)].bufpq_size > diff --git a/hw/usb/xen-usb.c b/hw/usb/xen-usb.c index 38ee660a30..09ec326aea 100644 --- a/hw/usb/xen-usb.c +++ b/hw/usb/xen-usb.c @@ -451,7 +451,7 @@ static int usbback_check_and_submit(struct usbback_req = *usbback_req) wValue =3D le16_to_cpu(ctrl->wValue); =20 /* - * When the device is first connected or resetted, USB device has no + * When the device is first connected or reset, USB device has no * address. In this initial state, following requests are sent to devi= ce * address (#0), * diff --git a/hw/usb/trace-events b/hw/usb/trace-events index 6bb9655c8d..ed7dc210d3 100644 --- a/hw/usb/trace-events +++ b/hw/usb/trace-events @@ -248,7 +248,7 @@ usb_set_device_feature(int addr, int feature, int ret) = "dev %d, feature %d, ret =20 # dev-hub.c usb_hub_reset(int addr) "dev %d" -usb_hub_control(int addr, int request, int value, int index, int length) "= dev %d, req 0x%x, value %d, index %d, langth %d" +usb_hub_control(int addr, int request, int value, int index, int length) "= dev %d, req 0x%x, value %d, index %d, length %d" usb_hub_get_port_status(int addr, int nr, int status, int changed) "dev %d= , port %d, status 0x%x, changed 0x%x" usb_hub_set_port_feature(int addr, int nr, const char *f) "dev %d, port %d= , feature %s" usb_hub_clear_port_feature(int addr, int nr, const char *f) "dev %d, port = %d, feature %s" --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 31 Aug 2023 06:00:01 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Gerd Hoffmann Subject: [PULL 32/41] hw/usb/hcd-xhci: Avoid variable-length array in xhci_get_port_bandwidth() Date: Thu, 31 Aug 2023 14:56:34 +0200 Message-ID: <20230831125646.67855-33-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487762944100001 From: Peter Maydell In xhci_get_port_bandwidth(), we use a variable-length array to construct the buffer to send back to the guest. Avoid the VLA by using dma_memory_set() to directly request the memory system to fill the guest memory with a string of '80's. The codebase has very few VLAs, and if we can get rid of them all we can make the compiler error on new additions. This is a defensive measure against security bugs where an on-stack dynamic allocation isn't correctly size-checked (e.g. CVE-2021-3527). Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20230824164818.2652452-1-peter.maydell@linaro.org> --- hw/usb/hcd-xhci.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index b89b618ec2..324177ad5d 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -2434,7 +2434,6 @@ static void xhci_detach_slot(XHCIState *xhci, USBPort= *uport) static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) { dma_addr_t ctx; - uint8_t bw_ctx[xhci->numports+1]; =20 DPRINTF("xhci_get_port_bandwidth()\n"); =20 @@ -2442,11 +2441,10 @@ static TRBCCode xhci_get_port_bandwidth(XHCIState *= xhci, uint64_t pctx) =20 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); =20 - /* TODO: actually implement real values here */ - bw_ctx[0] =3D 0; - memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ - if (dma_memory_write(xhci->as, ctx, bw_ctx, sizeof(bw_ctx), - MEMTXATTRS_UNSPECIFIED) !=3D MEMTX_OK) { + /* TODO: actually implement real values here. This is 80% for all port= s. */ + if (stb_dma(xhci->as, ctx, 0, MEMTXATTRS_UNSPECIFIED) !=3D MEMTX_OK || + dma_memory_set(xhci->as, ctx + 1, 80, xhci->numports, + MEMTXATTRS_UNSPECIFIED) !=3D MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory write failed!\n", __func__); return CC_TRB_ERROR; --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693487473; cv=none; d=zohomail.com; s=zohoarc; b=T1UNiapMz+jrd69t1oZjwGIPg5nk6Mb/7T2xGp4T9B7B8+UDOsRnk2HmyU3xndaJ3mF1DwLqDjob62AlyD52Z+S4+sQwm+A3YqanOsGIcyfSNGUxE0PiFGifOKPAP5tJrrZkkAMHVQYVuUQz3n/aKiZeX4logScvpG7RwpE+woA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693487473; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RBqrh3+OwbRO0FKJwz0pOQZiq7Hglu3XVSiWyrHauk4=; b=JDRfpRj7i3UvhThILNGw9bUxw1Ff5bg8HLo/MV65U5bmKwRKNL/E7RKHtMt1UzqMEKG+ta5VApd48yzjJB6IllYZGzozZlJfl6FL18f/VlNmcBOUJs4YiXP9ObnuWIYytvM1Zn8/DNsEpGsfU4IC6Hnj/vmnkLzinXxmXXpYztg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693487473613459.5052739518678; Thu, 31 Aug 2023 06:11:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbhLT-0008BH-0T; Thu, 31 Aug 2023 09:04:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbhHU-0005kf-7b for qemu-devel@nongnu.org; Thu, 31 Aug 2023 09:00:22 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbhHN-0006Uw-AD for qemu-devel@nongnu.org; Thu, 31 Aug 2023 09:00:15 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-3fee5ddc23eso7129215e9.1 for ; Thu, 31 Aug 2023 06:00:08 -0700 (PDT) Received: from m1x-phil.lan ([176.187.199.245]) by smtp.gmail.com with ESMTPSA id i16-20020adffc10000000b0031c5ee51638sm2147619wrr.109.2023.08.31.06.00.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 31 Aug 2023 06:00:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693486807; x=1694091607; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RBqrh3+OwbRO0FKJwz0pOQZiq7Hglu3XVSiWyrHauk4=; b=jwS/5IOwS7px3CF7UdLJXiNGi0KzHBTBrNC3LNr1yrKDqhQx7fm3CUw4PBMeKW4J1H jc1OBsWy4pZKscTGUgc96/BfumC5sIiVKA5KpA7agOKtnX9Z3GCBWmbbX9DJi7nSswyr g5CQzniYwRsFnM7KXcYMLDaRq5++/3A8p7tqiEvw5FwqAe+ovuwV5WXBc3YWm5UwObqD Q6lYKRb6zjlV4HIDhZQCPc5DQErAWV4vfZ390BvPC9USoGs5L6m+FabLrs7g2XZPw0j3 awlETQmsyds6nj0Wh7DUw3/KJS5ok5b9lhC14HhenTs48OV7AHP+Tky/SfWMHoA3+wf8 paMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693486807; x=1694091607; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RBqrh3+OwbRO0FKJwz0pOQZiq7Hglu3XVSiWyrHauk4=; b=aD7Q/MAljKoXAcY4gBEtPtdXCJV3P5Ce+Zc9kojKQ6AllmTK1XweoSIrYRkJ7NDSBl OUlzXf5AVgxTbU7csxyUmsYEzA1RY5YIIHlylhv/TZfkn/lm/y7ek5NXv8C6lXmyt8do CH3tjCZ2BM6Xr+y8htAbFg1TOrPoS1NUL7L/M/NJWZUc5x4GbkBeSIUuOiOztBvLG2Ok sHqSQDIJHb7El/CcmM3dOTKK9ri4aY8TYdakcr8d0GdW8UDJKRtZP6zpRug0Ez2XulGq SlE+LAcxZWJHzQzZk26jU7gXzw5+gSiVfgwmPHZEjFgH1DcFGPCoXIGoqQhUoeyS6SC+ R05w== X-Gm-Message-State: AOJu0Yxo3lJ2TZ3w6xj6mz7/7Y++ktJKCxpkjk3O4Fr8FBLGknfMRUx4 RPvUaEytjQmp4/it9L9rkGGxWRUvma903D57ilE= X-Google-Smtp-Source: AGHT+IHFtn1g4oVr4OxUDyOHvfLkdRRms95A80KEEeJytluOw9x87dJtzVPYJS4DW6y4OFRSEbfikw== X-Received: by 2002:adf:e5cf:0:b0:317:e542:80a8 with SMTP id a15-20020adfe5cf000000b00317e54280a8mr3780210wrn.15.1693486807461; Thu, 31 Aug 2023 06:00:07 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Alex=20Benn=C3=A9e?= , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Sergio Lopez , kvm@vger.kernel.org Subject: [PULL 33/41] hw/i386: Remove unuseful kvmclock_create() stub Date: Thu, 31 Aug 2023 14:56:35 +0200 Message-ID: <20230831125646.67855-34-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487529787100001 We shouldn't call kvmclock_create() when KVM is not available or disabled: - check for kvm_enabled() before calling it - assert KVM is enabled once called Since the call is elided when KVM is not available, we can remove the stub (it is never compiled). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Message-Id: <20230620083228.88796-2-philmd@linaro.org> --- include/hw/kvm/clock.h | 10 ---------- hw/i386/kvm/clock.c | 4 +++- hw/i386/microvm.c | 4 +++- hw/i386/pc_piix.c | 2 +- hw/i386/pc_q35.c | 4 +++- 5 files changed, 10 insertions(+), 14 deletions(-) diff --git a/include/hw/kvm/clock.h b/include/hw/kvm/clock.h index 7994071c4f..3efe0a871c 100644 --- a/include/hw/kvm/clock.h +++ b/include/hw/kvm/clock.h @@ -13,16 +13,6 @@ #ifndef HW_KVM_CLOCK_H #define HW_KVM_CLOCK_H =20 -#ifdef CONFIG_KVM - void kvmclock_create(bool create_always); =20 -#else /* CONFIG_KVM */ - -static inline void kvmclock_create(bool create_always) -{ -} - -#endif /* !CONFIG_KVM */ - #endif diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c index df70b4a033..0824c6d313 100644 --- a/hw/i386/kvm/clock.c +++ b/hw/i386/kvm/clock.c @@ -332,8 +332,10 @@ void kvmclock_create(bool create_always) { X86CPU *cpu =3D X86_CPU(first_cpu); =20 - if (!kvm_enabled() || !kvm_has_adjust_clock()) + assert(kvm_enabled()); + if (!kvm_has_adjust_clock()) { return; + } =20 if (create_always || cpu->env.features[FEAT_KVM] & ((1ULL << KVM_FEATURE_CLOCKSOURCE) | diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index 7227a2156c..6b762bc18e 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -180,7 +180,9 @@ static void microvm_devices_init(MicrovmMachineState *m= ms) x86ms->ioapic2 =3D ioapic_init_secondary(gsi_state); } =20 - kvmclock_create(true); + if (kvm_enabled()) { + kvmclock_create(true); + } =20 mms->virtio_irq_base =3D 5; mms->virtio_num_transports =3D 8; diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index ce1ac95274..3de8e0d741 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -192,7 +192,7 @@ static void pc_init1(MachineState *machine, pc_machine_init_sgx_epc(pcms); x86_cpus_init(x86ms, pcmc->default_cpu_version); =20 - if (pcmc->kvmclock_enabled) { + if (kvm_enabled() && pcmc->kvmclock_enabled) { kvmclock_create(pcmc->kvmclock_create_always); } =20 diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 37c4814bed..a95c5d046e 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -183,7 +183,9 @@ static void pc_q35_init(MachineState *machine) pc_machine_init_sgx_epc(pcms); x86_cpus_init(x86ms, pcmc->default_cpu_version); =20 - kvmclock_create(pcmc->kvmclock_create_always); + if (kvm_enabled()) { + kvmclock_create(pcmc->kvmclock_create_always); + } =20 /* pci enabled */ if (pcmc->pci_enabled) { --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693487871; cv=none; d=zohomail.com; s=zohoarc; b=MxibDfOyYXqG357QQLcQaf0Y1V5+d1E912gAtCdtNCeeMUm8aJ455INVtcVXnxNuEdzsK8D4ByYeJfLmEBhJhtXorMiXYvYTrG8Ak/9Fb6y289juHLZWdgC9vMuq1/fwwb8cWXnwyhzC99xrx1izBLL2htAKRDFmWt7DIFRF+c4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693487871; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Thu, 31 Aug 2023 06:00:13 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Alex=20Benn=C3=A9e?= , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Sergio Lopez Subject: [PULL 34/41] hw/i386: Rename 'hw/kvm/clock.h' -> 'hw/i386/kvm/clock.h' Date: Thu, 31 Aug 2023 14:56:36 +0200 Message-ID: <20230831125646.67855-35-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487871919100003 kvmclock_create() is only implemented in hw/i386/kvm/clock.h. Restrict the "hw/kvm/clock.h" header to i386 by moving it to hw/i386/. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Message-Id: <20230620083228.88796-3-philmd@linaro.org> --- {include/hw =3D> hw/i386}/kvm/clock.h | 4 ++-- hw/i386/kvm/clock.c | 2 +- hw/i386/microvm.c | 2 +- hw/i386/pc_piix.c | 2 +- hw/i386/pc_q35.c | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) rename {include/hw =3D> hw/i386}/kvm/clock.h (85%) diff --git a/include/hw/kvm/clock.h b/hw/i386/kvm/clock.h similarity index 85% rename from include/hw/kvm/clock.h rename to hw/i386/kvm/clock.h index 3efe0a871c..401c7e445b 100644 --- a/include/hw/kvm/clock.h +++ b/hw/i386/kvm/clock.h @@ -10,8 +10,8 @@ * See the COPYING file in the top-level directory. */ =20 -#ifndef HW_KVM_CLOCK_H -#define HW_KVM_CLOCK_H +#ifndef HW_I386_KVM_CLOCK_H +#define HW_I386_KVM_CLOCK_H =20 void kvmclock_create(bool create_always); =20 diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c index 0824c6d313..34348a3324 100644 --- a/hw/i386/kvm/clock.c +++ b/hw/i386/kvm/clock.c @@ -22,7 +22,7 @@ #include "kvm/kvm_i386.h" #include "migration/vmstate.h" #include "hw/sysbus.h" -#include "hw/kvm/clock.h" +#include "hw/i386/kvm/clock.h" #include "hw/qdev-properties.h" #include "qapi/error.h" =20 diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index 6b762bc18e..8deeb62774 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -32,7 +32,7 @@ =20 #include "hw/loader.h" #include "hw/irq.h" -#include "hw/kvm/clock.h" +#include "hw/i386/kvm/clock.h" #include "hw/i386/microvm.h" #include "hw/i386/x86.h" #include "target/i386/cpu.h" diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 3de8e0d741..5cbad6ad84 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -46,7 +46,7 @@ #include "hw/ide/piix.h" #include "hw/irq.h" #include "sysemu/kvm.h" -#include "hw/kvm/clock.h" +#include "hw/i386/kvm/clock.h" #include "hw/sysbus.h" #include "hw/i2c/smbus_eeprom.h" #include "exec/memory.h" diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index a95c5d046e..0bd68690f5 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -35,7 +35,7 @@ #include "hw/i2c/smbus_eeprom.h" #include "hw/rtc/mc146818rtc.h" #include "sysemu/kvm.h" -#include "hw/kvm/clock.h" +#include "hw/i386/kvm/clock.h" #include "hw/pci-host/q35.h" #include "hw/pci/pcie_port.h" #include "hw/qdev-properties.h" --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 31 Aug 2023 06:00:18 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Francisco Iglesias , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 35/41] util/fifo8: Fix typo in fifo8_push_all() description Date: Thu, 31 Aug 2023 14:56:37 +0200 Message-ID: <20230831125646.67855-36-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487585806100001 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Francisco Iglesias Reviewed-by: Alex Benn=C3=A9e Message-Id: <20230522153144.30610-2-philmd@linaro.org> --- include/qemu/fifo8.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/qemu/fifo8.h b/include/qemu/fifo8.h index 28bf2cee57..16be02f361 100644 --- a/include/qemu/fifo8.h +++ b/include/qemu/fifo8.h @@ -46,7 +46,7 @@ void fifo8_push(Fifo8 *fifo, uint8_t data); * fifo8_push_all: * @fifo: FIFO to push to * @data: data to push - * @size: number of bytes to push + * @num: number of bytes to push * * Push a byte array to the FIFO. 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Thu, 31 Aug 2023 06:00:24 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, Michael Tokarev , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Peter Xu , Lukas Straub , Richard Henderson , Paolo Bonzini Subject: [PULL 36/41] util: spelling fixes Date: Thu, 31 Aug 2023 14:56:38 +0200 Message-ID: <20230831125646.67855-37-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487938725100003 From: Michael Tokarev Signed-off-by: Michael Tokarev Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20230823065335.1919380-3-mjt@tls.msk.ru> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/elf.h | 4 ++-- include/io/channel-socket.h | 4 ++-- include/io/task.h | 2 +- include/qemu/iova-tree.h | 4 ++-- include/qemu/yank.h | 2 +- util/cpuinfo-aarch64.c | 4 ++-- util/cpuinfo-i386.c | 4 ++-- util/cpuinfo-ppc.c | 2 +- util/main-loop.c | 2 +- util/oslib-posix.c | 2 +- util/qdist.c | 2 +- util/qemu-sockets.c | 2 +- util/rcu.c | 2 +- 13 files changed, 18 insertions(+), 18 deletions(-) diff --git a/include/elf.h b/include/elf.h index ec9755e73b..e7259ec366 100644 --- a/include/elf.h +++ b/include/elf.h @@ -1125,9 +1125,9 @@ typedef struct { #define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ #define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ =20 -/* Additional section indeces. */ +/* Additional section indices. */ =20 -#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared +#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tentatively declar= ed symbols in ANSI C. */ #define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. = */ =20 diff --git a/include/io/channel-socket.h b/include/io/channel-socket.h index 513c428fe4..ab15577d38 100644 --- a/include/io/channel-socket.h +++ b/include/io/channel-socket.h @@ -124,7 +124,7 @@ void qio_channel_socket_connect_async(QIOChannelSocket = *ioc, * qio_channel_socket_listen_sync: * @ioc: the socket channel object * @addr: the address to listen to - * @num: the expected ammount of connections + * @num: the expected amount of connections * @errp: pointer to a NULL-initialized error object * * Attempt to listen to the address @addr. This method @@ -141,7 +141,7 @@ int qio_channel_socket_listen_sync(QIOChannelSocket *io= c, * qio_channel_socket_listen_async: * @ioc: the socket channel object * @addr: the address to listen to - * @num: the expected ammount of connections + * @num: the expected amount of connections * @callback: the function to invoke on completion * @opaque: user data to pass to @callback * @destroy: the function to free @opaque diff --git a/include/io/task.h b/include/io/task.h index beec4f5cfd..dc7d32ebd0 100644 --- a/include/io/task.h +++ b/include/io/task.h @@ -145,7 +145,7 @@ typedef void (*QIOTaskWorker)(QIOTask *task, * The QIOTask module can also be used to perform operations * in a background thread context, while still reporting the * results in the main event thread. This allows code which - * cannot easily be rewritten to be asychronous (such as DNS + * cannot easily be rewritten to be asynchronous (such as DNS * lookups) to be easily run non-blocking. Reporting the * results in the main thread context means that the caller * typically does not need to be concerned about thread diff --git a/include/qemu/iova-tree.h b/include/qemu/iova-tree.h index 8528e5c98f..2a10a7052e 100644 --- a/include/qemu/iova-tree.h +++ b/include/qemu/iova-tree.h @@ -15,7 +15,7 @@ * Currently the iova tree will only allow to keep ranges * information, and no extra user data is allowed for each element. A * benefit is that we can merge adjacent ranges internally within the - * tree. It can save a lot of memory when the ranges are splitted but + * tree. It can save a lot of memory when the ranges are split but * mostly continuous. * * Note that current implementation does not provide any thread @@ -128,7 +128,7 @@ const DMAMap *iova_tree_find_address(const IOVATree *tr= ee, hwaddr iova); * iova_tree_foreach: * * @tree: the iova tree to iterate on - * @iterator: the interator for the mappings, return true to stop + * @iterator: the iterator for the mappings, return true to stop * * Iterate over the iova tree. * diff --git a/include/qemu/yank.h b/include/qemu/yank.h index 5375a1f195..1907150933 100644 --- a/include/qemu/yank.h +++ b/include/qemu/yank.h @@ -25,7 +25,7 @@ typedef void (YankFn)(void *opaque); * @instance: The instance. * @errp: Error object. * - * Returns true on success or false if an error occured. + * Returns true on success or false if an error occurred. */ bool yank_register_instance(const YankInstance *instance, Error **errp); =20 diff --git a/util/cpuinfo-aarch64.c b/util/cpuinfo-aarch64.c index ababc39550..7d39f47e3b 100644 --- a/util/cpuinfo-aarch64.c +++ b/util/cpuinfo-aarch64.c @@ -1,6 +1,6 @@ /* * SPDX-License-Identifier: GPL-2.0-or-later - * Host specific cpu indentification for AArch64. + * Host specific cpu identification for AArch64. */ =20 #include "qemu/osdep.h" @@ -33,7 +33,7 @@ static bool sysctl_for_bool(const char *name) /* * We might in the future ask for properties not present in older kern= els, * but we're only asking about static properties, all of which should = be - * 'int'. So we shouln't see ENOMEM (val too small), or any of the ot= her + * 'int'. So we shouldn't see ENOMEM (val too small), or any of the o= ther * more exotic errors. */ assert(errno =3D=3D ENOENT); diff --git a/util/cpuinfo-i386.c b/util/cpuinfo-i386.c index 3a7b7e0ad1..b2ed65bb10 100644 --- a/util/cpuinfo-i386.c +++ b/util/cpuinfo-i386.c @@ -1,6 +1,6 @@ /* * SPDX-License-Identifier: GPL-2.0-or-later - * Host specific cpu indentification for x86. + * Host specific cpu identification for x86. */ =20 #include "qemu/osdep.h" @@ -74,7 +74,7 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) * of their memory operands to be 16-byte aligned. * * AMD has provided an even stronger guarantee that proces= sors - * with AVX provide 16-byte atomicity for all cachable, + * with AVX provide 16-byte atomicity for all cacheable, * naturally aligned single loads and stores, e.g. MOVDQU. * * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D1046= 88 diff --git a/util/cpuinfo-ppc.c b/util/cpuinfo-ppc.c index 7212afa45d..1ea3db0ac8 100644 --- a/util/cpuinfo-ppc.c +++ b/util/cpuinfo-ppc.c @@ -1,6 +1,6 @@ /* * SPDX-License-Identifier: GPL-2.0-or-later - * Host specific cpu indentification for ppc. + * Host specific cpu identification for ppc. */ =20 #include "qemu/osdep.h" diff --git a/util/main-loop.c b/util/main-loop.c index 014c795916..797b640c41 100644 --- a/util/main-loop.c +++ b/util/main-loop.c @@ -47,7 +47,7 @@ */ /* * Disable CFI checks. - * We are going to call a signal hander directly. Such handler may or may = not + * We are going to call a signal handler directly. Such handler may or may= not * have been defined in our binary, so there's no guarantee that the point= er * used to set the handler is a cfi-valid pointer. Since the handlers are * stored in kernel memory, changing the handler to an attacker-defined diff --git a/util/oslib-posix.c b/util/oslib-posix.c index 760390b31e..4d583da7ce 100644 --- a/util/oslib-posix.c +++ b/util/oslib-posix.c @@ -671,7 +671,7 @@ void qemu_free_stack(void *stack, size_t sz) =20 /* * Disable CFI checks. - * We are going to call a signal hander directly. Such handler may or may = not + * We are going to call a signal handler directly. Such handler may or may= not * have been defined in our binary, so there's no guarantee that the point= er * used to set the handler is a cfi-valid pointer. Since the handlers are * stored in kernel memory, changing the handler to an attacker-defined diff --git a/util/qdist.c b/util/qdist.c index 5f75e24c29..ef3566b03a 100644 --- a/util/qdist.c +++ b/util/qdist.c @@ -210,7 +210,7 @@ void qdist_bin__internal(struct qdist *to, const struct= qdist *from, size_t n) =20 /* * To avoid double-counting we capture [left, right) ranges, excep= t for - * the righmost bin, which captures a [left, right] range. + * the rightmost bin, which captures a [left, right] range. */ while (j < from->n && (from->entries[j].x < right || i =3D=3D n - = 1)) { struct qdist_entry *o =3D &from->entries[j]; diff --git a/util/qemu-sockets.c b/util/qemu-sockets.c index 892d33f5e6..83e84b1186 100644 --- a/util/qemu-sockets.c +++ b/util/qemu-sockets.c @@ -929,7 +929,7 @@ static int unix_listen_saddr(UnixSocketAddress *saddr, =20 if (pathbuf !=3D NULL) { /* - * This dummy fd usage silences the mktemp() unsecure warning. + * This dummy fd usage silences the mktemp() insecure warning. * Using mkstemp() doesn't make things more secure here * though. bind() complains about existing files, so we have * to unlink first and thus re-open the race window. The diff --git a/util/rcu.c b/util/rcu.c index 30a7e22026..e587bcc483 100644 --- a/util/rcu.c +++ b/util/rcu.c @@ -355,7 +355,7 @@ void drain_call_rcu(void) * * Note that since we have only one global queue of the RCU callbacks, * we also end up waiting for most of RCU callbacks that were register= ed - * on the other threads, but this is a side effect that shoudn't be + * on the other threads, but this is a side effect that shouldn't be * assumed. */ =20 --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693487642; cv=none; d=zohomail.com; s=zohoarc; b=DFYGsUXeVoGIQiXUjOQMzy84Oxpj8cP7kkm/9r8dIP9JG9sCf5Yb7drrXgxSNly2NSYaWBXz22VbH3zsXQOg/zLL1E0VuJEsGwexJlVfOgF9CYYn9mTT9IGBH5NPlyvRwZHqD/VZv+Ts2GmoMPdnGifL2u0SbCVnwCIS5EQ7yOQ= ARC-Message-Signature: i=1; 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Thu, 31 Aug 2023 06:00:30 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, Michael Tokarev , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Gerd Hoffmann , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Peter Maydell , Akihiko Odaki Subject: [PULL 37/41] ui: spelling fixes Date: Thu, 31 Aug 2023 14:56:39 +0200 Message-ID: <20230831125646.67855-38-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487643231100003 From: Michael Tokarev Signed-off-by: Michael Tokarev Message-ID: <20230823065335.1919380-2-mjt@tls.msk.ru> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/ui/kbd-state.h | 2 +- include/ui/spice-display.h | 2 +- ui/keymaps.h | 2 +- ui/vnc-enc-zywrle.h | 4 ++-- ui/sdl2-2d.c | 2 +- ui/sdl2.c | 2 +- ui/vnc-enc-zrle.c.inc | 2 +- ui/cocoa.m | 2 +- 8 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/ui/kbd-state.h b/include/ui/kbd-state.h index eb9067dd53..fb79776128 100644 --- a/include/ui/kbd-state.h +++ b/include/ui/kbd-state.h @@ -65,7 +65,7 @@ void qkbd_state_key_event(QKbdState *kbd, QKeyCode qcode,= bool down); * using qemu_input_event_send_key_delay(). * * @kbd: state tracker state. - * @delay_ms: the delay in miliseconds. + * @delay_ms: the delay in milliseconds. */ void qkbd_state_set_delay(QKbdState *kbd, int delay_ms); =20 diff --git a/include/ui/spice-display.h b/include/ui/spice-display.h index 5aa13664d6..e1a9b36185 100644 --- a/include/ui/spice-display.h +++ b/include/ui/spice-display.h @@ -42,7 +42,7 @@ #define NUM_MEMSLOTS_GROUPS 2 =20 /* - * Internal enum to differenciate between options for + * Internal enum to differentiate between options for * io calls that have a sync (old) version and an _async (new) * version: * QXL_SYNC: use the old version diff --git a/ui/keymaps.h b/ui/keymaps.h index 6473405485..3d52c0882a 100644 --- a/ui/keymaps.h +++ b/ui/keymaps.h @@ -44,7 +44,7 @@ typedef struct { /* "up" flag */ #define SCANCODE_UP 0x80 =20 -/* Additional modifiers to use if not catched another way. */ +/* Additional modifiers to use if not caught another way. */ #define SCANCODE_SHIFT 0x100 #define SCANCODE_CTRL 0x200 #define SCANCODE_ALT 0x400 diff --git a/ui/vnc-enc-zywrle.h b/ui/vnc-enc-zywrle.h index e661ec117d..64fbc90ee7 100644 --- a/ui/vnc-enc-zywrle.h +++ b/ui/vnc-enc-zywrle.h @@ -485,7 +485,7 @@ static inline void wavelet(int *buf, int width, int hei= ght, int level) =20 /* RGB <=3D> YUV conversion stuffs. - YUV coversion is explained as following formula in strict meaning: + YUV conversion is explained as following formula in strict meaning: Y =3D 0.299R + 0.587G + 0.114B ( 0<=3DY<=3D255) U =3D -0.169R - 0.331G + 0.500B (-128<=3DU<=3D127) V =3D 0.500R - 0.419G - 0.081B (-128<=3DV<=3D127) @@ -539,7 +539,7 @@ static inline void wavelet(int *buf, int width, int hei= ght, int level) +------+------+ =20 So, we must transfer each sub images individually in strict meaning. - But at least ZRLE meaning, following one decompositon image is same as + But at least ZRLE meaning, following one decomposition image is same as avobe individual sub image. I use this format. (Strictly saying, transfer order is reverse(Hxy->Hy->Hx->L) for simplified procedure for any wavelet level.) diff --git a/ui/sdl2-2d.c b/ui/sdl2-2d.c index bfebbdeaea..06468cd493 100644 --- a/ui/sdl2-2d.c +++ b/ui/sdl2-2d.c @@ -150,7 +150,7 @@ bool sdl2_2d_check_format(DisplayChangeListener *dcl, { /* * We let SDL convert for us a few more formats than, - * the native ones. Thes are the ones I have tested. + * the native ones. These are the ones I have tested. */ return (format =3D=3D PIXMAN_x8r8g8b8 || format =3D=3D PIXMAN_a8r8g8b8 || diff --git a/ui/sdl2.c b/ui/sdl2.c index 0d91b555e3..ea4a92cd36 100644 --- a/ui/sdl2.c +++ b/ui/sdl2.c @@ -860,7 +860,7 @@ static void sdl2_display_init(DisplayState *ds, Display= Options *o) SDL_SetHint(SDL_HINT_VIDEO_X11_NET_WM_BYPASS_COMPOSITOR, "0"); #endif #ifndef CONFIG_WIN32 - /* QEMU uses its own low level keyboard hook procecure on Windows */ + /* QEMU uses its own low level keyboard hook procedure on Windows */ SDL_SetHint(SDL_HINT_GRAB_KEYBOARD, "1"); #endif #ifdef SDL_HINT_ALLOW_ALT_TAB_WHILE_GRABBED diff --git a/ui/vnc-enc-zrle.c.inc b/ui/vnc-enc-zrle.c.inc index c107d8affc..a8ca37d05e 100644 --- a/ui/vnc-enc-zrle.c.inc +++ b/ui/vnc-enc-zrle.c.inc @@ -110,7 +110,7 @@ static void ZRLE_ENCODE_TILE(VncState *vs, ZRLE_PIXEL *= data, int w, int h, ZRLE_PIXEL *end =3D ptr + h * w; *end =3D ~*(end-1); /* one past the end is different so the while loop= ends */ =20 - /* Real limit is 127 but we wan't a way to know if there is more than = 127 */ + /* Real limit is 127 but we want a way to know if there is more than 1= 27 */ palette_init(palette, 256, ZRLE_BPP); =20 while (ptr < end) { diff --git a/ui/cocoa.m b/ui/cocoa.m index 0c2153d17c..4d8989c4eb 100644 --- a/ui/cocoa.m +++ b/ui/cocoa.m @@ -2045,7 +2045,7 @@ static void cocoa_display_init(DisplayState *ds, Disp= layOptions *opts) =20 /* * Create the menu entries which depend on QEMU state (for consoles - * and removeable devices). These make calls back into QEMU functions, + * and removable devices). These make calls back into QEMU functions, * which is OK because at this point we know that the second thread * holds the iothread lock and is synchronously waiting for us to * finish. --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693487851; cv=none; d=zohomail.com; s=zohoarc; b=hX3K4bR8j+rW1dESYIu0acP6vtszUeMrXhQQdI1yaFZ+3RnkQpw6deHXSdTCgy72b299JeVxonYXNy5OVUImUYoNETzqUf4bUmP6ff9WSGpfAIXky6ewDO+BOcQHaY2Sz6wKvynD0oqDR3sd1CSUTJcqrDfSHIDWFDuTpySavaM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693487851; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Thu, 31 Aug 2023 06:00:36 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Thomas Huth , Stefan Hajnoczi , Markus Armbruster , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Juan Quintela Subject: [PULL 38/41] docs/style: permit inline loop variables Date: Thu, 31 Aug 2023 14:56:40 +0200 Message-ID: <20230831125646.67855-39-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487852471100007 From: Alex Benn=C3=A9e I've already wasted enough of my time debugging aliased variables in deeply nested loops. While not scattering variable declarations around is a good aim I think we can make an exception for stuff used inside a loop. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth Reviewed-by: Stefan Hajnoczi Acked-by: Markus Armbruster Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20230822155004.1158931-1-alex.bennee@linaro.org> --- docs/devel/style.rst | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/docs/devel/style.rst b/docs/devel/style.rst index 3cfcdeb9cd..2f68b50079 100644 --- a/docs/devel/style.rst +++ b/docs/devel/style.rst @@ -204,7 +204,14 @@ Declarations =20 Mixed declarations (interleaving statements and declarations within blocks) are generally not allowed; declarations should be at the beginning -of blocks. +of blocks. To avoid accidental re-use it is permissible to declare +loop variables inside for loops: + +.. code-block:: c + + for (int i =3D 0; i < ARRAY_SIZE(thing); i++) { + /* do something loopy */ + } =20 Every now and then, an exception is made for declarations inside a #ifdef or #ifndef block: if the code looks nicer, such declarations can --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693487370; cv=none; d=zohomail.com; s=zohoarc; b=EKA/YwsQ8shX2G/FzpneGZiZkBKmLcYH1CBIfgnUUqPz6TMpuJjUy/x2cwAzOCZJccuJpjx+NTzu+AhW8DtX5YwmNoh8vig5rfIknnP0QtpkZYkGk6lR0SdWjPdo4pX9uBqlFHWgf0DX80VxsloRi9qBJP2waOhuWt4MnCSY8W0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Thu, 31 Aug 2023 06:00:43 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, Akihiko Odaki , Michael Tokarev , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Thomas Huth , John Snow , Cleber Rosa Subject: [PULL 39/41] meson: Fix MESONINTROSPECT parsing Date: Thu, 31 Aug 2023 14:56:41 +0200 Message-ID: <20230831125646.67855-40-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487399346100001 From: Akihiko Odaki The arguments in MESONINTROSPECT are quoted with shlex.quote() so it must be parsed with shlex.split(). Fixes: cf60ccc330 ("cutils: Introduce bundle mechanism") Reported-by: Michael Tokarev Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Michael Tokarev Tested-by: Michael Tokarev Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20230812061540.5398-1-akihiko.odaki@daynix.com> --- scripts/symlink-install-tree.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/scripts/symlink-install-tree.py b/scripts/symlink-install-tree= .py index 8ed97e3c94..b72563895c 100644 --- a/scripts/symlink-install-tree.py +++ b/scripts/symlink-install-tree.py @@ -4,6 +4,7 @@ import errno import json import os +import shlex import subprocess import sys =20 @@ -14,7 +15,7 @@ def destdir_join(d1: str, d2: str) -> str: return str(PurePath(d1, *PurePath(d2).parts[1:])) =20 introspect =3D os.environ.get('MESONINTROSPECT') -out =3D subprocess.run([*introspect.split(' '), '--installed'], +out =3D subprocess.run([*shlex.split(introspect), '--installed'], stdout=3Dsubprocess.PIPE, check=3DTrue).stdout for source, dest in json.loads(out).items(): bundle_dest =3D destdir_join('qemu-bundle', dest) --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 31 Aug 2023 06:00:48 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, Alexander Graf , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Akihiko Odaki , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Thomas Huth Subject: [PULL 40/41] build: Only define OS_OBJECT_USE_OBJC with gcc Date: Thu, 31 Aug 2023 14:56:42 +0200 Message-ID: <20230831125646.67855-41-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487474140100002 From: Alexander Graf Recent versions of macOS use clang instead of gcc. The OS_OBJECT_USE_OBJC define is only necessary when building with gcc. Let's not define it when building with clang. With this patch, I can successfully include GCD headers in QEMU when building with clang. Signed-off-by: Alexander Graf Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Akihiko Odaki Message-ID: <20230830161425.91946-2-graf@amazon.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- meson.build | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/meson.build b/meson.build index ec14079c67..296f6ef1d2 100644 --- a/meson.build +++ b/meson.build @@ -223,7 +223,9 @@ qemu_ldflags =3D [] if targetos =3D=3D 'darwin' # Disable attempts to use ObjectiveC features in os/object.h since they # won't work when we're compiling with gcc as a C compiler. - qemu_common_flags +=3D '-DOS_OBJECT_USE_OBJC=3D0' + if compiler.get_id() =3D=3D 'gcc' + qemu_common_flags +=3D '-DOS_OBJECT_USE_OBJC=3D0' + endif elif targetos =3D=3D 'solaris' # needed for CMSG_ macros in sys/socket.h qemu_common_flags +=3D '-D_XOPEN_SOURCE=3D600' --=20 2.41.0 From nobody Wed May 15 06:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693487440434100001 Since commit 139c1837db ("meson: rename included C source files to .c.inc"), QEMU standard procedure for included C files is to use *.c.inc. Besides, since commit 6a0057aa22 ("docs/devel: make a statement about includes") this is documented as the Coding Style: If you do use template header files they should be named with the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are being included for expansion. Therefore rename 'bti-crt.inc.c' as 'bti-crt.c.inc'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Message-Id: <20230606141252.95032-6-philmd@linaro.org> --- tests/tcg/aarch64/bti-1.c | 2 +- tests/tcg/aarch64/bti-3.c | 2 +- tests/tcg/aarch64/{bti-crt.inc.c =3D> bti-crt.c.inc} | 0 3 files changed, 2 insertions(+), 2 deletions(-) rename tests/tcg/aarch64/{bti-crt.inc.c =3D> bti-crt.c.inc} (100%) diff --git a/tests/tcg/aarch64/bti-1.c b/tests/tcg/aarch64/bti-1.c index 61924f0d7a..99a879af23 100644 --- a/tests/tcg/aarch64/bti-1.c +++ b/tests/tcg/aarch64/bti-1.c @@ -2,7 +2,7 @@ * Branch target identification, basic notskip cases. */ =20 -#include "bti-crt.inc.c" +#include "bti-crt.c.inc" =20 static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc) { diff --git a/tests/tcg/aarch64/bti-3.c b/tests/tcg/aarch64/bti-3.c index a852856d9a..8c534c09d7 100644 --- a/tests/tcg/aarch64/bti-3.c +++ b/tests/tcg/aarch64/bti-3.c @@ -2,7 +2,7 @@ * BTI vs PACIASP */ =20 -#include "bti-crt.inc.c" +#include "bti-crt.c.inc" =20 static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc) { diff --git a/tests/tcg/aarch64/bti-crt.inc.c b/tests/tcg/aarch64/bti-crt.c.= inc similarity index 100% rename from tests/tcg/aarch64/bti-crt.inc.c rename to tests/tcg/aarch64/bti-crt.c.inc --=20 2.41.0