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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 05/24] target/arm: Introduce make_ccsidr64
Date: Thu, 31 Aug 2023 11:45:00 +0100
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From: Richard Henderson <richard.henderson@linaro.org>
Do not hard-code the constants for Neoverse V1.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/cpu64.c | 48 ++++++++++++++++++++++++++++--------------
1 file changed, 32 insertions(+), 16 deletions(-)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 4cd73779c80..00f39d42a8c 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -24,9 +24,36 @@
#include "qemu/module.h"
#include "qapi/visitor.h"
#include "hw/qdev-properties.h"
+#include "qemu/units.h"
#include "internals.h"
#include "cpregs.h"
=20
+static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize,
+ unsigned cachesize)
+{
+ unsigned lg_linesize =3D ctz32(linesize);
+ unsigned sets;
+
+ /*
+ * The 64-bit CCSIDR_EL1 format is:
+ * [55:32] number of sets - 1
+ * [23:3] associativity - 1
+ * [2:0] log2(linesize) - 4
+ * so 0 =3D=3D 16 bytes, 1 =3D=3D 32 bytes, 2 =3D=3D 64 byte=
s, etc
+ */
+ assert(assoc !=3D 0);
+ assert(is_power_of_2(linesize));
+ assert(lg_linesize >=3D 4 && lg_linesize <=3D 7 + 4);
+
+ /* sets * associativity * linesize =3D=3D cachesize. */
+ sets =3D cachesize / (assoc * linesize);
+ assert(cachesize % (assoc * linesize) =3D=3D 0);
+
+ return ((uint64_t)(sets - 1) << 32)
+ | ((assoc - 1) << 3)
+ | (lg_linesize - 4);
+}
+
static void aarch64_a35_initfn(Object *obj)
{
ARMCPU *cpu =3D ARM_CPU(obj);
@@ -651,26 +678,15 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
* The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values,
* but also says it implements CCIDX, which means they should be
* 64-bit format. So we here use values which are based on the textual
- * information in chapter 2 of the TRM (and on the fact that
- * sets * associativity * linesize =3D=3D cachesize).
- *
- * The 64-bit CCSIDR_EL1 format is:
- * [55:32] number of sets - 1
- * [23:3] associativity - 1
- * [2:0] log2(linesize) - 4
- * so 0 =3D=3D 16 bytes, 1 =3D=3D 32 bytes, 2 =3D=3D 64 byte=
s, etc
- *
- * L1: 4-way set associative 64-byte line size, total size 64K,
- * so sets is 256.
+ * information in chapter 2 of the TRM:
*
+ * L1: 4-way set associative 64-byte line size, total size 64K.
* L2: 8-way set associative, 64 byte line size, either 512K or 1MB.
- * We pick 1MB, so this has 2048 sets.
- *
* L3: No L3 (this matches the CLIDR_EL1 value).
*/
- cpu->ccsidr[0] =3D 0x000000ff0000001aull; /* 64KB L1 dcache */
- cpu->ccsidr[1] =3D 0x000000ff0000001aull; /* 64KB L1 icache */
- cpu->ccsidr[2] =3D 0x000007ff0000003aull; /* 1MB L2 cache */
+ cpu->ccsidr[0] =3D make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
+ cpu->ccsidr[1] =3D cpu->ccsidr[0]; /* L1 icache */
+ cpu->ccsidr[2] =3D make_ccsidr64(8, 64, 1 * MiB); /* L2 cache */
=20
/* From 3.2.115 SCTLR_EL3 */
cpu->reset_sctlr =3D 0x30c50838;
--=20
2.34.1