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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478721; x=1694083521; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7ncdZHIDdNC6GVeCDPftwbMq1HmKWTmiwY6qY4VZq8U=; b=aEvjt0u0Bu6u3bYYHxPJJn4Mq9Vk5hPMg7Q/IQy88XaTlVheJqDtif572k7XE44xWs uKWlF7D2MqfiDcxvJbo44bFzmpXp0+rg5klS6AMTarO3m2qM8jgGp8tisoAf1gLBP8cS 9kYPk8wQtT5BI2lFA1GxIErlI8NOGlpNYYXpxRWuMDuqWKhT/vxYPNYW33dnepOUWUzA mILHAyMN+Yqx5m4BW3smIoZgy4EoWjOSF0WlUSI54I6xNGQ1Nv1GXvsh+hBUlXPmEWM2 Hd79IOT+UmxOrSLUPU6JZoCtXT+bf0X9QU3S5qChFyjCZgE5KENHvuD4IUP3NOR2l7Xk M0kA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478721; x=1694083521; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7ncdZHIDdNC6GVeCDPftwbMq1HmKWTmiwY6qY4VZq8U=; b=FmU85lPQRWpBpsXF7byGKtKT1IZNrxLbq++1AwCEWtBr24hJD8G5bCdeIoXZg3cNUk 7VtBGDo45J9PINo2sDCaZ/Ryz2auJfqdjMH7NlSdXNn7IqrGUQQK+YpPbUBHUaq+pmvR A2Z+47niT16RWJk5pPqKXZIHdzfOfELsCW61ZEC0KOl+HwbaoA+UGVrUlwXxvoeb+Xk6 Zo9UuCnh2wsmpaJedzRc6yKIxywnY5pHi5FlF32naT8pR5WXRd0TM2HJ8fwXPjYR1ceP +D79XKUhWpFGE5iQhQaEZ34YrwsrYu5fS9jq/ZXJGTSeKhGbqUEwdXpfz0ZYwa/tjVR8 kUuw== X-Gm-Message-State: AOJu0Yy+XkLRzaEe3fIvMnaxvpIOy+9eqh+jT6ICY4lzSd6g3eJgVvvQ 9T7PBLMIIJUAiFFkDZvCq9sXE7Bva8ShsgGSvbo= X-Google-Smtp-Source: AGHT+IHIc6YiAhKIEl2ogus9sOmjc1ncuOZtndBaMXMUAZUJ8zPWj4+7BWGHRi7fIpVLAtG9k1FpBQ== X-Received: by 2002:adf:e704:0:b0:31a:d6cf:7709 with SMTP id c4-20020adfe704000000b0031ad6cf7709mr3552676wrm.22.1693478720977; Thu, 31 Aug 2023 03:45:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/24] target/arm: Reduce dcz_blocksize to uint8_t Date: Thu, 31 Aug 2023 11:44:56 +0100 Message-Id: <20230831104519.3520658-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478793427100013 From: Richard Henderson This value is only 4 bits wide. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20230811214031.171020-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cdf8600b96a..a1e604366b2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1074,7 +1074,8 @@ struct ArchCPU { bool prop_lpa2; =20 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ - uint32_t dcz_blocksize; + uint8_t dcz_blocksize; + uint64_t rvbar_prop; /* Property/input signals. */ =20 /* Configurable aspects of GIC cpu interface (which is part of the CPU= ) */ --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478753; cv=none; d=zohomail.com; s=zohoarc; b=SaQ8IgCOCC9fs7uGQytVWdC6s/soUSN0QmxYcaynsDfXQcrjC5yOMmWnTFk2sXheGVwhW5oVajuYHBcnsy70L+w0SqNwRZrMfzJ1D8s5/S1NakehZiALPWZd/9lnH5vgX6/LpDtMdz71T5qlI+2Cz4ZPLT6+PkpJxlcLAQb8FNc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478753; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sqDepVXoZwHSwJpS9MMP5oFVXnn43HF4tsSvcENoNxg=; b=BPnYt4tDSht0fW+RARQcInmhf3C8WzukBdyOd/LUcNP87oJ22wiyFPw2Lvh0fKllWdUuG855xu1llRhaeDR2KnykE/OYt5TU240aaL2vh90Z1HcZEqfCm1jQH2zFILWNzbZNnhlUiTEsWP2Rx8XQgaoQ/H28lDAxRai9/hNjF6o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693478753132282.6502955910489; Thu, 31 Aug 2023 03:45:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbfB7-0003YP-B6; Thu, 31 Aug 2023 06:45:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbfB1-0003Ix-9g for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:27 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbfAx-00042L-Hm for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:26 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4013454fa93so6502225e9.0 for ; Thu, 31 Aug 2023 03:45:23 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478721; x=1694083521; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=sqDepVXoZwHSwJpS9MMP5oFVXnn43HF4tsSvcENoNxg=; b=K6r3kOp4eX2o2hYhCczl6gW/zCKFr4/mi7dO2ngBYv98X9t4JDsqeDaFsYKivYSZ6h bHIQo2/pUKS1Uc1HIbcTluRe05erWe0mzguuvKmSS+cpvGMtpoqlPL/nAshZqd5/JmCc FkwGy5AL9F1uKHc1HphZf2HjAbtWg9xoYHsvRqQ9bqX1D3Hv1jJI2HEabpokT6gNRBAa zuXlYqcWWQOtfXO1LcrwFUqsuElwpDIMIDpt0ggLn+APwNWw/VvwuU2N7vdpGXROKmeJ 0SJhuYxhsFILpcgd68mNKWEwVBecZ7/8mYH2Y5hQntTkjTiF7TVM9EYL5yUBS7QmVKDT Y6Lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478721; x=1694083521; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sqDepVXoZwHSwJpS9MMP5oFVXnn43HF4tsSvcENoNxg=; b=lBDpUQohX7pB8WKQGWseUTdgvZ0vZEYXmPIIJ4k1iDoRc5zw2j1KOhYoOrYjUnmpp7 7pwYIa/AeuE00u7bn2fNjmpTtlJT6VJtmRB/IXMslcKAokjugTYstDloT/k6+25WDU7o 6211UwYfoxiNmTe/b056JQFI350XYT57mdy/f8OCidOfqlgViRM75rnxacIYrk9uh8F8 KyU7UPadXmDXbF+l5yWQM3sz4u+e58+SjwyjVxcWbSjEIqsbwVRsI/aS6J5ozua9Qx0Y q2jf21Sc5ohnYus1BXfIk2/SSmE4LCM36cv1kgxbHi+46vwpBPV8i80spPezwHqszoKn Gs5Q== X-Gm-Message-State: AOJu0YyPtRPj4ZDDcbMJ6qR4f2PRkYQLNOphRsfCLzBpmqRTqoZXaAYh vZpIK16FUn8cdNFUryeOgCyaM9fzMTVIX2OZ8u8= X-Google-Smtp-Source: AGHT+IFk1rINzeKxubee+yLU5yqDsVOJbIFBeaJq+r9MG8F727EucCM+foYdF4eFmyYqJttcsu0IKQ== X-Received: by 2002:a05:600c:2294:b0:401:bdf9:c336 with SMTP id 20-20020a05600c229400b00401bdf9c336mr3995613wmf.27.1693478721367; Thu, 31 Aug 2023 03:45:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/24] target/arm: Allow cpu to configure GM blocksize Date: Thu, 31 Aug 2023 11:44:57 +0100 Message-Id: <20230831104519.3520658-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478755358100007 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Previously we hard-coded the blocksize with GMID_EL1_BS. But the value we choose for -cpu max does not match the value that cortex-a710 uses. Mirror the way we handle dcz_blocksize. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20230811214031.171020-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/internals.h | 6 ----- target/arm/tcg/translate.h | 2 ++ target/arm/helper.c | 11 +++++--- target/arm/tcg/cpu64.c | 1 + target/arm/tcg/mte_helper.c | 46 ++++++++++++++++++++++------------ target/arm/tcg/translate-a64.c | 5 ++-- 7 files changed, 45 insertions(+), 28 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a1e604366b2..278cc135c23 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1075,6 +1075,8 @@ struct ArchCPU { =20 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ uint8_t dcz_blocksize; + /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ + uint8_t gm_blocksize; =20 uint64_t rvbar_prop; /* Property/input signals. */ =20 diff --git a/target/arm/internals.h b/target/arm/internals.h index cf13bb94f59..5f5393b25c4 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1246,12 +1246,6 @@ void arm_log_exception(CPUState *cs); =20 #endif /* !CONFIG_USER_ONLY */ =20 -/* - * The log2 of the words in the tag block, for GMID_EL1.BS. - * The is the maximum, 256 bytes, which manipulates 64-bits of tags. - */ -#define GMID_EL1_BS 6 - /* * SVE predicates are 1/8 the size of SVE vectors, and cannot use * the same simd_desc() encoding due to restrictions on size. diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index d1cacff0b2f..f748ba6f394 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -151,6 +151,8 @@ typedef struct DisasContext { int8_t btype; /* A copy of cpu->dcz_blocksize. */ uint8_t dcz_blocksize; + /* A copy of cpu->gm_blocksize. */ + uint8_t gm_blocksize; /* True if this page is guarded. */ bool guarded_page; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 85291d5b8e2..4dfc51de351 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7748,10 +7748,6 @@ static const ARMCPRegInfo mte_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 6, .access =3D PL1_RW, .accessfn =3D access_mte, .fieldoffset =3D offsetof(CPUARMState, cp15.gcr_el1) }, - { .name =3D "GMID_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 4, - .access =3D PL1_R, .accessfn =3D access_aa64_tid5, - .type =3D ARM_CP_CONST, .resetvalue =3D GMID_EL1_BS }, { .name =3D "TCO", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 7, .type =3D ARM_CP_NO_RAW, @@ -9342,6 +9338,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) * then define only a RAZ/WI version of PSTATE.TCO. */ if (cpu_isar_feature(aa64_mte, cpu)) { + ARMCPRegInfo gmid_reginfo =3D { + .name =3D "GMID_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 4, + .access =3D PL1_R, .accessfn =3D access_aa64_tid5, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->gm_blocksize, + }; + define_one_arm_cp_reg(cpu, &gmid_reginfo); define_arm_cp_regs(cpu, mte_reginfo); define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 8019f00bc3f..4cd73779c80 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -868,6 +868,7 @@ void aarch64_max_tcg_initfn(Object *obj) cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ cpu->dcz_blocksize =3D 7; /* 512 bytes */ #endif + cpu->gm_blocksize =3D 6; /* 256 bytes */ =20 cpu->sve_vq.supported =3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); cpu->sme_vq.supported =3D SVE_VQ_POW2_MAP; diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 9c64def0816..3640c6e57f5 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -421,46 +421,54 @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr) } } =20 -#define LDGM_STGM_SIZE (4 << GMID_EL1_BS) - uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) { int mmu_idx =3D cpu_mmu_index(env, false); uintptr_t ra =3D GETPC(); + int gm_bs =3D env_archcpu(env)->gm_blocksize; + int gm_bs_bytes =3D 4 << gm_bs; void *tag_mem; =20 - ptr =3D QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE); + ptr =3D QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); =20 /* Trap if accessing an invalid page. */ tag_mem =3D allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD, - LDGM_STGM_SIZE, MMU_DATA_LOAD, - LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra); + gm_bs_bytes, MMU_DATA_LOAD, + gm_bs_bytes / (2 * TAG_GRANULE), ra); =20 /* The tag is squashed to zero if the page does not support tags. */ if (!tag_mem) { return 0; } =20 - QEMU_BUILD_BUG_ON(GMID_EL1_BS !=3D 6); /* - * We are loading 64-bits worth of tags. The ordering of elements - * within the word corresponds to a 64-bit little-endian operation. + * The ordering of elements within the word corresponds to + * a little-endian operation. */ - return ldq_le_p(tag_mem); + switch (gm_bs) { + case 6: + /* 256 bytes -> 16 tags -> 64 result bits */ + return ldq_le_p(tag_mem); + default: + /* cpu configured with unsupported gm blocksize. */ + g_assert_not_reached(); + } } =20 void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) { int mmu_idx =3D cpu_mmu_index(env, false); uintptr_t ra =3D GETPC(); + int gm_bs =3D env_archcpu(env)->gm_blocksize; + int gm_bs_bytes =3D 4 << gm_bs; void *tag_mem; =20 - ptr =3D QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE); + ptr =3D QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); =20 /* Trap if accessing an invalid page. */ tag_mem =3D allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, - LDGM_STGM_SIZE, MMU_DATA_LOAD, - LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra); + gm_bs_bytes, MMU_DATA_LOAD, + gm_bs_bytes / (2 * TAG_GRANULE), ra); =20 /* * Tag store only happens if the page support tags, @@ -470,12 +478,18 @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uin= t64_t val) return; } =20 - QEMU_BUILD_BUG_ON(GMID_EL1_BS !=3D 6); /* - * We are storing 64-bits worth of tags. The ordering of elements - * within the word corresponds to a 64-bit little-endian operation. + * The ordering of elements within the word corresponds to + * a little-endian operation. */ - stq_le_p(tag_mem, val); + switch (gm_bs) { + case 6: + stq_le_p(tag_mem, val); + break; + default: + /* cpu configured with unsupported gm blocksize. */ + g_assert_not_reached(); + } } =20 void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index da686cc9537..0b77c92437f 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3786,7 +3786,7 @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag = *a) gen_helper_stgm(cpu_env, addr, tcg_rt); } else { MMUAccessType acc =3D MMU_DATA_STORE; - int size =3D 4 << GMID_EL1_BS; + int size =3D 4 << s->gm_blocksize; =20 clean_addr =3D clean_data_tbi(s, addr); tcg_gen_andi_i64(clean_addr, clean_addr, -size); @@ -3818,7 +3818,7 @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag = *a) gen_helper_ldgm(tcg_rt, cpu_env, addr); } else { MMUAccessType acc =3D MMU_DATA_LOAD; - int size =3D 4 << GMID_EL1_BS; + int size =3D 4 << s->gm_blocksize; =20 clean_addr =3D clean_data_tbi(s, addr); tcg_gen_andi_i64(clean_addr, clean_addr, -size); @@ -13896,6 +13896,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->cp_regs =3D arm_cpu->cp_regs; dc->features =3D env->features; dc->dcz_blocksize =3D arm_cpu->dcz_blocksize; + dc->gm_blocksize =3D arm_cpu->gm_blocksize; =20 #ifdef CONFIG_USER_ONLY /* In sve_probe_page, we assume TBI is enabled. */ --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478752; cv=none; d=zohomail.com; s=zohoarc; b=F6d9zH7dP7eWCkvv5li8Hn/auaIc4vzGZ2valrv+FZiUxMkGBYbMZvSihVz5JYaPK3tPj46LHNHXv1P9UYZHHTCC+fdgMh/vED3yelg8NHdZU6X1MEEnHZoaBzL8mlyVQAhTGCHMwETUO5jH+PRUepaEdS9YShLSMLbtKY5T48w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478752; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0tfdVnStaNkhnripPGAZual0o+sSnkMAkUnDX0QV/9I=; b=IvAZC3jOwJA5sqhMHu3CMmefaCBGGLdCIFBnopLrMxOlzIKYTdRB+8ebYgvgEDiKA7ZgMfN6SVkdzOFuyhXjy4za4Lo3Pgn40LVz7762SBOv9gN5yAX/Bc8TG5OUiTKfL4sEo0ICDp2joITQJbrZnMGC6DMhavErBgmSH1KsXqQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693478752809586.5536108277333; Thu, 31 Aug 2023 03:45:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbfB2-0003NM-P3; Thu, 31 Aug 2023 06:45:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbfB0-0003I3-8r for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:27 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbfAx-00042O-Gf for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:25 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-307d58b3efbso467404f8f.0 for ; Thu, 31 Aug 2023 03:45:22 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478722; x=1694083522; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0tfdVnStaNkhnripPGAZual0o+sSnkMAkUnDX0QV/9I=; b=PIVcoiQxTGhllsoBJP9FcXQa+Kklav2aZqa8f/BAI3REWgi9iL8jfYR2cZXpaTL3FJ ypaVlememSRkq/hW+ZY+/vBg2ma715g9qL4PmAEfmkeAdfUUS+RPt/eT8mzb2DI7mbPu nX3MUk492DxqPAK9MVeVP1ThHqEgl1q+1hkqv/eQicM+BEmpcyVUiAYNFGcxLd1Wds7B joTh5U+YUKZAcllTM4T4jdCaJoPZCdu71k1gbk2JqtvgmAuvEIkI+PNBBFWzNc9v7Ujy zKmMuQU/il9bC0f7mYcMf30saU3qknb5ho/7/+QXCyQyLK2h5woZs4sUTSsXNCTLBDbv 8p3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478722; x=1694083522; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0tfdVnStaNkhnripPGAZual0o+sSnkMAkUnDX0QV/9I=; b=IQ1M9Vgq2O8rPsStlYUYgqiPYf3Kbmds/4gz0S2JsYXf3r6MR5CrdBT29rQmuMdUUp 8HCCNbzEwJK3x9M8bQuJNUpZrJ8tnVzzgYfIbtfHAnKdSn0u/UVnQROtkdvUyZTxeV4g 0JoUaZTcH9B9RZeOBS1v6ENjgharUFKPQ2TDX+A8S6Ey9lnU4Sl5QBpV/p5uMB24u0Ob 441TMHstjVXQ1MAh/omY2peT45j+49+EyJgetn6qZAyJK/Q1t/1h3l8O0zBHtW74dsTo U1rw03x74oU5Q7xO3CdhPfAevtcJ83BplHBex4jBE2r5A+w+RE4BLlv/4wyr8tWYME71 OFsw== X-Gm-Message-State: AOJu0Yxa/jasu8bmUTsTEogNm1s6u5bXL8KXq2aZI33yYbMUm6Dl1AD0 5i4Pfmpy2DKsvHxFQrr8Jqy720FwX3okc5VkMVY= X-Google-Smtp-Source: AGHT+IE6xAaGOeeEqaVsjaYcLY2r+Ef+yhdHYfljzQjiFamkIN8GZaRYr+WesPCwNrnKDYPz1Z+wTg== X-Received: by 2002:a5d:568f:0:b0:31a:d3fd:221b with SMTP id f15-20020a5d568f000000b0031ad3fd221bmr3478186wrv.20.1693478721761; Thu, 31 Aug 2023 03:45:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/24] target/arm: Support more GM blocksizes Date: Thu, 31 Aug 2023 11:44:58 +0100 Message-Id: <20230831104519.3520658-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478754202100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Support all of the easy GM block sizes. Use direct memory operations, since the pointers are aligned. While BS=3D2 (16 bytes, 1 tag) is a legal setting, that requires an atomic store of one nibble. This is not difficult, but there is also no point in supporting it until required. Note that cortex-a710 sets GM blocksize to match its cacheline size of 64 bytes. I expect many implementations will also match the cacheline, which makes 16 bytes very unlikely. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20230811214031.171020-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 18 +++++++++--- target/arm/tcg/mte_helper.c | 56 +++++++++++++++++++++++++++++++------ 2 files changed, 62 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d906d2b1caa..fe73fd8af75 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2056,16 +2056,26 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) ID_PFR1, VIRTUALIZATION, 0); } =20 + if (cpu_isar_feature(aa64_mte, cpu)) { + /* + * The architectural range of GM blocksize is 2-6, however qemu + * doesn't support blocksize of 2 (see HELPER(ldgm)). + */ + if (tcg_enabled()) { + assert(cpu->gm_blocksize >=3D 3 && cpu->gm_blocksize <=3D 6); + } + #ifndef CONFIG_USER_ONLY - if (cpu->tag_memory =3D=3D NULL && cpu_isar_feature(aa64_mte, cpu)) { /* * Disable the MTE feature bits if we do not have tag-memory * provided by the machine. */ - cpu->isar.id_aa64pfr1 =3D - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); - } + if (cpu->tag_memory =3D=3D NULL) { + cpu->isar.id_aa64pfr1 =3D + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); + } #endif + } =20 if (tcg_enabled()) { /* diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 3640c6e57f5..b23d11563ab 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -428,6 +428,8 @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) int gm_bs =3D env_archcpu(env)->gm_blocksize; int gm_bs_bytes =3D 4 << gm_bs; void *tag_mem; + uint64_t ret; + int shift; =20 ptr =3D QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); =20 @@ -443,16 +445,41 @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) =20 /* * The ordering of elements within the word corresponds to - * a little-endian operation. + * a little-endian operation. Computation of shift comes from + * + * index =3D address + * data =3D tag + * + * Because of the alignment of ptr above, BS=3D6 has shift=3D0. + * All memory operations are aligned. Defer support for BS=3D2, + * requiring insertion or extraction of a nibble, until we + * support a cpu that requires it. */ switch (gm_bs) { + case 3: + /* 32 bytes -> 2 tags -> 8 result bits */ + ret =3D *(uint8_t *)tag_mem; + break; + case 4: + /* 64 bytes -> 4 tags -> 16 result bits */ + ret =3D cpu_to_le16(*(uint16_t *)tag_mem); + break; + case 5: + /* 128 bytes -> 8 tags -> 32 result bits */ + ret =3D cpu_to_le32(*(uint32_t *)tag_mem); + break; case 6: /* 256 bytes -> 16 tags -> 64 result bits */ - return ldq_le_p(tag_mem); + return cpu_to_le64(*(uint64_t *)tag_mem); default: - /* cpu configured with unsupported gm blocksize. */ + /* + * CPU configured with unsupported/invalid gm blocksize. + * This is detected early in arm_cpu_realizefn. + */ g_assert_not_reached(); } + shift =3D extract64(ptr, LOG2_TAG_GRANULE, 4) * 4; + return ret << shift; } =20 void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) @@ -462,6 +489,7 @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint6= 4_t val) int gm_bs =3D env_archcpu(env)->gm_blocksize; int gm_bs_bytes =3D 4 << gm_bs; void *tag_mem; + int shift; =20 ptr =3D QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); =20 @@ -478,13 +506,25 @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uin= t64_t val) return; } =20 - /* - * The ordering of elements within the word corresponds to - * a little-endian operation. - */ + /* See LDGM for comments on BS and on shift. */ + shift =3D extract64(ptr, LOG2_TAG_GRANULE, 4) * 4; + val >>=3D shift; switch (gm_bs) { + case 3: + /* 32 bytes -> 2 tags -> 8 result bits */ + *(uint8_t *)tag_mem =3D val; + break; + case 4: + /* 64 bytes -> 4 tags -> 16 result bits */ + *(uint16_t *)tag_mem =3D cpu_to_le16(val); + break; + case 5: + /* 128 bytes -> 8 tags -> 32 result bits */ + *(uint32_t *)tag_mem =3D cpu_to_le32(val); + break; case 6: - stq_le_p(tag_mem, val); + /* 256 bytes -> 16 tags -> 64 result bits */ + *(uint64_t *)tag_mem =3D cpu_to_le64(val); break; default: /* cpu configured with unsupported gm blocksize. */ --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478797; cv=none; d=zohomail.com; s=zohoarc; b=cUKBsAR+quwYv5wBcQJQelrMp+gH+nt2KeROlD3lJAhVmkV0kdZ45oKbsuFN6VWptzVyLFArMIVMzafIdhNFct0M1ByebpjZ0dpoyZbawshhEmQ7aosrJvuG+AGFl7aeSU6mBdvMjiPypX2rmUR4s4zBC2SlyrPjRG1bazyEOz4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478797; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WPpMGXQPxV6Gd1haLOeww5avLvhBkPk1RqCrlh/RzWQ=; b=Ei9nbXxqP68xJx51MRRfHCLxXBF8w3g8xK7t7CHsOC2fvKmp2+ljKGs78o0llG5urgdVkmg/qgEOzDMgJVZUVdxxZR8goXji9HLts4pljcrziTmT9Xpn4FFc3cA8kN5TnhhKvYeDQkbRueizYwCqIpO9/8GsZ3JbNYofjUlfyj8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693478797430797.7934955075403; Thu, 31 Aug 2023 03:46:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbfB2-0003Mc-LJ; Thu, 31 Aug 2023 06:45:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbfB0-0003IA-Tn for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:27 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbfAx-00042S-IM for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:26 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-4020b88bd03so6205185e9.3 for ; Thu, 31 Aug 2023 03:45:23 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478722; x=1694083522; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=WPpMGXQPxV6Gd1haLOeww5avLvhBkPk1RqCrlh/RzWQ=; b=GSiaO5Mrq0HBtOTm7BIT8SaQRCJ/P7rnQ6lSUAfvHJPC8ti7TmR6amdaIHAE9Q1Kf2 RVFuqzkfHi9UEs0RKCqj+e0mPKBXwhOCBvqQuTL3MR33OFHlxBNBYoQkXO/B6INjD5QV NNDOEUMjonyIu04dj5p6wM+4zPAPmFIVqieQwP6ti359KY36TQ10EYujUxebA7yRTIfp EN7NOweN3p19TTHE+sMuvVoh0l0pu0k7UJwVed4A0dNqbJ4sbym5ZeKN5K2voD4AT6LV HuG22nbOLo8YdvwhCXNB9q0RId3GFico8kjW9FVsREC6RdwEzQ4c9hJ6wdtRG0j2YsBU iZ1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478722; x=1694083522; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WPpMGXQPxV6Gd1haLOeww5avLvhBkPk1RqCrlh/RzWQ=; b=f3g1dca25L6RBZ1wd1+DLQgWdtfAHU2PFr+3N8GkFIfilZqpPlagIXIytRr8A6x5H8 wBwPDF1LH8o7GxmWlWEvQiV83BYh1F3GxxSGAzI2FekFJ/UPkz3g4DlaBpduO6SFAMHl Bs3ceWRaWQ/XIP455ICQiaIDaLHVFA+l6CHhJrVu1lbdiOkU5o5dR54cDuY9R98c1B6b PDSK4obu0fVYdIrL2q/HYuRlrQTJhvFonEo9zRdmz1rYgStlionB0Qejn+RN7lpkDHf3 R+oGyRZr1YCGNGSZ717wC9WE88IGXqJGAwhTorloAuLQF6bSD6JkTwLrkSiyF2Uigg4B WFMA== X-Gm-Message-State: AOJu0Yzec6wEAd2gKy2m/F0/huL9StqHujHLIJbz1gezOl0IWhHx/yCt hXFAX8G2+XH+df7cbRlD419dVPvKKpO4aPt4XR8= X-Google-Smtp-Source: AGHT+IGaHFGV1zViONlP5OLtLg19sT4V43IRUVssamJcSgGNsTGcyhpksmeWMmi3/AFLGlYMZ0Z6YQ== X-Received: by 2002:a5d:4089:0:b0:31a:d6cb:7f94 with SMTP id o9-20020a5d4089000000b0031ad6cb7f94mr3528262wrp.23.1693478722121; Thu, 31 Aug 2023 03:45:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/24] target/arm: When tag memory is not present, set MTE=1 Date: Thu, 31 Aug 2023 11:44:59 +0100 Message-Id: <20230831104519.3520658-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478799505100005 Content-Type: text/plain; charset="utf-8" From: Richard Henderson When the cpu support MTE, but the system does not, reduce cpu support to user instructions at EL0 instead of completely disabling MTE. If we encounter a cpu implementation which does something else, we can revisit this setting. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20230811214031.171020-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index fe73fd8af75..23901121ac6 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2067,12 +2067,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 #ifndef CONFIG_USER_ONLY /* - * Disable the MTE feature bits if we do not have tag-memory - * provided by the machine. + * If we do not have tag-memory provided by the machine, + * reduce MTE support to instructions enabled at EL0. + * This matches Cortex-A710 BROADCASTMTE input being LOW. */ if (cpu->tag_memory =3D=3D NULL) { cpu->isar.id_aa64pfr1 =3D - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); } #endif } --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478798; cv=none; d=zohomail.com; s=zohoarc; b=RYj/5OfLfmkiWcxmajTFTqe+obSpTCD6WtTCftjiQYb82hbNW+r1oeDpGijcdIoOQPZfI9Qa1ZuPYacIZWCAd0w36J2EOyxBDWSArmrccqqi+095/V5ahGnu2U5wqlGYpp1Afaysivo25C9zm43SQ4B0Phj3+1i9EWWuOx3kPz4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478798; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Zu723NqO5csexGltvqwm/VR8QzDnvxeiqLGXpa9N4pc=; b=U3VYa8ez5XBfWIOkObVzJy0yxkD2BM2lMo1TsneRFDSzDDl5o+EoC6jw2l7sZuV/ysG6z4q2auJ6bdjcQphPJp66bUXeF0Qng+MsTV/kQ2kJucTQZZAF0MsnQY5ylBPuFGJ41fHnHfXHSVlw1t2e6fMOtFXUNfDUKIVQpGi4sIk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693478798300387.39609329821803; Thu, 31 Aug 2023 03:46:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbfBP-000461-Fc; Thu, 31 Aug 2023 06:45:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbfB3-0003RD-Sy for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:29 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbfAy-00042b-HX for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:27 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-31c6d17aec4so487597f8f.1 for ; Thu, 31 Aug 2023 03:45:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478722; x=1694083522; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Zu723NqO5csexGltvqwm/VR8QzDnvxeiqLGXpa9N4pc=; b=iWLGQauJhDnrprfvNSTZgwF8EPejP+9OuENDLwCm9ja1VbwenkyZ5+0zKqvlvARmXN O5ErTHwULLla+IFQl2/ZAJUiBW8WKMrAogD5/wV+OikWmDL8fJK7nDHYmzGB4shFeTeo oXeWJgx7UvKf/9RjXIrlJGk+d9ZhC2RHJEkeVgNKs2qh5JEjftzfco2f77pfzPMUcSp8 MLBNil0t66qxoJUpG5h6znt4mVPhJaUrSNuKCfqx1Stv8czRQ4249nGn9piIUnH1S4ME MuMQz191QKOWPiek2woQ1RobsZcZbc2dpSDdCvY6WbNcdudgl9xUnP7VrPpryePhT1GY cYSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478722; x=1694083522; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zu723NqO5csexGltvqwm/VR8QzDnvxeiqLGXpa9N4pc=; b=blRYDSNbKk0vlZJMhB79vH/H6JR3CsfFZBj2CSYDfHU3sXc73PJEL1GSxWhkgZyR7Z 1WWOHHX1wsMLvnRQIt8fCirn25OOZdczjslP7712JrpbKHgsuT6OLJ9AfcLT3vjzFlAL srp2oinsNPLXev0RXBLpz4WnltzZ0Plw8FcAmHvRmh1exxw+hpgkfXFpuXHhUq3BZBPl BWPDcvR10XTVJfrTxpSwPNWTJH1PkDpUnp7XzDLiut16MEOguBccQvgj4jBS/A0Jdp90 WNYwsmF4C1nFVBKHoDTOGQai+7r733siwpTXiF38Gm+h00SHdO9KNzKZawB07ncn8Vft jaXw== X-Gm-Message-State: AOJu0Yy3WkrTfAzFWBLMhc0b9Gct0ELDuBSWw20pOJaN4yPylJQ6DvfK Mu2aXNgq+sELj/SYpmT6SBvVXK+RvtaMHeIA788= X-Google-Smtp-Source: AGHT+IFzRxu9YEWApYDLGAPVTsLV+h2jbCTV+TOvQgHX5OgrkpWson76fML6052xode6qnj3olP6KA== X-Received: by 2002:a5d:4c84:0:b0:30f:bb83:e6f4 with SMTP id z4-20020a5d4c84000000b0030fbb83e6f4mr4349409wrs.0.1693478722555; Thu, 31 Aug 2023 03:45:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/24] target/arm: Introduce make_ccsidr64 Date: Thu, 31 Aug 2023 11:45:00 +0100 Message-Id: <20230831104519.3520658-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478800034100007 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Do not hard-code the constants for Neoverse V1. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20230811214031.171020-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/cpu64.c | 48 ++++++++++++++++++++++++++++-------------- 1 file changed, 32 insertions(+), 16 deletions(-) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 4cd73779c80..00f39d42a8c 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -24,9 +24,36 @@ #include "qemu/module.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" +#include "qemu/units.h" #include "internals.h" #include "cpregs.h" =20 +static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize, + unsigned cachesize) +{ + unsigned lg_linesize =3D ctz32(linesize); + unsigned sets; + + /* + * The 64-bit CCSIDR_EL1 format is: + * [55:32] number of sets - 1 + * [23:3] associativity - 1 + * [2:0] log2(linesize) - 4 + * so 0 =3D=3D 16 bytes, 1 =3D=3D 32 bytes, 2 =3D=3D 64 byte= s, etc + */ + assert(assoc !=3D 0); + assert(is_power_of_2(linesize)); + assert(lg_linesize >=3D 4 && lg_linesize <=3D 7 + 4); + + /* sets * associativity * linesize =3D=3D cachesize. */ + sets =3D cachesize / (assoc * linesize); + assert(cachesize % (assoc * linesize) =3D=3D 0); + + return ((uint64_t)(sets - 1) << 32) + | ((assoc - 1) << 3) + | (lg_linesize - 4); +} + static void aarch64_a35_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -651,26 +678,15 @@ static void aarch64_neoverse_v1_initfn(Object *obj) * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values, * but also says it implements CCIDX, which means they should be * 64-bit format. So we here use values which are based on the textual - * information in chapter 2 of the TRM (and on the fact that - * sets * associativity * linesize =3D=3D cachesize). - * - * The 64-bit CCSIDR_EL1 format is: - * [55:32] number of sets - 1 - * [23:3] associativity - 1 - * [2:0] log2(linesize) - 4 - * so 0 =3D=3D 16 bytes, 1 =3D=3D 32 bytes, 2 =3D=3D 64 byte= s, etc - * - * L1: 4-way set associative 64-byte line size, total size 64K, - * so sets is 256. + * information in chapter 2 of the TRM: * + * L1: 4-way set associative 64-byte line size, total size 64K. * L2: 8-way set associative, 64 byte line size, either 512K or 1MB. - * We pick 1MB, so this has 2048 sets. - * * L3: No L3 (this matches the CLIDR_EL1 value). */ - cpu->ccsidr[0] =3D 0x000000ff0000001aull; /* 64KB L1 dcache */ - cpu->ccsidr[1] =3D 0x000000ff0000001aull; /* 64KB L1 icache */ - cpu->ccsidr[2] =3D 0x000007ff0000003aull; /* 1MB L2 cache */ + cpu->ccsidr[0] =3D make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ + cpu->ccsidr[1] =3D cpu->ccsidr[0]; /* L1 icache */ + cpu->ccsidr[2] =3D make_ccsidr64(8, 64, 1 * MiB); /* L2 cache */ =20 /* From 3.2.115 SCTLR_EL3 */ cpu->reset_sctlr =3D 0x30c50838; --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478812; cv=none; d=zohomail.com; s=zohoarc; b=kFP/DtmjsPb3L4dja/AAAM60tNSKgYKoJwUkLtFsJ9w8eAuaMTGLgs399sAQcHTKpYkoOugMzLv3+tWTND2/szUF3qhv1Rt/4448xr5VseEnThALhfUGBepjFzrPvc6tXQKyj1jnnZTg1tdtA75HXPvIAxzggULuYtpq1H4ZU2I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478812; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oe9Jt0sfVfKoVrUXZlvG7DRWxhpDGvcCVkIY29waBDc=; b=ZkuwiRgjk4EYoJutHM+oO6LMtnygUlzts1bHfH/YanlxUdEL61RKe++dmcQzEJJ6h6EISob68G41MjxErV+zk3k2cStbT4+xZGDnp3+NVWt7coOi4F0IpprtGafCZMqPLJ8x5NTVG9mDWeh9xvkF3/VBgLta23drCw2E/Sni9co= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693478812071433.5034744619893; Thu, 31 Aug 2023 03:46:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbfBF-0003ky-KY; Thu, 31 Aug 2023 06:45:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbfB3-0003R9-Ri for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:29 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbfAy-00042j-Ts for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:28 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-31c79850df5so498152f8f.1 for ; Thu, 31 Aug 2023 03:45:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478723; x=1694083523; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=oe9Jt0sfVfKoVrUXZlvG7DRWxhpDGvcCVkIY29waBDc=; b=lvkkLzO+bvzdyed5o+nU44A1670hrKy98KmD13ANtsy/YuzPJFaIF/enadDatb411B 86K8+93J6k3uSZMTk5Ki0fak1JMzqnGFm0ctNLONy7vQmBIT39Cl5X/nEFVhnUUYLNWC PSDv1TMUQ7eGzbJRgT33Ww4pTJrUWDYyyr+nDT7VUs0FG2nEoD8r3tbsta0jB6D7TCim tfCQDzGqqvzyop4uKQwb9Sqs48OtE6MwObijWB0zt2Qw0AknyH7KGzxQYyOefK6nKXo+ gFDKIFZ6NKbVP/R4YhOFSWSrkPuf492/6Sjsuv7SDTqqIdvRUxfJT2FJ8mM37MFkQZMp mZxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478723; x=1694083523; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oe9Jt0sfVfKoVrUXZlvG7DRWxhpDGvcCVkIY29waBDc=; b=gzrkhtxXRVKXew/HPZRe17/7eccYBb8Ij6HwBk3bnIEoUQna3sQDz/MyVRAKaYW6un yUcOOteVqokxq9MgEiMrL3LKV/ElbIAerebGufYVuB0lxm+ht60RpCTH1k4UYXen/4Dz BbbVAF2WFlWXO8ejngsuRxeRQtb6FCbi1pASpfcEjdhAKJnsLacMOmv7uDmvVy+UVW8v DVOL6uL6GhHlhLSHhXIobq8kNaED3rNKz7wsV0pB5o4k0m/E4CLxLcrOS1Qzbeim9Q2w i/kzUSlNFwsk43RZsBHUkh6L5A3LP1SHu8AoND0kCSLoeq+/hcA5Iv1vDNSQOQlGcDL5 xwog== X-Gm-Message-State: AOJu0YxG8efrjYDsIJ51CTJHCrw5ngbkeXLkOLBJUjhr3scfhtdnPqH/ kK0+GaaFH7SK472xvcx5v8ohnz4xjqEMNuo4d8Y= X-Google-Smtp-Source: AGHT+IHX9IOaIbu+WxonB/PHLajx2VfxX9wpj1m8WlBhqlK6EOjlUi2IX428u51cJUFiU7/TxeFQkA== X-Received: by 2002:a5d:6b88:0:b0:319:6fff:f2c1 with SMTP id n8-20020a5d6b88000000b003196ffff2c1mr3736933wrx.38.1693478723010; Thu, 31 Aug 2023 03:45:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/24] target/arm: Apply access checks to neoverse-n1 special registers Date: Thu, 31 Aug 2023 11:45:01 +0100 Message-Id: <20230831104519.3520658-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478814121100009 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Access to many of the special registers is enabled or disabled by ACTLR_EL[23], which we implement as constant 0, which means that all writes outside EL3 should trap. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20230811214031.171020-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 2 ++ target/arm/helper.c | 4 ++-- target/arm/tcg/cpu64.c | 46 +++++++++++++++++++++++++++++++++--------- 3 files changed, 41 insertions(+), 11 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 14785686f64..f1293d16c07 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -1077,4 +1077,6 @@ static inline void define_cortex_a72_a57_a53_cp_regin= fo(ARMCPU *cpu) { } void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); #endif =20 +CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool); + #endif /* TARGET_ARM_CPREGS_H */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 4dfc51de351..e3f5a7d2bdc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -319,8 +319,8 @@ static CPAccessResult access_tpm(CPUARMState *env, cons= t ARMCPRegInfo *ri, } =20 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ -static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo= *ri, - bool isread) +CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) { if (arm_current_el(env) =3D=3D 1) { uint64_t trap =3D isread ? HCR_TRVM : HCR_TVM; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 00f39d42a8c..bc3db798f09 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -463,10 +463,30 @@ static void aarch64_a64fx_initfn(Object *obj) /* TODO: Add A64FX specific HPC extension registers */ } =20 +static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo = *r, + bool read) +{ + if (!read) { + int el =3D arm_current_el(env); + + /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. = */ + if (el < 2 && arm_is_el2_enabled(env)) { + return CP_ACCESS_TRAP_EL2; + } + /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. = */ + if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) { + return CP_ACCESS_TRAP_EL3; + } + } + return CP_ACCESS_OK; +} + static const ARMCPRegInfo neoverse_n1_cp_reginfo[] =3D { { .name =3D "ATCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 7, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + /* Traps and enables are the same as for TCR_EL1. */ + .accessfn =3D access_tvm_trvm, .fgt =3D FGT_TCR_EL1, }, { .name =3D "ATCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 15, .crm =3D 7, .opc2 =3D 0, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, @@ -481,13 +501,16 @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = =3D { .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "CPUACTLR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .accessfn =3D access_actlr_w }, { .name =3D "CPUACTLR2_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .accessfn =3D access_actlr_w }, { .name =3D "CPUACTLR3_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 2, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .accessfn =3D access_actlr_w }, /* * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU * (and in particular its system registers). @@ -497,7 +520,8 @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] =3D { .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 4 }, { .name =3D "CPUECTLR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 4, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0x961563= 010 }, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0x961563= 010, + .accessfn =3D access_actlr_w }, { .name =3D "CPUPCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 8, .opc2 =3D 1, .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, @@ -512,16 +536,20 @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = =3D { .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "CPUPWRCTLR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 2, .opc2 =3D 7, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .accessfn =3D access_actlr_w }, { .name =3D "ERXPFGCDN_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 2, .opc2 =3D 2, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .accessfn =3D access_actlr_w }, { .name =3D "ERXPFGCTL_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 2, .opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .accessfn =3D access_actlr_w }, { .name =3D "ERXPFGF_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .accessfn =3D access_actlr_w }, }; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478723; x=1694083523; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=QU826JqtU7kXfHncN4gi9tl/7HUQ0VtfB7fV2Nl8dBc=; b=YeKRlXTj0+WXFWQlCGUiAd0vr6ROVJrc+afALHKqLcfMs+smwrybcsHfRA41KcIgJV 9z9F+VGVYMYkv62Decb+Ld/AX6vowBDWQe0IvricA1Abx5jQsiRALQmR6U3scrJtNGvg FI0t6Kd+8t3wwDEKCkFh619+wACjM0Dia+4KBu/y8uUn9i2/YJErWPMnanLqV/B3Q89U 2kTJpHQoeMM3y7MLSDU20wNJzbJctqXzK0WxBz5HaTGXsd6iaoy8NLNbqOcQQuAxyg/5 IA3DfShZzLxcMpiV8zi+I9FQ2IDH2AgrMOy1zuXQFYudADyeRM+vQy5mKmz4cuQGPfHr XS1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478723; x=1694083523; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QU826JqtU7kXfHncN4gi9tl/7HUQ0VtfB7fV2Nl8dBc=; b=ZsPPK8F+vGLeY6e2o7jCwqLXQ4LoktV6aFYf1CFKkPuXki3Dtxz8qk5dWIPOye7WkF X+CqsFWUnzWbgxDYg10CmqbVE7c2nX/cRGukQZzVBtGv/LHPLQ5+jcyJ9H4P2MEX8M5l 4MupLnqHUGOI8c6DJvQnw3X2mGfriLDWgWVfXaCWjSh/YSU5juwlIRbZBuxNsuOSlrPH aUplBnoR/yhVseOJlzenVUo77AhTmrDRj6GZuwK95DdN84xZKo7GuWFPq0Ou+bJsY32T F/Nk3K1yau2Ej1CqdzlCeTOlvIYCm674uE5swNbg6pdTkLcaOiZeFrYbmG2FOF9wDSYy gefg== X-Gm-Message-State: AOJu0YxqC8+VgQ4uoVyTjOo+8tkE1gx/QTLohfJdXDH+qug57o1gNh9r yLj7+h+XGXmoa47LkhCVJZhm0ccMLBIhEUsQQPs= X-Google-Smtp-Source: AGHT+IE3yjCcSMPir6ZLvfzEHPlfYLSBC1/0jt8MiFXDu1l1sR4SP6GABt1BZuGWHy29+BIUi3poiQ== X-Received: by 2002:a05:6000:4d:b0:314:3740:7f69 with SMTP id k13-20020a056000004d00b0031437407f69mr3464811wrx.37.1693478723527; Thu, 31 Aug 2023 03:45:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/24] target/arm: Apply access checks to neoverse-v1 special registers Date: Thu, 31 Aug 2023 11:45:02 +0100 Message-Id: <20230831104519.3520658-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478764628100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson There is only one additional EL1 register modeled, which also needs to use access_actlr_w. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20230811214031.171020-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/cpu64.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index bc3db798f09..b0cac05be65 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -560,7 +560,8 @@ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) static const ARMCPRegInfo neoverse_v1_cp_reginfo[] =3D { { .name =3D "CPUECTLR2_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 5, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .accessfn =3D access_actlr_w }, { .name =3D "CPUPPMCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 2, .opc2 =3D 0, .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478861; cv=none; d=zohomail.com; s=zohoarc; b=koHw1NQa2CCLH2fetb6TNUTaG6T+QPGCc3Vc7TVsZKZ5W+yGyrvxwiAOPEvBHXRYfAP5yjNg/WFyH6wo7OoGR6x/W2Q2XVjQ0KAKoseTd3k3GUnZ80Nic2asbNL+ETn5eyR5KxsDemDZ8haP5NEvwjNDvQPIvI8Cw89ZbUFQ0KI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478861; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pajFn5q5HPV3atNa2Qh8ORUExlGjK7L5LypBPDHo1HM=; b=EMkf+0ieP1OGFrEkw5SmI/cBWh92Ibo8oeJA+I59N9M49sNw3aWtXcZCRtoUywuMIAZGUxG/AksN0o2qD4uUKANFCi6AfUzHYRH3Ai1vYMJ4iYOeXQec3XxyVxKzjFSpcJpf2cD9Ram/ybV6j57QMfWFoILAypgBxmXmumwzHOY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693478861847966.4616329449203; Thu, 31 Aug 2023 03:47:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbfBJ-0003pk-QK; Thu, 31 Aug 2023 06:45:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbfB5-0003YU-Le for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:32 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbfAz-00042z-77 for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:29 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-31aec0a1a8bso385342f8f.0 for ; Thu, 31 Aug 2023 03:45:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478724; x=1694083524; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=pajFn5q5HPV3atNa2Qh8ORUExlGjK7L5LypBPDHo1HM=; b=BaRtFNEJJ5W1UM2Hh+CrOYeNds0sBEx+slhr3fAqbZJMpKmXLDRzmT/cLklrVAgius pB5iflugSnWjf6O7iDON8xyvGOUMKzbhtFPGQjk/Xq8vye5fz6Lwvn4oyQmCQdeERcTN YMwoINH1uVnvCxwbuFkg00s/fO3NyWtg72rKZtHaLWIcoKrIiAqG92O14FXkqkpa15IX sbSLn876+zirLwHMIGMDpVs2Ra0HMDdO9l6qLW5O/74TqTghQss7YAdileGYZlY1m9fo amqd4u+YL9e0u5JuXQ/4aQ0BFwKnDcljklrwfiygnuhTW10hXYtTVhhPPN4Ax+HJVEt0 7bHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478724; x=1694083524; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pajFn5q5HPV3atNa2Qh8ORUExlGjK7L5LypBPDHo1HM=; b=cQWV+YT/64OSqd08CvVjowJ/3Kyto+en8mWXojIFgmGdGCQAC17/ej5rprzLkuQaM8 aoxaIc7dWuNanndz6AfsZpHan56MbId7Qc7o8kj0eeiR+vXVMfXQJ8IxxUW0nEKnYmTo okuXELUfWfjAgFWF3jZHUZRATRcJDoxNgiPfQMMaMDBdP2yxBJMX7VckefY5TllzpHHT bz1SrDNVfZMdJ8N0vbPkqtCtagz2/M+7HEcAXOtixl2KQdJOjzE5h4U2mSCjIvNg8CJR 4YEdk0Wk+0ADjevhVAdYwRqxvIz4Oh84JKgqIhpa8eXzMRGt0jy6E7bzCmsWZDshM9Cd lLRA== X-Gm-Message-State: AOJu0YxOL6X8C5Ru0QYfLg9evjaGnoKQltrtn3Qo66a4VDkXf66AZDNF G5FWKbIOM3ulnAN9b5JK4W9GTMYLDh/iQ6vLmwI= X-Google-Smtp-Source: AGHT+IEu+lnPZCXerFo5AlGRHwRUnX2yDh869Pq09WbXcD8dxXfFYSx1hbV4rQqq/dUiMhF8zILi1w== X-Received: by 2002:a5d:4c45:0:b0:317:dcdd:3fa1 with SMTP id n5-20020a5d4c45000000b00317dcdd3fa1mr1953110wrt.34.1693478723945; Thu, 31 Aug 2023 03:45:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/24] target/arm: Suppress FEAT_TRBE (Trace Buffer Extension) Date: Thu, 31 Aug 2023 11:45:03 +0100 Message-Id: <20230831104519.3520658-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478863572100007 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing external to the cpu, which is out of scope for QEMU. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20230811214031.171020-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 23901121ac6..17540300feb 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2088,6 +2088,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) /* FEAT_SPE (Statistical Profiling Extension) */ cpu->isar.id_aa64dfr0 =3D FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); + /* FEAT_TRBE (Trace Buffer Extension) */ + cpu->isar.id_aa64dfr0 =3D + FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); /* FEAT_TRF (Self-hosted Trace Extension) */ cpu->isar.id_aa64dfr0 =3D FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478793; cv=none; d=zohomail.com; s=zohoarc; b=aVMqlTeQ/Bcr9GCPo38l4JF3qQGyQPbSXmYvkrYA1LZet0sJMa5FfbCSetaQCvfEX5dYJpvQgSOQO/zBXAGdDVG5yJW9e4XN7yx6TjQcKffFdIPuCeyoKu+kLnfMNjG59ZecxtPJsFl2jaWzppqLd9vSkRd7UevRZ5hoq9059Zg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478793; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lVOuGivkVkqx+z9AuvvbwwEp8j+j9CudGauQPKqJ+z4=; b=KipLimpPRvDqNK/94xLgDwu4DuWF3XTNdMH3R/rBWDrbMxkbisQaPhSKn/RKYnaPPiy3pDw8rXp/oL9sB28jkGiwSdngsU1V4Gk4yqyGZrSKBOG11r1XBewyw6YTbZcBGROIOMLjufnF0MA52/yC/AF5M2GWgsGwD9nfyuw5XMo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693478793593951.3984589765195; Thu, 31 Aug 2023 03:46:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbfBF-0003in-1m; Thu, 31 Aug 2023 06:45:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbfB5-0003Yc-NX for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:32 -0400 Received: from mail-lf1-x12a.google.com ([2a00:1450:4864:20::12a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbfB0-00043E-BS for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:30 -0400 Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-500cefc3644so1337371e87.3 for ; Thu, 31 Aug 2023 03:45:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478724; x=1694083524; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=lVOuGivkVkqx+z9AuvvbwwEp8j+j9CudGauQPKqJ+z4=; b=Ul281Byx4L6d9kX41iMTaNRW4X8HaIRHb2mtMCIDB4wgoAelGdSaNqZq1n6kil7s3q XOIlVCCFYTyljiP29JodVNqXAXnWQTdjDleaJdT0HOVvqmO3c4HPfsX77rb7+VVe3NOT w7H71sOLEEdwuUfqBXDrrr1eDmtsRfAXnZJZNW0K62zCokJPQO1VD9cjknZ7QNJuiSx0 tBV3U12PQZwlAVTeD5Fee9+W4U1RP1ZEetlLVbyVqCKWWg1UJDiApgvynG3Bqii7xQer F0YrxTbClSWvCw5IDheoOGWmyLsIsUIn6hcQTYbNu9Xfte7UuHue8IxvZFFir6Vadgtv /H/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478724; x=1694083524; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lVOuGivkVkqx+z9AuvvbwwEp8j+j9CudGauQPKqJ+z4=; b=MwUBk93RY4ixLf/9EomUbJvOkZZv/LDkKBQV9XL/9mbvQLLggch2hcORTG8uaFRX2p W+pgWT8Wg61Q7KmcJR1fluXLA/SdggLYTqDy5DBHMyEGHBUL6usbhoPpEeIarNg6BcOr I3jgIdFSpMicdpXUmcHGKfyQSaiMb9Jb3YgiMumX3+v3A9LdaBCedou1dsOlfuQalMMf kNA/qXV9GU+4NlyCgbuSB9rEWbUxg4MTSVHibVhqNVb/oYSKEKIlxaKVkhT7Dz6FMHkQ g+D+RIQGQ4ffWyFbMa4NdelW5Opk+Zq8Aj8Y9WGw81otqucLgC0V1zEg54FE/y+Ci69X D5jA== X-Gm-Message-State: AOJu0Yx6NaXsyvfrm1ecIl3JLJlf9ebY4+PgB3mwoKzts2j0lZt8x3V6 kVwmwrieRVqksMXjuHm6wiBslQpjtAOvIUxSv0w= X-Google-Smtp-Source: AGHT+IGgLxujwfxheEb+litsZND+9orQgtHvA7BiZtNrJZcJejuhR2uyDw7g4DCfZvkBv8/zoO7OYw== X-Received: by 2002:a19:7b06:0:b0:4f8:5d0f:c779 with SMTP id w6-20020a197b06000000b004f85d0fc779mr3382119lfc.40.1693478724348; Thu, 31 Aug 2023 03:45:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/24] target/arm: Implement FEAT_HPDS2 as a no-op Date: Thu, 31 Aug 2023 11:45:04 +0100 Message-Id: <20230831104519.3520658-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12a; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478795764100019 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This feature allows the operating system to set TCR_ELx.HWU* to allow the implementation to use the PBHA bits from the block and page descriptors for for IMPLEMENTATION DEFINED purposes. Since QEMU has no need to use these bits, we may simply ignore them. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20230811214031.171020-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu32.c | 2 +- target/arm/tcg/cpu64.c | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index bdafc68819b..2012bbf7c7c 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -40,6 +40,7 @@ the following architecture extensions: - FEAT_HAFDBS (Hardware management of the access flag and dirty bit state) - FEAT_HCX (Support for the HCRX_EL2 register) - FEAT_HPDS (Hierarchical permission disables) +- FEAT_HPDS2 (Translation table page-based hardware attributes) - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) - FEAT_IDST (ID space trap handling) - FEAT_IESB (Implicit error synchronization event) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 47d2e8e7811..1f918ff5375 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -62,7 +62,7 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_mmfr3 =3D t; =20 t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index b0cac05be65..11e406d960e 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -852,7 +852,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2); /* FEAT_HPDS2 */ t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */ t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478812; cv=none; d=zohomail.com; s=zohoarc; b=hiTvTUAiSwb+6QMkhIGvaN84Rk7ouR09bhAHg9dAUqLWIyVHfyefBWTKfj0nbG9EK0+kqqwSAnOhHOPVZjw7ShVR/paiYK8M0NC66RP3la9u02Eck+z3ZbDOTLqIIfBZJcf5Nh5mJC1RFRWV8jlFXfep5c3D/IOOmI4yoPHaukQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478812; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=V+aecnBNWTPodaj6GhkLLfWe+WYRhpIxXHTBKvGRaTA=; b=KKVTDnsXp0bzDVVgrGfwjEBlK7erkGgBXsLtUwP4ryo9pXFW5A4JCsnbReHOjckiMkvUUHu2N5kwtdNzlk6PCL1CrY6W9xPNMybRQcFfUFBIPJIlUOsLCZAs6512pg83JJy5ciCcdrIZG9hA8XOw9J46InX654e8VtoH0CxTNO4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169347881219984.81881085647171; Thu, 31 Aug 2023 03:46:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbfBF-0003m1-SP; Thu, 31 Aug 2023 06:45:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbfB5-0003YS-L9 for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:32 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbfB0-00043J-BV for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:29 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-3fef56f7248so6271045e9.3 for ; Thu, 31 Aug 2023 03:45:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478724; x=1694083524; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=V+aecnBNWTPodaj6GhkLLfWe+WYRhpIxXHTBKvGRaTA=; b=fh1M1XCJLQCVkbRJMHus0gXfPC4AGFC7G44pvZlyHtKjhOLEGkdCIaT2D2i+gRQk1c kST7dXOTwQXVkj2YpHPhPhRLDr7ZPzEb54hRn3QcU6g2/4puRjOD4AVzc83PqrQIu+xI 4rIchycNTGlpiz1iwQ0ijkbS0fCTvZYm9ODQRcCRzaqy0CALTr5CsrKH//GmXAtMXFa2 fl1l6/7HoqYjkgBSVtmCYPnfM2PnIACDS/fYI8dU8zvw/Q1BaYQRQ3cY3OiXQlevr7gL UFyebQPEH1uh7o95SHW3jzdKAj3iZS2vR6nrSHAbzwps24z36KeL2BrO9K8uL3UUvk+N 8YyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478724; x=1694083524; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V+aecnBNWTPodaj6GhkLLfWe+WYRhpIxXHTBKvGRaTA=; b=KaNIPnLCYFIPIgm+1dhkPZuCKQPq1aaJPEzq7izWr6zd0efbiw/DAfa843C61BewJm iq4opbjGrLPxgZeeh7uZNFHI4V07OltxRVg+7aXC5OjYC2PgIx54GNTnf4Jvxkiq4wLH gyxqFf4lLQoboYU6xnVVukd7jlnCSVJQg8YcWB20r9VGK5ATgiEJvHb/5MONxk+rH3V+ 7WgoG0pZ42045sg0ta/hMUQ3yIWfSt/Dkll6T6yrPJj9Ff2BC/bcGWmlmvrcoyi9L+kD JMWiAOIhia+MpTIggh4nFUjLbQZlU19kiydE0ZQjfXr2dyhOKmPGONtBVrhej1Vd+1zr uREQ== X-Gm-Message-State: AOJu0Yz6Vv8nlJz235vxPnY8GyMiP99D2nniw5+P/tKYHPor+IUyHI+Q jFMGVqvyXfIpjc7iU0u5WOKYs/x/eNiPVuVBzvk= X-Google-Smtp-Source: AGHT+IG3nYL3qkfDouOa42DG57oIWH1GVP/+iNPT2+7oqm5PsCGheRoMzi5hcEYB8vCnxT99BGT9EA== X-Received: by 2002:adf:f0cd:0:b0:317:5722:a41b with SMTP id x13-20020adff0cd000000b003175722a41bmr3690931wro.7.1693478724757; Thu, 31 Aug 2023 03:45:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/24] target/arm: properly document FEAT_CRC32 Date: Thu, 31 Aug 2023 11:45:05 +0100 Message-Id: <20230831104519.3520658-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478814397100011 From: Alex Benn=C3=A9e This is a mandatory feature for Armv8.1 architectures but we don't state the feature clearly in our emulation list. Also include FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Alex Benn=C3=A9e Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org Cc: qemu-stable@nongnu.org Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org> [PMM: pluralize 'instructions' in docs] Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 2012bbf7c7c..2e6a7c8961e 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -14,6 +14,7 @@ the following architecture extensions: - FEAT_BBM at level 2 (Translation table break-before-make levels) - FEAT_BF16 (AArch64 BFloat16 instructions) - FEAT_BTI (Branch Target Identification) +- FEAT_CRC32 (CRC32 instructions) - FEAT_CSV2 (Cache speculation variant 2) - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 11e406d960e..0f8972950d6 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -788,7 +788,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* FEAT_CRC32 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478859; cv=none; d=zohomail.com; s=zohoarc; b=G1lVxjNyMwhPHAT/KvLQGPx09mgis19VLLE2Z6Y5Ira4hXvsjEYIT8BWMFjRjGKo1fhXhDAECH5vkaaupizX2d9IHZwA3mC/sju48dZ23jWWuTM4s0DRkPNmbXuMNgQfhcP5sD3061kv3XHuZSKMK1O8nKEpz2/mnctYkTzV69w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478859; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kyRjWza4FydApFPcQyrvxJM4UV9pQPcxGBS07VokX2o=; b=AUvT5ngma1kh8uV4igNwKTYWTfZvkCsPNLBkRTt2Vyf0PDkQEzaNP2yvg1sLTHsdnKRR7cRcSmEoidsM+ewXy087QqNZ0Zpt4t63MLUbKg73MY8BilTapL/6tLMZddaZvfzrn3nBS559SGGI5lW5ra8ZYlC2d45bOROjxUxY02U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693478859286589.2838891098386; Thu, 31 Aug 2023 03:47:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbfBQ-00048k-1f; Thu, 31 Aug 2023 06:45:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbfB5-0003YT-Lc for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:32 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbfB1-00043Q-1K for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:30 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-400a087b0bfso6273995e9.2 for ; Thu, 31 Aug 2023 03:45:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478725; x=1694083525; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=kyRjWza4FydApFPcQyrvxJM4UV9pQPcxGBS07VokX2o=; b=C7eTEmu3wRM/GH5sFLOAWRD0yxRvp7ZGhRFko1yr/vclm3w/PHUNgLx3KxLiPzzKoi 06gLZxw4nuFzkGm0kcoeEU7w0inGNMJNut5Qz4zo4Nth6h8r9/f3EFjXTMqoyjBlnmdH hLO79aBU/rJVCdWJDuASwdT+Fw1w02X5dbelEiXfLmuB/TCp9nS8AnJf+7uTfagSSKtA zGVqVjBHodGG6U39mxAL0tQ1biqrjKDauBMvpS3o4KqEPxN2Iqin7rBWZIKdeC0ui54q 2CmeXAj9fCADQhBc+v112McuX+fgjwYAgxYMl4Ptr8GLEifIo/vacgExqZ3X6uNDZC8p +DHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478725; x=1694083525; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kyRjWza4FydApFPcQyrvxJM4UV9pQPcxGBS07VokX2o=; b=NzD2iY47Y7aQscW127vRYSOJmEuAtCmq3PV0b0JGCMhgxBIgClfm6o8mKXA3nyHND9 hh9TqatgsOy4As3rnVILRLoW0nSlq1ZhQf4EjrZi9Y2ER0200vWyoVWrqgn4pbW3TJyX z+F0kSidQbSYsCTBpd72Or7mmj+Wh8CUpWZb8vF2I64z1WL/naxT7etRGpSsrRnQUbwr sNS0dbuFaWTIK2k39jPDfxAUcYKj5XqsaK8YSFluDnjcpGH6oV3ucBkQgvBXBSrWZPpO /y17I4EGmwxQ1nHawrM8bxT6bl2qNBod6YCZhnjhsoq9zhe7KDzjT6tNSnPsGUdsJkOB nQLw== X-Gm-Message-State: AOJu0Yx5C3DAkrkG2gAP/t8pBbmMe4MmZpwPnc2e1qp4bk5UDVu+2oek bEoIf3jKMu74Vrkb5EsvGY+UU+eRPwAbN9IpiXU= X-Google-Smtp-Source: AGHT+IHqm88wppzu+ELKGeMzH7jpjKjbcJ0zUsOkGun5lTH4ATRAwMRmj2lMLxeWWfqmF4YS0hv5lw== X-Received: by 2002:a05:600c:228e:b0:3fe:ef11:d79f with SMTP id 14-20020a05600c228e00b003feef11d79fmr4159542wmf.36.1693478725135; Thu, 31 Aug 2023 03:45:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/24] Remove i.MX7 IOMUX GPR device from i.MX6UL Date: Thu, 31 Aug 2023 11:45:06 +0100 Message-Id: <20230831104519.3520658-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478861250100003 Content-Type: text/plain; charset="utf-8" From: Jean-Christophe Dubois i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device. In particular, register 22 is not present on i.MX6UL and this is actualy The only register that is really emulated in the i.MX7 IOMUX GPR device. Note: The i.MX6UL code is actually also implementing the IOMUX GPR device as an unimplemented device at the same bus adress and the 2 instantiations were actualy colliding. So we go back to the unimplemented device for now. Signed-off-by: Jean-Christophe Dubois Message-id: 48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tri= budubois.net Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx6ul.h | 2 -- hw/arm/fsl-imx6ul.c | 11 ----------- 2 files changed, 13 deletions(-) diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index 9ee15ae38d6..3bec6bb3fb7 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -22,7 +22,6 @@ #include "hw/misc/imx6ul_ccm.h" #include "hw/misc/imx6_src.h" #include "hw/misc/imx7_snvs.h" -#include "hw/misc/imx7_gpr.h" #include "hw/intc/imx_gpcv2.h" #include "hw/watchdog/wdt_imx2.h" #include "hw/gpio/imx_gpio.h" @@ -74,7 +73,6 @@ struct FslIMX6ULState { IMX6SRCState src; IMX7SNVSState snvs; IMXGPCv2State gpcv2; - IMX7GPRState gpr; IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS]; IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS]; IMXSerialState uart[FSL_IMX6UL_NUM_UARTS]; diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index 2189dcbb72c..0fdd2782ba5 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -63,11 +63,6 @@ static void fsl_imx6ul_init(Object *obj) */ object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); =20 - /* - * GPR - */ - object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR); - /* * GPIOs 1 to 5 */ @@ -537,12 +532,6 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error= **errp) FSL_IMX6UL_WDOGn_IRQ[i])); } =20 - /* - * GPR - */ - sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR= ); - /* * SDMA */ --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478862; cv=none; d=zohomail.com; s=zohoarc; b=A9Q9LmOJZX/+g7OYSYg5uE8Hj1Hf0OQrsHpkoCy+grAvBulX6iAVjWkvfcpmfTHYd4jzrwlmfwMxDhkBkmxiBIqaR9sloUi/uHztKX3ZjcbeHu8k9zeQS1O5SKX4TfZPQRsDBOZQSbDEO16U3Wa3RqRUR8/o48N3He2NadZH51I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478862; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TezHjCyr/pegc2JSFZbMQFCmEx4buRUZ+C0WWCBvLyA=; b=fPL4/ZSS+nA+sEBg7fkjXHJeYlLkzF+n122zdG33PCgxRPUXt1BpqRjCR7GRtt+wrHiNlnp5COe9wVNJgOkysC+JQIMsIIRUqvuoWvEbzzOkw7HJRUyJbGh3evubDQopdD4XWWk1TzPvczc8lQUAv+yT1kbxBoBKphyLPj2XP4I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693478862041697.553646120724; Thu, 31 Aug 2023 03:47:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbfBM-0003sd-MC; Thu, 31 Aug 2023 06:45:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbfB7-0003ZZ-H0 for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:34 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbfB1-00043a-0h for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:31 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-31c6d17aec4so487632f8f.1 for ; Thu, 31 Aug 2023 03:45:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478725; x=1694083525; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=TezHjCyr/pegc2JSFZbMQFCmEx4buRUZ+C0WWCBvLyA=; b=rvb5iCvZJx8bzOofSYdubFG6qOUt7hupKBvFZCq5tLAxLRpmzn/ySMVMa4WpjtK+R0 yk3SyA/GM95dUgpnHzWxiSQ7puuqcMgAf82hs2BM2o35/AOB8ra6ZIT+LfbVKZUiYxpV kIqmQAjb+ZsHwA2KNR0AP8rOTrEUTfTFGyS03j90MdTlfpS4LIYftmJ562lqYP7KvQpu IHkY5S3+HrKl6RoVdH5jlHrwu3BY2uRr6xoLhb9GFsxBoetmwgDS8VjXMWI3eLk2Z9Q9 DLD0j5+YFg3S5rd0rVLgQfts62QtwiRtVyc3ljVZhWOacm/MoYz2loiwNdtM8qBCjuDS yLvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478725; x=1694083525; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TezHjCyr/pegc2JSFZbMQFCmEx4buRUZ+C0WWCBvLyA=; b=WA4rCyzaHi60GQML39T/SN5StVBNR/pf25lHY9vf1cE2wb88oUdu+RkPXLwgqGHY7A 6iDimBF8RfvDf5KNRdC2obkF55YVfkk/TWFTyN8dgi7Yf/m13z6fh6onHzmVbH0pj5CT QxPlQcQlRtkzDxQS+gmmWSFJyISwUIRYbau6yITRYzP50tdzsQm54eUx8C46s/WjaTlX D+q8bh1fZx8UrT4p4oM/ckrBeumGoFeHajh/YA8dNQ5okNXzAvn4C2ni/uavgGAgWnu6 tGLGqirw1ge8fYJ0SpW23XRldWKVDWYClfY+EdIIslsP80OIN62c8Gkp7nRkuyY3v14o 4HGw== X-Gm-Message-State: AOJu0YxtDUppYQGxz/LDCF3Kn9nkTwTbX0grG57QnUqW8s+VeEgSu52H voLtngqw5/kqfJT5B1A4Z4UYHPWr/env8QAEO6Q= X-Google-Smtp-Source: AGHT+IHBje37cOadb/jbpCf+yPrKnnuAp7CsbEg+ree+CjVFwxnkHtMw3C9pucEKIPZQ93z+fSu6ww== X-Received: by 2002:adf:e809:0:b0:31a:d2f9:7372 with SMTP id o9-20020adfe809000000b0031ad2f97372mr4232313wrm.29.1693478725570; Thu, 31 Aug 2023 03:45:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/24] Refactor i.MX6UL processor code Date: Thu, 31 Aug 2023 11:45:07 +0100 Message-Id: <20230831104519.3520658-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478863590100008 Content-Type: text/plain; charset="utf-8" From: Jean-Christophe Dubois * Add Addr and size definition for most i.MX6UL devices in i.MX6UL header f= ile. * Use those newly defined named constants whenever possible. * Standardize the way we init a familly of unimplemented devices - SAI - PWM - CAN * Add/rework few comments Signed-off-by: Jean-Christophe Dubois Message-id: d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tri= budubois.net Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx6ul.h | 156 +++++++++++++++++++++++++++++++----- hw/arm/fsl-imx6ul.c | 147 ++++++++++++++++++++++----------- 2 files changed, 232 insertions(+), 71 deletions(-) diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index 3bec6bb3fb7..f7bf684b428 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -37,6 +37,7 @@ #include "exec/memory.h" #include "cpu.h" #include "qom/object.h" +#include "qemu/units.h" =20 #define TYPE_FSL_IMX6UL "fsl-imx6ul" OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL) @@ -57,6 +58,9 @@ enum FslIMX6ULConfiguration { FSL_IMX6UL_NUM_ADCS =3D 2, FSL_IMX6UL_NUM_USB_PHYS =3D 2, FSL_IMX6UL_NUM_USBS =3D 2, + FSL_IMX6UL_NUM_SAIS =3D 3, + FSL_IMX6UL_NUM_CANS =3D 2, + FSL_IMX6UL_NUM_PWMS =3D 4, }; =20 struct FslIMX6ULState { @@ -92,119 +96,227 @@ struct FslIMX6ULState { =20 enum FslIMX6ULMemoryMap { FSL_IMX6UL_MMDC_ADDR =3D 0x80000000, - FSL_IMX6UL_MMDC_SIZE =3D 2 * 1024 * 1024 * 1024UL, + FSL_IMX6UL_MMDC_SIZE =3D (2 * GiB), =20 FSL_IMX6UL_QSPI1_MEM_ADDR =3D 0x60000000, - FSL_IMX6UL_EIM_ALIAS_ADDR =3D 0x58000000, - FSL_IMX6UL_EIM_CS_ADDR =3D 0x50000000, - FSL_IMX6UL_AES_ENCRYPT_ADDR =3D 0x10000000, - FSL_IMX6UL_QSPI1_RX_ADDR =3D 0x0C000000, + FSL_IMX6UL_QSPI1_MEM_SIZE =3D (256 * MiB), =20 - /* AIPS-2 */ + FSL_IMX6UL_EIM_ALIAS_ADDR =3D 0x58000000, + FSL_IMX6UL_EIM_ALIAS_SIZE =3D (128 * MiB), + + FSL_IMX6UL_EIM_CS_ADDR =3D 0x50000000, + FSL_IMX6UL_EIM_CS_SIZE =3D (128 * MiB), + + FSL_IMX6UL_AES_ENCRYPT_ADDR =3D 0x10000000, + FSL_IMX6UL_AES_ENCRYPT_SIZE =3D (1 * MiB), + + FSL_IMX6UL_QSPI1_RX_ADDR =3D 0x0C000000, + FSL_IMX6UL_QSPI1_RX_SIZE =3D (32 * MiB), + + /* AIPS-2 Begin */ FSL_IMX6UL_UART6_ADDR =3D 0x021FC000, + FSL_IMX6UL_I2C4_ADDR =3D 0x021F8000, + FSL_IMX6UL_UART5_ADDR =3D 0x021F4000, FSL_IMX6UL_UART4_ADDR =3D 0x021F0000, FSL_IMX6UL_UART3_ADDR =3D 0x021EC000, FSL_IMX6UL_UART2_ADDR =3D 0x021E8000, + FSL_IMX6UL_WDOG3_ADDR =3D 0x021E4000, + FSL_IMX6UL_QSPI_ADDR =3D 0x021E0000, + FSL_IMX6UL_QSPI_SIZE =3D 0x500, + FSL_IMX6UL_SYS_CNT_CTRL_ADDR =3D 0x021DC000, + FSL_IMX6UL_SYS_CNT_CTRL_SIZE =3D (16 * KiB), + FSL_IMX6UL_SYS_CNT_CMP_ADDR =3D 0x021D8000, + FSL_IMX6UL_SYS_CNT_CMP_SIZE =3D (16 * KiB), + FSL_IMX6UL_SYS_CNT_RD_ADDR =3D 0x021D4000, + FSL_IMX6UL_SYS_CNT_RD_SIZE =3D (16 * KiB), + FSL_IMX6UL_TZASC_ADDR =3D 0x021D0000, + FSL_IMX6UL_TZASC_SIZE =3D (16 * KiB), + FSL_IMX6UL_PXP_ADDR =3D 0x021CC000, + FSL_IMX6UL_PXP_SIZE =3D (16 * KiB), + FSL_IMX6UL_LCDIF_ADDR =3D 0x021C8000, + FSL_IMX6UL_LCDIF_SIZE =3D 0x100, + FSL_IMX6UL_CSI_ADDR =3D 0x021C4000, + FSL_IMX6UL_CSI_SIZE =3D 0x100, + FSL_IMX6UL_CSU_ADDR =3D 0x021C0000, + FSL_IMX6UL_CSU_SIZE =3D (16 * KiB), + FSL_IMX6UL_OCOTP_CTRL_ADDR =3D 0x021BC000, + FSL_IMX6UL_OCOTP_CTRL_SIZE =3D (4 * KiB), + FSL_IMX6UL_EIM_ADDR =3D 0x021B8000, + FSL_IMX6UL_EIM_SIZE =3D 0x100, + FSL_IMX6UL_SIM2_ADDR =3D 0x021B4000, + FSL_IMX6UL_MMDC_CFG_ADDR =3D 0x021B0000, + FSL_IMX6UL_MMDC_CFG_SIZE =3D (4 * KiB), + FSL_IMX6UL_ROMCP_ADDR =3D 0x021AC000, + FSL_IMX6UL_ROMCP_SIZE =3D 0x300, + FSL_IMX6UL_I2C3_ADDR =3D 0x021A8000, FSL_IMX6UL_I2C2_ADDR =3D 0x021A4000, FSL_IMX6UL_I2C1_ADDR =3D 0x021A0000, + FSL_IMX6UL_ADC2_ADDR =3D 0x0219C000, FSL_IMX6UL_ADC1_ADDR =3D 0x02198000, + FSL_IMX6UL_ADCn_SIZE =3D 0x100, + FSL_IMX6UL_USDHC2_ADDR =3D 0x02194000, FSL_IMX6UL_USDHC1_ADDR =3D 0x02190000, - FSL_IMX6UL_SIM1_ADDR =3D 0x0218C000, - FSL_IMX6UL_ENET1_ADDR =3D 0x02188000, - FSL_IMX6UL_USBO2_USBMISC_ADDR =3D 0x02184800, - FSL_IMX6UL_USBO2_USB_ADDR =3D 0x02184000, - FSL_IMX6UL_USBO2_PL301_ADDR =3D 0x02180000, - FSL_IMX6UL_AIPS2_CFG_ADDR =3D 0x0217C000, - FSL_IMX6UL_CAAM_ADDR =3D 0x02140000, - FSL_IMX6UL_A7MPCORE_DAP_ADDR =3D 0x02100000, =20 - /* AIPS-1 */ + FSL_IMX6UL_SIM1_ADDR =3D 0x0218C000, + FSL_IMX6UL_SIMn_SIZE =3D (16 * KiB), + + FSL_IMX6UL_ENET1_ADDR =3D 0x02188000, + + FSL_IMX6UL_USBO2_USBMISC_ADDR =3D 0x02184800, + FSL_IMX6UL_USBO2_USB1_ADDR =3D 0x02184000, + FSL_IMX6UL_USBO2_USB2_ADDR =3D 0x02184200, + + FSL_IMX6UL_USBO2_PL301_ADDR =3D 0x02180000, + FSL_IMX6UL_USBO2_PL301_SIZE =3D (16 * KiB), + + FSL_IMX6UL_AIPS2_CFG_ADDR =3D 0x0217C000, + FSL_IMX6UL_AIPS2_CFG_SIZE =3D 0x100, + + FSL_IMX6UL_CAAM_ADDR =3D 0x02140000, + FSL_IMX6UL_CAAM_SIZE =3D (16 * KiB), + + FSL_IMX6UL_A7MPCORE_DAP_ADDR =3D 0x02100000, + FSL_IMX6UL_A7MPCORE_DAP_SIZE =3D (4 * KiB), + /* AIPS-2 End */ + + /* AIPS-1 Begin */ FSL_IMX6UL_PWM8_ADDR =3D 0x020FC000, FSL_IMX6UL_PWM7_ADDR =3D 0x020F8000, FSL_IMX6UL_PWM6_ADDR =3D 0x020F4000, FSL_IMX6UL_PWM5_ADDR =3D 0x020F0000, + FSL_IMX6UL_SDMA_ADDR =3D 0x020EC000, + FSL_IMX6UL_SDMA_SIZE =3D 0x300, + FSL_IMX6UL_GPT2_ADDR =3D 0x020E8000, + FSL_IMX6UL_IOMUXC_GPR_ADDR =3D 0x020E4000, + FSL_IMX6UL_IOMUXC_GPR_SIZE =3D 0x40, + FSL_IMX6UL_IOMUXC_ADDR =3D 0x020E0000, + FSL_IMX6UL_IOMUXC_SIZE =3D 0x700, + FSL_IMX6UL_GPC_ADDR =3D 0x020DC000, + FSL_IMX6UL_SRC_ADDR =3D 0x020D8000, + FSL_IMX6UL_EPIT2_ADDR =3D 0x020D4000, FSL_IMX6UL_EPIT1_ADDR =3D 0x020D0000, + FSL_IMX6UL_SNVS_HP_ADDR =3D 0x020CC000, + FSL_IMX6UL_USBPHY2_ADDR =3D 0x020CA000, - FSL_IMX6UL_USBPHY2_SIZE =3D (4 * 1024), FSL_IMX6UL_USBPHY1_ADDR =3D 0x020C9000, - FSL_IMX6UL_USBPHY1_SIZE =3D (4 * 1024), + FSL_IMX6UL_ANALOG_ADDR =3D 0x020C8000, + FSL_IMX6UL_ANALOG_SIZE =3D 0x300, + FSL_IMX6UL_CCM_ADDR =3D 0x020C4000, + FSL_IMX6UL_WDOG2_ADDR =3D 0x020C0000, FSL_IMX6UL_WDOG1_ADDR =3D 0x020BC000, + FSL_IMX6UL_KPP_ADDR =3D 0x020B8000, + FSL_IMX6UL_KPP_SIZE =3D 0x10, + FSL_IMX6UL_ENET2_ADDR =3D 0x020B4000, + FSL_IMX6UL_SNVS_LP_ADDR =3D 0x020B0000, + FSL_IMX6UL_SNVS_LP_SIZE =3D (16 * KiB), + FSL_IMX6UL_GPIO5_ADDR =3D 0x020AC000, FSL_IMX6UL_GPIO4_ADDR =3D 0x020A8000, FSL_IMX6UL_GPIO3_ADDR =3D 0x020A4000, FSL_IMX6UL_GPIO2_ADDR =3D 0x020A0000, FSL_IMX6UL_GPIO1_ADDR =3D 0x0209C000, + FSL_IMX6UL_GPT1_ADDR =3D 0x02098000, + FSL_IMX6UL_CAN2_ADDR =3D 0x02094000, FSL_IMX6UL_CAN1_ADDR =3D 0x02090000, + FSL_IMX6UL_CANn_SIZE =3D (4 * KiB), + FSL_IMX6UL_PWM4_ADDR =3D 0x0208C000, FSL_IMX6UL_PWM3_ADDR =3D 0x02088000, FSL_IMX6UL_PWM2_ADDR =3D 0x02084000, FSL_IMX6UL_PWM1_ADDR =3D 0x02080000, + FSL_IMX6UL_PWMn_SIZE =3D 0x20, + FSL_IMX6UL_AIPS1_CFG_ADDR =3D 0x0207C000, + FSL_IMX6UL_AIPS1_CFG_SIZE =3D (16 * KiB), + FSL_IMX6UL_BEE_ADDR =3D 0x02044000, + FSL_IMX6UL_BEE_SIZE =3D (16 * KiB), + FSL_IMX6UL_TOUCH_CTRL_ADDR =3D 0x02040000, + FSL_IMX6UL_TOUCH_CTRL_SIZE =3D 0x100, + FSL_IMX6UL_SPBA_ADDR =3D 0x0203C000, + FSL_IMX6UL_SPBA_SIZE =3D 0x100, + FSL_IMX6UL_ASRC_ADDR =3D 0x02034000, + FSL_IMX6UL_ASRC_SIZE =3D 0x100, + FSL_IMX6UL_SAI3_ADDR =3D 0x02030000, FSL_IMX6UL_SAI2_ADDR =3D 0x0202C000, FSL_IMX6UL_SAI1_ADDR =3D 0x02028000, + FSL_IMX6UL_SAIn_SIZE =3D 0x200, + FSL_IMX6UL_UART8_ADDR =3D 0x02024000, FSL_IMX6UL_UART1_ADDR =3D 0x02020000, FSL_IMX6UL_UART7_ADDR =3D 0x02018000, + FSL_IMX6UL_ECSPI4_ADDR =3D 0x02014000, FSL_IMX6UL_ECSPI3_ADDR =3D 0x02010000, FSL_IMX6UL_ECSPI2_ADDR =3D 0x0200C000, FSL_IMX6UL_ECSPI1_ADDR =3D 0x02008000, + FSL_IMX6UL_SPDIF_ADDR =3D 0x02004000, + FSL_IMX6UL_SPDIF_SIZE =3D 0x100, + /* AIPS-1 End */ + + FSL_IMX6UL_BCH_ADDR =3D 0x01808000, + FSL_IMX6UL_BCH_SIZE =3D 0x200, + + FSL_IMX6UL_GPMI_ADDR =3D 0x01806000, + FSL_IMX6UL_GPMI_SIZE =3D 0x200, =20 FSL_IMX6UL_APBH_DMA_ADDR =3D 0x01804000, - FSL_IMX6UL_APBH_DMA_SIZE =3D (32 * 1024), + FSL_IMX6UL_APBH_DMA_SIZE =3D (4 * KiB), =20 FSL_IMX6UL_A7MPCORE_ADDR =3D 0x00A00000, =20 FSL_IMX6UL_OCRAM_ALIAS_ADDR =3D 0x00920000, - FSL_IMX6UL_OCRAM_ALIAS_SIZE =3D 0x00060000, + FSL_IMX6UL_OCRAM_ALIAS_SIZE =3D (384 * KiB), + FSL_IMX6UL_OCRAM_MEM_ADDR =3D 0x00900000, - FSL_IMX6UL_OCRAM_MEM_SIZE =3D 0x00020000, + FSL_IMX6UL_OCRAM_MEM_SIZE =3D (128 * KiB), + FSL_IMX6UL_CAAM_MEM_ADDR =3D 0x00100000, - FSL_IMX6UL_CAAM_MEM_SIZE =3D 0x00008000, + FSL_IMX6UL_CAAM_MEM_SIZE =3D (32 * KiB), + FSL_IMX6UL_ROM_ADDR =3D 0x00000000, - FSL_IMX6UL_ROM_SIZE =3D 0x00018000, + FSL_IMX6UL_ROM_SIZE =3D (96 * KiB), }; =20 enum FslIMX6ULIRQs { diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index 0fdd2782ba5..06a32aff647 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -64,7 +64,7 @@ static void fsl_imx6ul_init(Object *obj) object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); =20 /* - * GPIOs 1 to 5 + * GPIOs */ for (i =3D 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { snprintf(name, NAME_SIZE, "gpio%d", i); @@ -72,7 +72,7 @@ static void fsl_imx6ul_init(Object *obj) } =20 /* - * GPT 1, 2 + * GPTs */ for (i =3D 0; i < FSL_IMX6UL_NUM_GPTS; i++) { snprintf(name, NAME_SIZE, "gpt%d", i); @@ -80,7 +80,7 @@ static void fsl_imx6ul_init(Object *obj) } =20 /* - * EPIT 1, 2 + * EPITs */ for (i =3D 0; i < FSL_IMX6UL_NUM_EPITS; i++) { snprintf(name, NAME_SIZE, "epit%d", i + 1); @@ -88,7 +88,7 @@ static void fsl_imx6ul_init(Object *obj) } =20 /* - * eCSPI + * eCSPIs */ for (i =3D 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { snprintf(name, NAME_SIZE, "spi%d", i + 1); @@ -96,7 +96,7 @@ static void fsl_imx6ul_init(Object *obj) } =20 /* - * I2C + * I2Cs */ for (i =3D 0; i < FSL_IMX6UL_NUM_I2CS; i++) { snprintf(name, NAME_SIZE, "i2c%d", i + 1); @@ -104,7 +104,7 @@ static void fsl_imx6ul_init(Object *obj) } =20 /* - * UART + * UARTs */ for (i =3D 0; i < FSL_IMX6UL_NUM_UARTS; i++) { snprintf(name, NAME_SIZE, "uart%d", i); @@ -112,25 +112,31 @@ static void fsl_imx6ul_init(Object *obj) } =20 /* - * Ethernet + * Ethernets */ for (i =3D 0; i < FSL_IMX6UL_NUM_ETHS; i++) { snprintf(name, NAME_SIZE, "eth%d", i); object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET); } =20 - /* USB */ + /* + * USB PHYs + */ for (i =3D 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { snprintf(name, NAME_SIZE, "usbphy%d", i); object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY); } + + /* + * USBs + */ for (i =3D 0; i < FSL_IMX6UL_NUM_USBS; i++) { snprintf(name, NAME_SIZE, "usb%d", i); object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); } =20 /* - * SDHCI + * SDHCIs */ for (i =3D 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { snprintf(name, NAME_SIZE, "usdhc%d", i); @@ -138,7 +144,7 @@ static void fsl_imx6ul_init(Object *obj) } =20 /* - * Watchdog + * Watchdogs */ for (i =3D 0; i < FSL_IMX6UL_NUM_WDTS; i++) { snprintf(name, NAME_SIZE, "wdt%d", i); @@ -184,10 +190,10 @@ static void fsl_imx6ul_realize(DeviceState *dev, Erro= r **errp) * A7MPCORE DAP */ create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_AD= DR, - 0x100000); + FSL_IMX6UL_A7MPCORE_DAP_SIZE); =20 /* - * GPT 1, 2 + * GPTs */ for (i =3D 0; i < FSL_IMX6UL_NUM_GPTS; i++) { static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] =3D { @@ -212,7 +218,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error = **errp) } =20 /* - * EPIT 1, 2 + * EPITs */ for (i =3D 0; i < FSL_IMX6UL_NUM_EPITS; i++) { static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = =3D { @@ -237,7 +243,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error = **errp) } =20 /* - * GPIO + * GPIOs */ for (i =3D 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = =3D { @@ -279,17 +285,12 @@ static void fsl_imx6ul_realize(DeviceState *dev, Erro= r **errp) } =20 /* - * IOMUXC and IOMUXC_GPR + * IOMUXC */ - for (i =3D 0; i < 1; i++) { - static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS= ] =3D { - FSL_IMX6UL_IOMUXC_ADDR, - FSL_IMX6UL_IOMUXC_GPR_ADDR, - }; - - snprintf(name, NAME_SIZE, "iomuxc%d", i); - create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x40= 00); - } + create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR, + FSL_IMX6UL_IOMUXC_SIZE); + create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR, + FSL_IMX6UL_IOMUXC_GPR_SIZE); =20 /* * CCM @@ -309,7 +310,9 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error = **errp) sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR); =20 - /* Initialize all ECSPI */ + /* + * ECSPIs + */ for (i =3D 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = =3D { FSL_IMX6UL_ECSPI1_ADDR, @@ -337,7 +340,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error = **errp) } =20 /* - * I2C + * I2Cs */ for (i =3D 0; i < FSL_IMX6UL_NUM_I2CS; i++) { static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] =3D { @@ -363,7 +366,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error = **errp) } =20 /* - * UART + * UARTs */ for (i =3D 0; i < FSL_IMX6UL_NUM_UARTS; i++) { static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = =3D { @@ -401,7 +404,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error = **errp) } =20 /* - * Ethernet + * Ethernets * * We must use two loops since phy_connected affects the other interfa= ce * and we have to set all properties before calling sysbus_realize(). @@ -454,28 +457,45 @@ static void fsl_imx6ul_realize(DeviceState *dev, Erro= r **errp) FSL_IMX6UL_ENETn_TIMER_IRQ[i])= ); } =20 - /* USB */ + /* + * USB PHYs + */ for (i =3D 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { + static const hwaddr + FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] =3D= { + FSL_IMX6UL_USBPHY1_ADDR, + FSL_IMX6UL_USBPHY2_ADDR, + }; + sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0, - FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000); + FSL_IMX6UL_USB_PHYn_ADDR[i]); } =20 + /* + * USBs + */ for (i =3D 0; i < FSL_IMX6UL_NUM_USBS; i++) { + static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS= ] =3D { + FSL_IMX6UL_USBO2_USB1_ADDR, + FSL_IMX6UL_USBO2_USB2_ADDR, + }; + static const int FSL_IMX6UL_USBn_IRQ[] =3D { FSL_IMX6UL_USB1_IRQ, FSL_IMX6UL_USB2_IRQ, }; + sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, - FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200); + FSL_IMX6UL_USB02_USBn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX6UL_USBn_IRQ[i])); } =20 /* - * USDHC + * USDHCs */ for (i =3D 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = =3D { @@ -507,7 +527,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error = **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR); =20 /* - * Watchdog + * Watchdogs */ for (i =3D 0; i < FSL_IMX6UL_NUM_WDTS; i++) { static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] =3D= { @@ -515,6 +535,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error = **errp) FSL_IMX6UL_WDOG2_ADDR, FSL_IMX6UL_WDOG3_ADDR, }; + static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] =3D { FSL_IMX6UL_WDOG1_IRQ, FSL_IMX6UL_WDOG2_IRQ, @@ -535,33 +556,59 @@ static void fsl_imx6ul_realize(DeviceState *dev, Erro= r **errp) /* * SDMA */ - create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000); + create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, + FSL_IMX6UL_SDMA_SIZE); =20 /* - * SAI (Audio SSI (Synchronous Serial Interface)) + * SAIs (Audio SSI (Synchronous Serial Interface)) */ - create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000); - create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000); - create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000); + for (i =3D 0; i < FSL_IMX6UL_NUM_SAIS; i++) { + static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] =3D { + FSL_IMX6UL_SAI1_ADDR, + FSL_IMX6UL_SAI2_ADDR, + FSL_IMX6UL_SAI3_ADDR, + }; + + snprintf(name, NAME_SIZE, "sai%d", i); + create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i], + FSL_IMX6UL_SAIn_SIZE); + } =20 /* - * PWM + * PWMs */ - create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000); - create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000); - create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000); - create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000); + for (i =3D 0; i < FSL_IMX6UL_NUM_PWMS; i++) { + static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] =3D { + FSL_IMX6UL_PWM1_ADDR, + FSL_IMX6UL_PWM2_ADDR, + FSL_IMX6UL_PWM3_ADDR, + FSL_IMX6UL_PWM4_ADDR, + }; + + snprintf(name, NAME_SIZE, "pwm%d", i); + create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i], + FSL_IMX6UL_PWMn_SIZE); + } =20 /* * Audio ASRC (asynchronous sample rate converter) */ - create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000); + create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, + FSL_IMX6UL_ASRC_SIZE); =20 /* - * CAN + * CANs */ - create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000); - create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000); + for (i =3D 0; i < FSL_IMX6UL_NUM_CANS; i++) { + static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] =3D { + FSL_IMX6UL_CAN1_ADDR, + FSL_IMX6UL_CAN2_ADDR, + }; + + snprintf(name, NAME_SIZE, "can%d", i); + create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i], + FSL_IMX6UL_CANn_SIZE); + } =20 /* * APHB_DMA @@ -579,13 +626,15 @@ static void fsl_imx6ul_realize(DeviceState *dev, Erro= r **errp) }; =20 snprintf(name, NAME_SIZE, "adc%d", i); - create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000); + create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], + FSL_IMX6UL_ADCn_SIZE); } =20 /* * LCD */ - create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000); + create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, + FSL_IMX6UL_LCDIF_SIZE); =20 /* * ROM memory --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478791; cv=none; d=zohomail.com; s=zohoarc; b=NxKq/5Y37m28XYpHgYFyuUVdOd64oFl4kEPMhpKkLBIZ7ZSwrYcP+DvglMfROg4zxaba25BiGheRhvVQ4N2F8lBYC4E/qXyEDX43HsKHZO+VTZAtrCR245KqwGjs30HuiUcikFDKJshe9JAHsIlb4Y7Sl7bj/ZSXlVVZKpP05k4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478791; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=d8C43XFZ9tO8SprZx5Cpb/h7ovOf0gqzc6LRcUwwY6I=; b=ah9tOVvEL6BW1rc3ofIo2yXgYq0nUKkNLPlt6HdU6TwufafwhnSdSwTXUFTQwK/L3WRAqXQFXwKt05CqxJJwvbzhLxGmYgaO+Xvns7Bef3OWcXjwkrpqKqiMo6opDDCYOIUVu519LzoISE/j7w4lprhQVFfr8bA5p/7djYBGk/8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693478791905493.47806345686297; Thu, 31 Aug 2023 03:46:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbfBF-0003jV-Bp; Thu, 31 Aug 2023 06:45:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbfB7-0003Za-Gv for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:35 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbfB1-00043j-ES for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:31 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-4020b88bd03so6205855e9.3 for ; Thu, 31 Aug 2023 03:45:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478726; x=1694083526; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=d8C43XFZ9tO8SprZx5Cpb/h7ovOf0gqzc6LRcUwwY6I=; b=Arkjihixh0w9iKEoCqZ2swtgpDMsz6qi3EQMp5NlbVqxHNL+8bQQtF3mnE3jk6ktCd gnKBoCtJg2T3ua8Or4LDR+l4ZToG1zI9ZbQZ48JaPrJ4jm6r8uTzTj4CkoaGCFb4ZG2n QMcAa7Nw3OrlXZk4lsrM1i8LZUzYqVyZvO9JwtLKt5m2VkmWRiiJI/c3u7TG/PNGNYLf 4q8i/47iHP3GfVZxDbLBAIGcQ83uwPKYi488O7eiFBKIXD9WWHZlScBNN61aFfyj6XjF LJNh/EnTb7yL1KS1K9GPzCmvlr6Ci+rPRrNDkoUrvpr8AVs/gS0UKYB22KcGJbcELrEE cmEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478726; x=1694083526; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d8C43XFZ9tO8SprZx5Cpb/h7ovOf0gqzc6LRcUwwY6I=; b=PGjGhq/L9ipeAx9RkQuji2c/9EXU53CG89Ar38CJ8pcZO/UT4QftacMiXaJMRCpPHv 3Yz2UEVEBxoW6kB3y+kRO8W/UiZ8znnybY2GdpKvs2RP4t4pgWgwASXPiosWk68D/zxi 0P6KC922wJn96poO/qnu65NtItJkxwNRkyAluiRiUcAtAoKvTCJK77njavI6t0xwPwMA e1ScPqbSLEZc881gfaQS50hTlRnDi2w+n9PNdKz/QR3i9Z+K4kCUk6v3v9b2g7wAoYN7 QL/PdU11bhvZ1pgDFsUuonYJJdO4jWptLZ0TXw0tqB0y71T1Sc2PinyDpxoQJg2lsRLp NqqQ== X-Gm-Message-State: AOJu0YxvP0ZgcUdjZxFdVORVed/XU9AWB3d0zCOJT/ocwGYoj3zrbqZG j/lNyrII1yxxMpoy4/VTPFXniNLLRs77ciia1yQ= X-Google-Smtp-Source: AGHT+IEuGamRBxawi/ngBxaikZ01XxS/ANA38f304IpvEG/StXzFy7K9ORGJPHopf9T7RrlCDrZpGA== X-Received: by 2002:a7b:cd0a:0:b0:401:b2c7:3497 with SMTP id f10-20020a7bcd0a000000b00401b2c73497mr3625000wmj.11.1693478726070; Thu, 31 Aug 2023 03:45:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/24] Add i.MX6UL missing devices. Date: Thu, 31 Aug 2023 11:45:08 +0100 Message-Id: <20230831104519.3520658-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478793622100015 From: Jean-Christophe Dubois * Add TZASC as unimplemented device. - Allow bare metal application to access this (unimplemented) device * Add CSU as unimplemented device. - Allow bare metal application to access this (unimplemented) device * Add 4 missing PWM devices Signed-off-by: Jean-Christophe Dubois Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tri= budubois.net Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx6ul.h | 2 +- hw/arm/fsl-imx6ul.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index f7bf684b428..63012628ff0 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -60,7 +60,7 @@ enum FslIMX6ULConfiguration { FSL_IMX6UL_NUM_USBS =3D 2, FSL_IMX6UL_NUM_SAIS =3D 3, FSL_IMX6UL_NUM_CANS =3D 2, - FSL_IMX6UL_NUM_PWMS =3D 4, + FSL_IMX6UL_NUM_PWMS =3D 8, }; =20 struct FslIMX6ULState { diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index 06a32aff647..e37b69a5e16 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -583,6 +583,10 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error= **errp) FSL_IMX6UL_PWM2_ADDR, FSL_IMX6UL_PWM3_ADDR, FSL_IMX6UL_PWM4_ADDR, + FSL_IMX6UL_PWM5_ADDR, + FSL_IMX6UL_PWM6_ADDR, + FSL_IMX6UL_PWM7_ADDR, + FSL_IMX6UL_PWM8_ADDR, }; =20 snprintf(name, NAME_SIZE, "pwm%d", i); @@ -636,6 +640,18 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error= **errp) create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, FSL_IMX6UL_LCDIF_SIZE); =20 + /* + * CSU + */ + create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR, + FSL_IMX6UL_CSU_SIZE); + + /* + * TZASC + */ + create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR, + FSL_IMX6UL_TZASC_SIZE); + /* * ROM memory */ --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478726; x=1694083526; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=mfV/nwKI+irh9L62+dwToCu1Oo8P6yPQqKVntEFfbpw=; b=TRdkKHuhpNO63Yt2W90OmncD/LzbBjIeSyslhU6UXHV8/CR95FeMtIO655T5wa4Ce+ opP1Sp1IjWQV73TlVYSsw4gzR15ehlBYuYHsl2nElcuEgoG21nIjLL850Lc4LwJnE7JD 6MJRvhaSOMCoiiMF3LA9OyiR4NZyoIn/BoT6iMq64aF6BcK2bz4gPMtKzpA8mqzFFB/g koqYVzN9rlgwUd5k8Wr1jdky7nAdAv7zUNvVt50rnNBEp0LjLTzkbft98fYDGJyQ20zX SvXlZeqlYxPyNehv5GSUspZE9wX+ZFAPSOCpp2EeR7zUwaVyyPVXd04t8MTzkh1bBA91 ViLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478726; x=1694083526; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mfV/nwKI+irh9L62+dwToCu1Oo8P6yPQqKVntEFfbpw=; b=D+ujtHSoo9Fl/9TkShpiJIgp2NPws9HXIx+g3DHcJiKDl7kdsvLGz3nf5y76PTHzWB E+d/Prm60UTvjpZoeoziHhk6fF2YbLBRq7qrP7hseXvGdAwzN0GpRAUASizR/KyZ4dO8 nLYvgH3x2Jqy62s8GMDpJSzFnzXM6sx0duyOQdEHQiq/cZsR7pxZ4s+aWSzG/JDZHsyr WSMjazjCc0nNQqhHgsWuOzEurwPg/Zv9u61y3gTw/qr4bmGksl6dvmRe77D72dQHP7Bv VOuPl0xrPynMeaARpACiCMulZZEhPOrq0Sip0Y8FFlG6Lbp0BFvJ5omOFs/uo0CH+pBL YtXA== X-Gm-Message-State: AOJu0YwUMj6u015dpPqOPQpjt8AZX7qO91p1efIStfKrULNvdu4QXmCs Fj4Yv+2joRaUTkZ/9zJxQw2KDzt7RQK+2hqfnYU= X-Google-Smtp-Source: AGHT+IHelscb0i4XhlS3G2dZuThcPRb9bqzVNZBsblO1/zj6GtXcJlQU/X4rv4pASX8ViL7UdOl4kg== X-Received: by 2002:a05:600c:b57:b0:401:aa8f:7570 with SMTP id k23-20020a05600c0b5700b00401aa8f7570mr3633409wmr.1.1693478726479; Thu, 31 Aug 2023 03:45:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/24] Refactor i.MX7 processor code Date: Thu, 31 Aug 2023 11:45:09 +0100 Message-Id: <20230831104519.3520658-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478810039100001 Content-Type: text/plain; charset="utf-8" From: Jean-Christophe Dubois * Add Addr and size definition for all i.MX7 devices in i.MX7 header file. * Use those newly defined named constants whenever possible. * Standardize the way we init a familly of unimplemented devices - SAI - PWM - CAN * Add/rework few comments Signed-off-by: Jean-Christophe Dubois Message-id: 59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tri= budubois.net Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx7.h | 330 ++++++++++++++++++++++++++++---------- hw/arm/fsl-imx7.c | 130 ++++++++++----- 2 files changed, 335 insertions(+), 125 deletions(-) diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index fcce6421c8c..06b2c5e4acf 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -25,7 +25,6 @@ #include "hw/misc/imx7_ccm.h" #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx7_gpr.h" -#include "hw/misc/imx6_src.h" #include "hw/watchdog/wdt_imx2.h" #include "hw/gpio/imx_gpio.h" #include "hw/char/imx_serial.h" @@ -39,6 +38,7 @@ #include "hw/usb/chipidea.h" #include "cpu.h" #include "qom/object.h" +#include "qemu/units.h" =20 #define TYPE_FSL_IMX7 "fsl-imx7" OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7) @@ -57,6 +57,9 @@ enum FslIMX7Configuration { FSL_IMX7_NUM_ECSPIS =3D 4, FSL_IMX7_NUM_USBS =3D 3, FSL_IMX7_NUM_ADCS =3D 2, + FSL_IMX7_NUM_SAIS =3D 3, + FSL_IMX7_NUM_CANS =3D 2, + FSL_IMX7_NUM_PWMS =3D 4, }; =20 struct FslIMX7State { @@ -87,80 +90,106 @@ struct FslIMX7State { =20 enum FslIMX7MemoryMap { FSL_IMX7_MMDC_ADDR =3D 0x80000000, - FSL_IMX7_MMDC_SIZE =3D 2 * 1024 * 1024 * 1024UL, + FSL_IMX7_MMDC_SIZE =3D (2 * GiB), =20 - FSL_IMX7_GPIO1_ADDR =3D 0x30200000, - FSL_IMX7_GPIO2_ADDR =3D 0x30210000, - FSL_IMX7_GPIO3_ADDR =3D 0x30220000, - FSL_IMX7_GPIO4_ADDR =3D 0x30230000, - FSL_IMX7_GPIO5_ADDR =3D 0x30240000, - FSL_IMX7_GPIO6_ADDR =3D 0x30250000, - FSL_IMX7_GPIO7_ADDR =3D 0x30260000, + FSL_IMX7_QSPI1_MEM_ADDR =3D 0x60000000, + FSL_IMX7_QSPI1_MEM_SIZE =3D (256 * MiB), =20 - FSL_IMX7_IOMUXC_LPSR_GPR_ADDR =3D 0x30270000, + FSL_IMX7_PCIE1_MEM_ADDR =3D 0x40000000, + FSL_IMX7_PCIE1_MEM_SIZE =3D (256 * MiB), =20 - FSL_IMX7_WDOG1_ADDR =3D 0x30280000, - FSL_IMX7_WDOG2_ADDR =3D 0x30290000, - FSL_IMX7_WDOG3_ADDR =3D 0x302A0000, - FSL_IMX7_WDOG4_ADDR =3D 0x302B0000, + FSL_IMX7_QSPI1_RX_BUF_ADDR =3D 0x34000000, + FSL_IMX7_QSPI1_RX_BUF_SIZE =3D (32 * MiB), =20 - FSL_IMX7_IOMUXC_LPSR_ADDR =3D 0x302C0000, + /* PCIe Peripherals */ + FSL_IMX7_PCIE_REG_ADDR =3D 0x33800000, =20 - FSL_IMX7_GPT1_ADDR =3D 0x302D0000, - FSL_IMX7_GPT2_ADDR =3D 0x302E0000, - FSL_IMX7_GPT3_ADDR =3D 0x302F0000, - FSL_IMX7_GPT4_ADDR =3D 0x30300000, + /* MMAP Peripherals */ + FSL_IMX7_DMA_APBH_ADDR =3D 0x33000000, + FSL_IMX7_DMA_APBH_SIZE =3D 0x8000, =20 - FSL_IMX7_IOMUXC_ADDR =3D 0x30330000, - FSL_IMX7_IOMUXC_GPR_ADDR =3D 0x30340000, - FSL_IMX7_IOMUXCn_SIZE =3D 0x1000, + /* GPV configuration */ + FSL_IMX7_GPV6_ADDR =3D 0x32600000, + FSL_IMX7_GPV5_ADDR =3D 0x32500000, + FSL_IMX7_GPV4_ADDR =3D 0x32400000, + FSL_IMX7_GPV3_ADDR =3D 0x32300000, + FSL_IMX7_GPV2_ADDR =3D 0x32200000, + FSL_IMX7_GPV1_ADDR =3D 0x32100000, + FSL_IMX7_GPV0_ADDR =3D 0x32000000, + FSL_IMX7_GPVn_SIZE =3D (1 * MiB), =20 - FSL_IMX7_OCOTP_ADDR =3D 0x30350000, - FSL_IMX7_OCOTP_SIZE =3D 0x10000, + /* Arm Peripherals */ + FSL_IMX7_A7MPCORE_ADDR =3D 0x31000000, =20 - FSL_IMX7_ANALOG_ADDR =3D 0x30360000, - FSL_IMX7_SNVS_ADDR =3D 0x30370000, - FSL_IMX7_CCM_ADDR =3D 0x30380000, + /* AIPS-3 Begin */ =20 - FSL_IMX7_SRC_ADDR =3D 0x30390000, - FSL_IMX7_SRC_SIZE =3D 0x1000, + FSL_IMX7_ENET2_ADDR =3D 0x30BF0000, + FSL_IMX7_ENET1_ADDR =3D 0x30BE0000, =20 - FSL_IMX7_ADC1_ADDR =3D 0x30610000, - FSL_IMX7_ADC2_ADDR =3D 0x30620000, - FSL_IMX7_ADCn_SIZE =3D 0x1000, + FSL_IMX7_SDMA_ADDR =3D 0x30BD0000, + FSL_IMX7_SDMA_SIZE =3D (4 * KiB), =20 - FSL_IMX7_PWM1_ADDR =3D 0x30660000, - FSL_IMX7_PWM2_ADDR =3D 0x30670000, - FSL_IMX7_PWM3_ADDR =3D 0x30680000, - FSL_IMX7_PWM4_ADDR =3D 0x30690000, - FSL_IMX7_PWMn_SIZE =3D 0x10000, + FSL_IMX7_EIM_ADDR =3D 0x30BC0000, + FSL_IMX7_EIM_SIZE =3D (4 * KiB), =20 - FSL_IMX7_PCIE_PHY_ADDR =3D 0x306D0000, - FSL_IMX7_PCIE_PHY_SIZE =3D 0x10000, + FSL_IMX7_QSPI_ADDR =3D 0x30BB0000, + FSL_IMX7_QSPI_SIZE =3D 0x8000, =20 - FSL_IMX7_GPC_ADDR =3D 0x303A0000, + FSL_IMX7_SIM2_ADDR =3D 0x30BA0000, + FSL_IMX7_SIM1_ADDR =3D 0x30B90000, + FSL_IMX7_SIMn_SIZE =3D (4 * KiB), + + FSL_IMX7_USDHC3_ADDR =3D 0x30B60000, + FSL_IMX7_USDHC2_ADDR =3D 0x30B50000, + FSL_IMX7_USDHC1_ADDR =3D 0x30B40000, + + FSL_IMX7_USB3_ADDR =3D 0x30B30000, + FSL_IMX7_USBMISC3_ADDR =3D 0x30B30200, + FSL_IMX7_USB2_ADDR =3D 0x30B20000, + FSL_IMX7_USBMISC2_ADDR =3D 0x30B20200, + FSL_IMX7_USB1_ADDR =3D 0x30B10000, + FSL_IMX7_USBMISC1_ADDR =3D 0x30B10200, + FSL_IMX7_USBMISCn_SIZE =3D 0x200, + + FSL_IMX7_USB_PL301_ADDR =3D 0x30AD0000, + FSL_IMX7_USB_PL301_SIZE =3D (64 * KiB), + + FSL_IMX7_SEMAPHORE_HS_ADDR =3D 0x30AC0000, + FSL_IMX7_SEMAPHORE_HS_SIZE =3D (64 * KiB), + + FSL_IMX7_MUB_ADDR =3D 0x30AB0000, + FSL_IMX7_MUA_ADDR =3D 0x30AA0000, + FSL_IMX7_MUn_SIZE =3D (KiB), + + FSL_IMX7_UART7_ADDR =3D 0x30A90000, + FSL_IMX7_UART6_ADDR =3D 0x30A80000, + FSL_IMX7_UART5_ADDR =3D 0x30A70000, + FSL_IMX7_UART4_ADDR =3D 0x30A60000, + + FSL_IMX7_I2C4_ADDR =3D 0x30A50000, + FSL_IMX7_I2C3_ADDR =3D 0x30A40000, + FSL_IMX7_I2C2_ADDR =3D 0x30A30000, + FSL_IMX7_I2C1_ADDR =3D 0x30A20000, + + FSL_IMX7_CAN2_ADDR =3D 0x30A10000, + FSL_IMX7_CAN1_ADDR =3D 0x30A00000, + FSL_IMX7_CANn_SIZE =3D (4 * KiB), + + FSL_IMX7_AIPS3_CONF_ADDR =3D 0x309F0000, + FSL_IMX7_AIPS3_CONF_SIZE =3D (64 * KiB), =20 FSL_IMX7_CAAM_ADDR =3D 0x30900000, - FSL_IMX7_CAAM_SIZE =3D 0x40000, + FSL_IMX7_CAAM_SIZE =3D (256 * KiB), =20 - FSL_IMX7_CAN1_ADDR =3D 0x30A00000, - FSL_IMX7_CAN2_ADDR =3D 0x30A10000, - FSL_IMX7_CANn_SIZE =3D 0x10000, + FSL_IMX7_SPBA_ADDR =3D 0x308F0000, + FSL_IMX7_SPBA_SIZE =3D (4 * KiB), =20 - FSL_IMX7_I2C1_ADDR =3D 0x30A20000, - FSL_IMX7_I2C2_ADDR =3D 0x30A30000, - FSL_IMX7_I2C3_ADDR =3D 0x30A40000, - FSL_IMX7_I2C4_ADDR =3D 0x30A50000, + FSL_IMX7_SAI3_ADDR =3D 0x308C0000, + FSL_IMX7_SAI2_ADDR =3D 0x308B0000, + FSL_IMX7_SAI1_ADDR =3D 0x308A0000, + FSL_IMX7_SAIn_SIZE =3D (4 * KiB), =20 - FSL_IMX7_ECSPI1_ADDR =3D 0x30820000, - FSL_IMX7_ECSPI2_ADDR =3D 0x30830000, - FSL_IMX7_ECSPI3_ADDR =3D 0x30840000, - FSL_IMX7_ECSPI4_ADDR =3D 0x30630000, - - FSL_IMX7_LCDIF_ADDR =3D 0x30730000, - FSL_IMX7_LCDIF_SIZE =3D 0x1000, - - FSL_IMX7_UART1_ADDR =3D 0x30860000, + FSL_IMX7_UART3_ADDR =3D 0x30880000, /* * Some versions of the reference manual claim that UART2 is @ * 0x30870000, but experiments with HW + DT files in upstream @@ -168,45 +197,174 @@ enum FslIMX7MemoryMap { * actually located @ 0x30890000 */ FSL_IMX7_UART2_ADDR =3D 0x30890000, - FSL_IMX7_UART3_ADDR =3D 0x30880000, - FSL_IMX7_UART4_ADDR =3D 0x30A60000, - FSL_IMX7_UART5_ADDR =3D 0x30A70000, - FSL_IMX7_UART6_ADDR =3D 0x30A80000, - FSL_IMX7_UART7_ADDR =3D 0x30A90000, + FSL_IMX7_UART1_ADDR =3D 0x30860000, =20 - FSL_IMX7_SAI1_ADDR =3D 0x308A0000, - FSL_IMX7_SAI2_ADDR =3D 0x308B0000, - FSL_IMX7_SAI3_ADDR =3D 0x308C0000, - FSL_IMX7_SAIn_SIZE =3D 0x10000, + FSL_IMX7_ECSPI3_ADDR =3D 0x30840000, + FSL_IMX7_ECSPI2_ADDR =3D 0x30830000, + FSL_IMX7_ECSPI1_ADDR =3D 0x30820000, + FSL_IMX7_ECSPIn_SIZE =3D (4 * KiB), =20 - FSL_IMX7_ENET1_ADDR =3D 0x30BE0000, - FSL_IMX7_ENET2_ADDR =3D 0x30BF0000, + /* AIPS-3 End */ =20 - FSL_IMX7_USB1_ADDR =3D 0x30B10000, - FSL_IMX7_USBMISC1_ADDR =3D 0x30B10200, - FSL_IMX7_USB2_ADDR =3D 0x30B20000, - FSL_IMX7_USBMISC2_ADDR =3D 0x30B20200, - FSL_IMX7_USB3_ADDR =3D 0x30B30000, - FSL_IMX7_USBMISC3_ADDR =3D 0x30B30200, - FSL_IMX7_USBMISCn_SIZE =3D 0x200, + /* AIPS-2 Begin */ =20 - FSL_IMX7_USDHC1_ADDR =3D 0x30B40000, - FSL_IMX7_USDHC2_ADDR =3D 0x30B50000, - FSL_IMX7_USDHC3_ADDR =3D 0x30B60000, + FSL_IMX7_AXI_DEBUG_MON_ADDR =3D 0x307E0000, + FSL_IMX7_AXI_DEBUG_MON_SIZE =3D (64 * KiB), =20 - FSL_IMX7_SDMA_ADDR =3D 0x30BD0000, - FSL_IMX7_SDMA_SIZE =3D 0x1000, + FSL_IMX7_PERFMON2_ADDR =3D 0x307D0000, + FSL_IMX7_PERFMON1_ADDR =3D 0x307C0000, + FSL_IMX7_PERFMONn_SIZE =3D (64 * KiB), + + FSL_IMX7_DDRC_ADDR =3D 0x307A0000, + FSL_IMX7_DDRC_SIZE =3D (4 * KiB), + + FSL_IMX7_DDRC_PHY_ADDR =3D 0x30790000, + FSL_IMX7_DDRC_PHY_SIZE =3D (4 * KiB), + + FSL_IMX7_TZASC_ADDR =3D 0x30780000, + FSL_IMX7_TZASC_SIZE =3D (64 * KiB), + + FSL_IMX7_MIPI_DSI_ADDR =3D 0x30760000, + FSL_IMX7_MIPI_DSI_SIZE =3D (4 * KiB), + + FSL_IMX7_MIPI_CSI_ADDR =3D 0x30750000, + FSL_IMX7_MIPI_CSI_SIZE =3D 0x4000, + + FSL_IMX7_LCDIF_ADDR =3D 0x30730000, + FSL_IMX7_LCDIF_SIZE =3D 0x8000, + + FSL_IMX7_CSI_ADDR =3D 0x30710000, + FSL_IMX7_CSI_SIZE =3D (4 * KiB), + + FSL_IMX7_PXP_ADDR =3D 0x30700000, + FSL_IMX7_PXP_SIZE =3D 0x4000, + + FSL_IMX7_EPDC_ADDR =3D 0x306F0000, + FSL_IMX7_EPDC_SIZE =3D (4 * KiB), + + FSL_IMX7_PCIE_PHY_ADDR =3D 0x306D0000, + FSL_IMX7_PCIE_PHY_SIZE =3D (4 * KiB), + + FSL_IMX7_SYSCNT_CTRL_ADDR =3D 0x306C0000, + FSL_IMX7_SYSCNT_CMP_ADDR =3D 0x306B0000, + FSL_IMX7_SYSCNT_RD_ADDR =3D 0x306A0000, + + FSL_IMX7_PWM4_ADDR =3D 0x30690000, + FSL_IMX7_PWM3_ADDR =3D 0x30680000, + FSL_IMX7_PWM2_ADDR =3D 0x30670000, + FSL_IMX7_PWM1_ADDR =3D 0x30660000, + FSL_IMX7_PWMn_SIZE =3D (4 * KiB), + + FSL_IMX7_FlEXTIMER2_ADDR =3D 0x30650000, + FSL_IMX7_FlEXTIMER1_ADDR =3D 0x30640000, + FSL_IMX7_FLEXTIMERn_SIZE =3D (4 * KiB), + + FSL_IMX7_ECSPI4_ADDR =3D 0x30630000, + + FSL_IMX7_ADC2_ADDR =3D 0x30620000, + FSL_IMX7_ADC1_ADDR =3D 0x30610000, + FSL_IMX7_ADCn_SIZE =3D (4 * KiB), + + FSL_IMX7_AIPS2_CONF_ADDR =3D 0x305F0000, + FSL_IMX7_AIPS2_CONF_SIZE =3D (64 * KiB), + + /* AIPS-2 End */ + + /* AIPS-1 Begin */ + + FSL_IMX7_CSU_ADDR =3D 0x303E0000, + FSL_IMX7_CSU_SIZE =3D (64 * KiB), + + FSL_IMX7_RDC_ADDR =3D 0x303D0000, + FSL_IMX7_RDC_SIZE =3D (4 * KiB), + + FSL_IMX7_SEMAPHORE2_ADDR =3D 0x303C0000, + FSL_IMX7_SEMAPHORE1_ADDR =3D 0x303B0000, + FSL_IMX7_SEMAPHOREn_SIZE =3D (4 * KiB), + + FSL_IMX7_GPC_ADDR =3D 0x303A0000, + + FSL_IMX7_SRC_ADDR =3D 0x30390000, + FSL_IMX7_SRC_SIZE =3D (4 * KiB), + + FSL_IMX7_CCM_ADDR =3D 0x30380000, + + FSL_IMX7_SNVS_HP_ADDR =3D 0x30370000, + + FSL_IMX7_ANALOG_ADDR =3D 0x30360000, + + FSL_IMX7_OCOTP_ADDR =3D 0x30350000, + FSL_IMX7_OCOTP_SIZE =3D 0x10000, + + FSL_IMX7_IOMUXC_GPR_ADDR =3D 0x30340000, + FSL_IMX7_IOMUXC_GPR_SIZE =3D (4 * KiB), + + FSL_IMX7_IOMUXC_ADDR =3D 0x30330000, + FSL_IMX7_IOMUXC_SIZE =3D (4 * KiB), + + FSL_IMX7_KPP_ADDR =3D 0x30320000, + FSL_IMX7_KPP_SIZE =3D (4 * KiB), + + FSL_IMX7_ROMCP_ADDR =3D 0x30310000, + FSL_IMX7_ROMCP_SIZE =3D (4 * KiB), + + FSL_IMX7_GPT4_ADDR =3D 0x30300000, + FSL_IMX7_GPT3_ADDR =3D 0x302F0000, + FSL_IMX7_GPT2_ADDR =3D 0x302E0000, + FSL_IMX7_GPT1_ADDR =3D 0x302D0000, + + FSL_IMX7_IOMUXC_LPSR_ADDR =3D 0x302C0000, + FSL_IMX7_IOMUXC_LPSR_SIZE =3D (4 * KiB), + + FSL_IMX7_WDOG4_ADDR =3D 0x302B0000, + FSL_IMX7_WDOG3_ADDR =3D 0x302A0000, + FSL_IMX7_WDOG2_ADDR =3D 0x30290000, + FSL_IMX7_WDOG1_ADDR =3D 0x30280000, + + FSL_IMX7_IOMUXC_LPSR_GPR_ADDR =3D 0x30270000, + + FSL_IMX7_GPIO7_ADDR =3D 0x30260000, + FSL_IMX7_GPIO6_ADDR =3D 0x30250000, + FSL_IMX7_GPIO5_ADDR =3D 0x30240000, + FSL_IMX7_GPIO4_ADDR =3D 0x30230000, + FSL_IMX7_GPIO3_ADDR =3D 0x30220000, + FSL_IMX7_GPIO2_ADDR =3D 0x30210000, + FSL_IMX7_GPIO1_ADDR =3D 0x30200000, + + FSL_IMX7_AIPS1_CONF_ADDR =3D 0x301F0000, + FSL_IMX7_AIPS1_CONF_SIZE =3D (64 * KiB), =20 - FSL_IMX7_A7MPCORE_ADDR =3D 0x31000000, FSL_IMX7_A7MPCORE_DAP_ADDR =3D 0x30000000, + FSL_IMX7_A7MPCORE_DAP_SIZE =3D (1 * MiB), =20 - FSL_IMX7_PCIE_REG_ADDR =3D 0x33800000, - FSL_IMX7_PCIE_REG_SIZE =3D 16 * 1024, + /* AIPS-1 End */ =20 - FSL_IMX7_GPR_ADDR =3D 0x30340000, + FSL_IMX7_EIM_CS0_ADDR =3D 0x28000000, + FSL_IMX7_EIM_CS0_SIZE =3D (128 * MiB), =20 - FSL_IMX7_DMA_APBH_ADDR =3D 0x33000000, - FSL_IMX7_DMA_APBH_SIZE =3D 0x2000, + FSL_IMX7_OCRAM_PXP_ADDR =3D 0x00940000, + FSL_IMX7_OCRAM_PXP_SIZE =3D (32 * KiB), + + FSL_IMX7_OCRAM_EPDC_ADDR =3D 0x00920000, + FSL_IMX7_OCRAM_EPDC_SIZE =3D (128 * KiB), + + FSL_IMX7_OCRAM_MEM_ADDR =3D 0x00900000, + FSL_IMX7_OCRAM_MEM_SIZE =3D (128 * KiB), + + FSL_IMX7_TCMU_ADDR =3D 0x00800000, + FSL_IMX7_TCMU_SIZE =3D (32 * KiB), + + FSL_IMX7_TCML_ADDR =3D 0x007F8000, + FSL_IMX7_TCML_SIZE =3D (32 * KiB), + + FSL_IMX7_OCRAM_S_ADDR =3D 0x00180000, + FSL_IMX7_OCRAM_S_SIZE =3D (32 * KiB), + + FSL_IMX7_CAAM_MEM_ADDR =3D 0x00100000, + FSL_IMX7_CAAM_MEM_SIZE =3D (32 * KiB), + + FSL_IMX7_ROM_ADDR =3D 0x00000000, + FSL_IMX7_ROM_SIZE =3D (96 * KiB), }; =20 enum FslIMX7IRQs { diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 9e41d4b6772..e9760535393 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -36,6 +36,9 @@ static void fsl_imx7_init(Object *obj) char name[NAME_SIZE]; int i; =20 + /* + * CPUs + */ for (i =3D 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) { snprintf(name, NAME_SIZE, "cpu%d", i); object_initialize_child(obj, name, &s->cpu[i], @@ -49,7 +52,7 @@ static void fsl_imx7_init(Object *obj) TYPE_A15MPCORE_PRIV); =20 /* - * GPIOs 1 to 7 + * GPIOs */ for (i =3D 0; i < FSL_IMX7_NUM_GPIOS; i++) { snprintf(name, NAME_SIZE, "gpio%d", i); @@ -57,7 +60,7 @@ static void fsl_imx7_init(Object *obj) } =20 /* - * GPT1, 2, 3, 4 + * GPTs */ for (i =3D 0; i < FSL_IMX7_NUM_GPTS; i++) { snprintf(name, NAME_SIZE, "gpt%d", i); @@ -79,19 +82,24 @@ static void fsl_imx7_init(Object *obj) */ object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2); =20 + /* + * ECSPIs + */ for (i =3D 0; i < FSL_IMX7_NUM_ECSPIS; i++) { snprintf(name, NAME_SIZE, "spi%d", i + 1); object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); } =20 - + /* + * I2Cs + */ for (i =3D 0; i < FSL_IMX7_NUM_I2CS; i++) { snprintf(name, NAME_SIZE, "i2c%d", i + 1); object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); } =20 /* - * UART + * UARTs */ for (i =3D 0; i < FSL_IMX7_NUM_UARTS; i++) { snprintf(name, NAME_SIZE, "uart%d", i); @@ -99,7 +107,7 @@ static void fsl_imx7_init(Object *obj) } =20 /* - * Ethernet + * Ethernets */ for (i =3D 0; i < FSL_IMX7_NUM_ETHS; i++) { snprintf(name, NAME_SIZE, "eth%d", i); @@ -107,7 +115,7 @@ static void fsl_imx7_init(Object *obj) } =20 /* - * SDHCI + * SDHCIs */ for (i =3D 0; i < FSL_IMX7_NUM_USDHCS; i++) { snprintf(name, NAME_SIZE, "usdhc%d", i); @@ -120,7 +128,7 @@ static void fsl_imx7_init(Object *obj) object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); =20 /* - * Watchdog + * Watchdogs */ for (i =3D 0; i < FSL_IMX7_NUM_WDTS; i++) { snprintf(name, NAME_SIZE, "wdt%d", i); @@ -132,8 +140,14 @@ static void fsl_imx7_init(Object *obj) */ object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR); =20 + /* + * PCIE + */ object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HO= ST); =20 + /* + * USBs + */ for (i =3D 0; i < FSL_IMX7_NUM_USBS; i++) { snprintf(name, NAME_SIZE, "usb%d", i); object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); @@ -156,6 +170,9 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) return; } =20 + /* + * CPUs + */ for (i =3D 0; i < smp_cpus; i++) { o =3D OBJECT(&s->cpu[i]); =20 @@ -206,10 +223,10 @@ static void fsl_imx7_realize(DeviceState *dev, Error = **errp) * A7MPCORE DAP */ create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR, - 0x100000); + FSL_IMX7_A7MPCORE_DAP_SIZE); =20 /* - * GPT1, 2, 3, 4 + * GPTs */ for (i =3D 0; i < FSL_IMX7_NUM_GPTS; i++) { static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] =3D { @@ -234,6 +251,9 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) FSL_IMX7_GPTn_IRQ[i])); } =20 + /* + * GPIOs + */ for (i =3D 0; i < FSL_IMX7_NUM_GPIOS; i++) { static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] =3D { FSL_IMX7_GPIO1_ADDR, @@ -281,16 +301,10 @@ static void fsl_imx7_realize(DeviceState *dev, Error = **errp) /* * IOMUXC and IOMUXC_LPSR */ - for (i =3D 0; i < FSL_IMX7_NUM_IOMUXCS; i++) { - static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = =3D { - FSL_IMX7_IOMUXC_ADDR, - FSL_IMX7_IOMUXC_LPSR_ADDR, - }; - - snprintf(name, NAME_SIZE, "iomuxc%d", i); - create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i], - FSL_IMX7_IOMUXCn_SIZE); - } + create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR, + FSL_IMX7_IOMUXC_SIZE); + create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR, + FSL_IMX7_IOMUXC_LPSR_SIZE); =20 /* * CCM @@ -310,7 +324,9 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR); =20 - /* Initialize all ECSPI */ + /* + * ECSPIs + */ for (i =3D 0; i < FSL_IMX7_NUM_ECSPIS; i++) { static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] =3D { FSL_IMX7_ECSPI1_ADDR, @@ -335,6 +351,9 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) FSL_IMX7_SPIn_IRQ[i])); } =20 + /* + * I2Cs + */ for (i =3D 0; i < FSL_IMX7_NUM_I2CS; i++) { static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] =3D { FSL_IMX7_I2C1_ADDR, @@ -359,7 +378,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) } =20 /* - * UART + * UARTs */ for (i =3D 0; i < FSL_IMX7_NUM_UARTS; i++) { static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] =3D { @@ -394,7 +413,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) } =20 /* - * Ethernet + * Ethernets * * We must use two loops since phy_connected affects the other interfa= ce * and we have to set all properties before calling sysbus_realize(). @@ -434,7 +453,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) } =20 /* - * USDHC + * USDHCs */ for (i =3D 0; i < FSL_IMX7_NUM_USDHCS; i++) { static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] =3D { @@ -464,7 +483,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) * SNVS */ sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR); =20 /* * SRC @@ -472,7 +491,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZ= E); =20 /* - * Watchdog + * Watchdogs */ for (i =3D 0; i < FSL_IMX7_NUM_WDTS; i++) { static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] =3D { @@ -509,25 +528,49 @@ static void fsl_imx7_realize(DeviceState *dev, Error = **errp) create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_= SIZE); =20 /* - * PWM + * PWMs */ - create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_= SIZE); - create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_= SIZE); - create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_= SIZE); - create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_= SIZE); + for (i =3D 0; i < FSL_IMX7_NUM_PWMS; i++) { + static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] =3D { + FSL_IMX7_PWM1_ADDR, + FSL_IMX7_PWM2_ADDR, + FSL_IMX7_PWM3_ADDR, + FSL_IMX7_PWM4_ADDR, + }; + + snprintf(name, NAME_SIZE, "pwm%d", i); + create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i], + FSL_IMX7_PWMn_SIZE); + } =20 /* - * CAN + * CANs */ - create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_= SIZE); - create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_= SIZE); + for (i =3D 0; i < FSL_IMX7_NUM_CANS; i++) { + static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] =3D { + FSL_IMX7_CAN1_ADDR, + FSL_IMX7_CAN2_ADDR, + }; + + snprintf(name, NAME_SIZE, "can%d", i); + create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i], + FSL_IMX7_CANn_SIZE); + } =20 /* - * SAI (Audio SSI (Synchronous Serial Interface)) + * SAIs (Audio SSI (Synchronous Serial Interface)) */ - create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_= SIZE); - create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_= SIZE); - create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_= SIZE); + for (i =3D 0; i < FSL_IMX7_NUM_SAIS; i++) { + static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] =3D { + FSL_IMX7_SAI1_ADDR, + FSL_IMX7_SAI2_ADDR, + FSL_IMX7_SAI3_ADDR, + }; + + snprintf(name, NAME_SIZE, "sai%d", i); + create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i], + FSL_IMX7_SAIn_SIZE); + } =20 /* * OCOTP @@ -535,9 +578,15 @@ static void fsl_imx7_realize(DeviceState *dev, Error *= *errp) create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR, FSL_IMX7_OCOTP_SIZE); =20 + /* + * GPR + */ sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR); =20 + /* + * PCIE + */ sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR); =20 @@ -550,7 +599,9 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) irq =3D qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); =20 - + /* + * USBs + */ for (i =3D 0; i < FSL_IMX7_NUM_USBS; i++) { static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] =3D { FSL_IMX7_USBMISC1_ADDR, @@ -612,6 +663,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) */ create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR, FSL_IMX7_PCIE_PHY_SIZE); + } =20 static Property fsl_imx7_properties[] =3D { --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478863; cv=none; d=zohomail.com; s=zohoarc; b=kSOEW0eniMX8CVw8YUo+SE9m6ExMOjnaHR2htP5UpH8LrqdZHYpGdKULbL0ENq28HsDoR/qKuwYlMUNJMbppGaiU9GM31AeKAy+9apCzpUipDEvMsgXrcfuB8woVh76Wo/WqVVjFMkn4Ufxa75pFJ7cJ4hkSacI1WHKtY6Q1Wuk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478863; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Sd1LpcRGVzLeKAumLs+R9eKwSti+aOLRgWtTQkeU06w=; b=CzJ61ZeL6D6NEuG/0/hijWG29MHT50rdp5JQZ+f9/xw0gfYr6APQw43cy5j5N3283wiohzipZI5f66ZAUiw/9x8SUWzWCKOja7kTBgXWlPiwU7HVLEXY/XE2fkV8dphipx3Vh1JCqUlLxxnZvfdRXRnUNFLzJLCSzQlgnPXJBPw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693478863511910.0848654562811; Thu, 31 Aug 2023 03:47:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbfBN-0003yj-Dm; Thu, 31 Aug 2023 06:45:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbfBB-0003dg-DE for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:37 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbfB3-000446-HM for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:33 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-401bdff4cb4so6265695e9.3 for ; Thu, 31 Aug 2023 03:45:27 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478865676100015 From: Jean-Christophe Dubois * Add TZASC as unimplemented device. - Allow bare metal application to access this (unimplemented) device * Add CSU as unimplemented device. - Allow bare metal application to access this (unimplemented) device * Add various memory segments - OCRAM - OCRAM EPDC - OCRAM PXP - OCRAM S - ROM - CAAM Signed-off-by: Jean-Christophe Dubois Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tri= budubois.net Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx7.h | 7 +++++ hw/arm/fsl-imx7.c | 63 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 06b2c5e4acf..01e15004d76 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -84,6 +84,13 @@ struct FslIMX7State { IMX7GPRState gpr; ChipideaState usb[FSL_IMX7_NUM_USBS]; DesignwarePCIEHost pcie; + MemoryRegion rom; + MemoryRegion caam; + MemoryRegion ocram; + MemoryRegion ocram_epdc; + MemoryRegion ocram_pxp; + MemoryRegion ocram_s; + uint32_t phy_num[FSL_IMX7_NUM_ETHS]; bool phy_connected[FSL_IMX7_NUM_ETHS]; }; diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index e9760535393..97e982bf061 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -664,6 +664,69 @@ static void fsl_imx7_realize(DeviceState *dev, Error *= *errp) create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR, FSL_IMX7_PCIE_PHY_SIZE); =20 + /* + * CSU + */ + create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR, + FSL_IMX7_CSU_SIZE); + + /* + * TZASC + */ + create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR, + FSL_IMX7_TZASC_SIZE); + + /* + * OCRAM memory + */ + memory_region_init_ram(&s->ocram, NULL, "imx7.ocram", + FSL_IMX7_OCRAM_MEM_SIZE, + &error_abort); + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_AD= DR, + &s->ocram); + + /* + * OCRAM EPDC memory + */ + memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc", + FSL_IMX7_OCRAM_EPDC_SIZE, + &error_abort); + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_A= DDR, + &s->ocram_epdc); + + /* + * OCRAM PXP memory + */ + memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp", + FSL_IMX7_OCRAM_PXP_SIZE, + &error_abort); + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_AD= DR, + &s->ocram_pxp); + + /* + * OCRAM_S memory + */ + memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s", + FSL_IMX7_OCRAM_S_SIZE, + &error_abort); + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR, + &s->ocram_s); + + /* + * ROM memory + */ + memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom", + FSL_IMX7_ROM_SIZE, &error_abort); + memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR, + &s->rom); + + /* + * CAAM memory + */ + memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam", + FSL_IMX7_CAAM_MEM_SIZE, &error_abort); + memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADD= R, + &s->caam); } =20 static Property fsl_imx7_properties[] =3D { --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478918; cv=none; d=zohomail.com; s=zohoarc; b=MnlcpIxntL/MIWi811jGx0lrzMYy5F3+r4zwLVTk+qczmciCbBgi8tiPfpsMmYmEbh9aOm6xIiT7TrPoevAznYrKxV6Vy1V975sGLgMPIltEPdMVlhGNDlk5VhE5+3O7m8SKGGCoxuQTg4TptD64QX/ZCCNo0c4B9a/MdtAzNRU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478918; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478727; x=1694083527; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=hSMxzgK5NtAQ3tBUfUnB2Ts1bGZvvfrWIaFEnFIarPQ=; b=h3k3lijPfP0cz3gBzLKu/0SizpXizv9MU3N6HnNC5tC5W2/ldfWHaKmHyKM3j+cEPP hguLGObThRi348dJtGBa+CpcYFi+Y3LFLjha5bRS0yCeCJm5I4CcDOkBLIAo2gfuJf5R dfoQvotd8/iuYrTFaDTEy0SdxqZZ2PM5SVg6YKgJnF3N5zt4t44Df1VmNTLGHOv2/M4f 61IRYu1S0qzV/XLs88cB5zBWt5v/7lWql0WK6+/xWEmUU1zrRsngtdIQiup1ZI2VbcmH b7xxKmlIyVsRTyGfIAesxGOL3tJ99W8ZTjjUPkqXQFjRA8QIFGnKIK0FGcDHklx4F6bG 4EAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478727; x=1694083527; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hSMxzgK5NtAQ3tBUfUnB2Ts1bGZvvfrWIaFEnFIarPQ=; b=QhkOgTOBUBxgUmLKMwQqVR+ABmbLkbqqA32+JNeNGUOAgJRf7lpF3AXeNTlpQGtMwY 4EGSn62nrqdwOnXkMwvXdZx+DUZrZ8njIrP7xOEgJkar8Hs5Ez0IRsunPAZ4WNI+7DD9 vD0y7FcmuMGKpSphx6MPGJRn4xOpyhlLyRCo7HEIMehEg9oI4V6s0JFDQImbsLDklhb0 UpJvTEFzAQcuNBFU7Exv6stg48KqcL9FRrZ+SYr4cfmMT5DbD2nVLnf9eZY762X0E+G9 OYPsa/GJSbjC/SbFHZ9s7P10trokPIi4dSi1Av61E1AJS8BkKQR3IDQzzq9xuTPoYgJZ JOAA== X-Gm-Message-State: AOJu0YyBbFAs0icbOdE0zQUafxb37EQYAhUl3KUd2PHicpAsW4g5viNh qDap8Bu8jebOOyeyrGwmWfu7iCXm7VWpJmpMr+o= X-Google-Smtp-Source: AGHT+IHriij9bF7BLNtZSbccTvHTxDKA0BiBTqyGZPBaBmwO9/MPdp9oyJseYaUZfkW0HdUuLdZnYw== X-Received: by 2002:a2e:9795:0:b0:2bc:daa2:7838 with SMTP id y21-20020a2e9795000000b002bcdaa27838mr4227029lji.19.1693478727354; Thu, 31 Aug 2023 03:45:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/24] Add i.MX7 SRC device implementation Date: Thu, 31 Aug 2023 11:45:11 +0100 Message-Id: <20230831104519.3520658-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::232; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478919201100005 Content-Type: text/plain; charset="utf-8" From: Jean-Christophe Dubois The SRC device is normally used to start the secondary CPU. When running Linux directly, QEMU is emulating a PSCI interface that UBOOT is installing at boot time and therefore the fact that the SRC device is unimplemented is hidden as Qemu respond directly to PSCI requets without using the SRC device. But if you try to run a more bare metal application (maybe uboot itself), then it is not possible to start the secondary CPU as the SRC is an unimplemented device. This patch adds the ability to start the secondary CPU through the SRC device so that you can use this feature in bare metal applications. Signed-off-by: Jean-Christophe Dubois Reviewed-by: Peter Maydell Message-id: ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tri= budubois.net Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx7.h | 3 +- include/hw/misc/imx7_src.h | 66 +++++++++ hw/arm/fsl-imx7.c | 8 +- hw/misc/imx7_src.c | 276 +++++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + hw/misc/trace-events | 4 + 6 files changed, 356 insertions(+), 2 deletions(-) create mode 100644 include/hw/misc/imx7_src.h create mode 100644 hw/misc/imx7_src.c diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 01e15004d76..2cbfc6b2b2c 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -25,6 +25,7 @@ #include "hw/misc/imx7_ccm.h" #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx7_gpr.h" +#include "hw/misc/imx7_src.h" #include "hw/watchdog/wdt_imx2.h" #include "hw/gpio/imx_gpio.h" #include "hw/char/imx_serial.h" @@ -74,6 +75,7 @@ struct FslIMX7State { IMX7CCMState ccm; IMX7AnalogState analog; IMX7SNVSState snvs; + IMX7SRCState src; IMXGPCv2State gpcv2; IMXSPIState spi[FSL_IMX7_NUM_ECSPIS]; IMXI2CState i2c[FSL_IMX7_NUM_I2CS]; @@ -292,7 +294,6 @@ enum FslIMX7MemoryMap { FSL_IMX7_GPC_ADDR =3D 0x303A0000, =20 FSL_IMX7_SRC_ADDR =3D 0x30390000, - FSL_IMX7_SRC_SIZE =3D (4 * KiB), =20 FSL_IMX7_CCM_ADDR =3D 0x30380000, =20 diff --git a/include/hw/misc/imx7_src.h b/include/hw/misc/imx7_src.h new file mode 100644 index 00000000000..b4b97dcb1c1 --- /dev/null +++ b/include/hw/misc/imx7_src.h @@ -0,0 +1,66 @@ +/* + * IMX7 System Reset Controller + * + * Copyright (C) 2023 Jean-Christophe Dubois + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef IMX7_SRC_H +#define IMX7_SRC_H + +#include "hw/sysbus.h" +#include "qemu/bitops.h" +#include "qom/object.h" + +#define SRC_SCR 0 +#define SRC_A7RCR0 1 +#define SRC_A7RCR1 2 +#define SRC_M4RCR 3 +#define SRC_ERCR 5 +#define SRC_HSICPHY_RCR 7 +#define SRC_USBOPHY1_RCR 8 +#define SRC_USBOPHY2_RCR 9 +#define SRC_MPIPHY_RCR 10 +#define SRC_PCIEPHY_RCR 11 +#define SRC_SBMR1 22 +#define SRC_SRSR 23 +#define SRC_SISR 26 +#define SRC_SIMR 27 +#define SRC_SBMR2 28 +#define SRC_GPR1 29 +#define SRC_GPR2 30 +#define SRC_GPR3 31 +#define SRC_GPR4 32 +#define SRC_GPR5 33 +#define SRC_GPR6 34 +#define SRC_GPR7 35 +#define SRC_GPR8 36 +#define SRC_GPR9 37 +#define SRC_GPR10 38 +#define SRC_MAX 39 + +/* SRC_A7SCR1 */ +#define R_CORE1_ENABLE_SHIFT 1 +#define R_CORE1_ENABLE_LENGTH 1 +/* SRC_A7SCR0 */ +#define R_CORE1_RST_SHIFT 5 +#define R_CORE1_RST_LENGTH 1 +#define R_CORE0_RST_SHIFT 4 +#define R_CORE0_RST_LENGTH 1 + +#define TYPE_IMX7_SRC "imx7.src" +OBJECT_DECLARE_SIMPLE_TYPE(IMX7SRCState, IMX7_SRC) + +struct IMX7SRCState { + /* */ + SysBusDevice parent_obj; + + /* */ + MemoryRegion iomem; + + uint32_t regs[SRC_MAX]; +}; + +#endif /* IMX7_SRC_H */ diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 97e982bf061..474cfdc87c6 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -82,6 +82,11 @@ static void fsl_imx7_init(Object *obj) */ object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2); =20 + /* + * SRC + */ + object_initialize_child(obj, "src", &s->src, TYPE_IMX7_SRC); + /* * ECSPIs */ @@ -488,7 +493,8 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) /* * SRC */ - create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZ= E); + sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX7_SRC_ADDR); =20 /* * Watchdogs diff --git a/hw/misc/imx7_src.c b/hw/misc/imx7_src.c new file mode 100644 index 00000000000..983251e86f7 --- /dev/null +++ b/hw/misc/imx7_src.c @@ -0,0 +1,276 @@ +/* + * IMX7 System Reset Controller + * + * Copyright (c) 2023 Jean-Christophe Dubois + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "hw/misc/imx7_src.h" +#include "migration/vmstate.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qemu/main-loop.h" +#include "qemu/module.h" +#include "target/arm/arm-powerctl.h" +#include "hw/core/cpu.h" +#include "hw/registerfields.h" + +#include "trace.h" + +static const char *imx7_src_reg_name(uint32_t reg) +{ + static char unknown[20]; + + switch (reg) { + case SRC_SCR: + return "SRC_SCR"; + case SRC_A7RCR0: + return "SRC_A7RCR0"; + case SRC_A7RCR1: + return "SRC_A7RCR1"; + case SRC_M4RCR: + return "SRC_M4RCR"; + case SRC_ERCR: + return "SRC_ERCR"; + case SRC_HSICPHY_RCR: + return "SRC_HSICPHY_RCR"; + case SRC_USBOPHY1_RCR: + return "SRC_USBOPHY1_RCR"; + case SRC_USBOPHY2_RCR: + return "SRC_USBOPHY2_RCR"; + case SRC_PCIEPHY_RCR: + return "SRC_PCIEPHY_RCR"; + case SRC_SBMR1: + return "SRC_SBMR1"; + case SRC_SRSR: + return "SRC_SRSR"; + case SRC_SISR: + return "SRC_SISR"; + case SRC_SIMR: + return "SRC_SIMR"; + case SRC_SBMR2: + return "SRC_SBMR2"; + case SRC_GPR1: + return "SRC_GPR1"; + case SRC_GPR2: + return "SRC_GPR2"; + case SRC_GPR3: + return "SRC_GPR3"; + case SRC_GPR4: + return "SRC_GPR4"; + case SRC_GPR5: + return "SRC_GPR5"; + case SRC_GPR6: + return "SRC_GPR6"; + case SRC_GPR7: + return "SRC_GPR7"; + case SRC_GPR8: + return "SRC_GPR8"; + case SRC_GPR9: + return "SRC_GPR9"; + case SRC_GPR10: + return "SRC_GPR10"; + default: + sprintf(unknown, "%u ?", reg); + return unknown; + } +} + +static const VMStateDescription vmstate_imx7_src =3D { + .name =3D TYPE_IMX7_SRC, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, IMX7SRCState, SRC_MAX), + VMSTATE_END_OF_LIST() + }, +}; + +static void imx7_src_reset(DeviceState *dev) +{ + IMX7SRCState *s =3D IMX7_SRC(dev); + + memset(s->regs, 0, sizeof(s->regs)); + + /* Set reset values */ + s->regs[SRC_SCR] =3D 0xA0; + s->regs[SRC_SRSR] =3D 0x1; + s->regs[SRC_SIMR] =3D 0x1F; +} + +static uint64_t imx7_src_read(void *opaque, hwaddr offset, unsigned size) +{ + uint32_t value =3D 0; + IMX7SRCState *s =3D (IMX7SRCState *)opaque; + uint32_t index =3D offset >> 2; + + if (index < SRC_MAX) { + value =3D s->regs[index]; + } else { + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" + HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset); + } + + trace_imx7_src_read(imx7_src_reg_name(index), value); + + return value; +} + + +/* + * The reset is asynchronous so we need to defer clearing the reset + * bit until the work is completed. + */ + +struct SRCSCRResetInfo { + IMX7SRCState *s; + uint32_t reset_bit; +}; + +static void imx7_clear_reset_bit(CPUState *cpu, run_on_cpu_data data) +{ + struct SRCSCRResetInfo *ri =3D data.host_ptr; + IMX7SRCState *s =3D ri->s; + + assert(qemu_mutex_iothread_locked()); + + s->regs[SRC_A7RCR0] =3D deposit32(s->regs[SRC_A7RCR0], ri->reset_bit, = 1, 0); + + trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0= ]); + + g_free(ri); +} + +static void imx7_defer_clear_reset_bit(uint32_t cpuid, + IMX7SRCState *s, + uint32_t reset_shift) +{ + struct SRCSCRResetInfo *ri; + CPUState *cpu =3D arm_get_cpu_by_id(cpuid); + + if (!cpu) { + return; + } + + ri =3D g_new(struct SRCSCRResetInfo, 1); + ri->s =3D s; + ri->reset_bit =3D reset_shift; + + async_run_on_cpu(cpu, imx7_clear_reset_bit, RUN_ON_CPU_HOST_PTR(ri)); +} + + +static void imx7_src_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + IMX7SRCState *s =3D (IMX7SRCState *)opaque; + uint32_t index =3D offset >> 2; + long unsigned int change_mask; + uint32_t current_value =3D value; + + if (index >=3D SRC_MAX) { + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" + HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset); + return; + } + + trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0= ]); + + change_mask =3D s->regs[index] ^ (uint32_t)current_value; + + switch (index) { + case SRC_A7RCR0: + if (FIELD_EX32(change_mask, CORE0, RST)) { + arm_reset_cpu(0); + imx7_defer_clear_reset_bit(0, s, R_CORE0_RST_SHIFT); + } + if (FIELD_EX32(change_mask, CORE1, RST)) { + arm_reset_cpu(1); + imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT); + } + s->regs[index] =3D current_value; + break; + case SRC_A7RCR1: + /* + * On real hardware when the system reset controller starts a + * secondary CPU it runs through some boot ROM code which reads + * the SRC_GPRX registers controlling the start address and branch= es + * to it. + * Here we are taking a short cut and branching directly to the + * requested address (we don't want to run the boot ROM code inside + * QEMU) + */ + if (FIELD_EX32(change_mask, CORE1, ENABLE)) { + if (FIELD_EX32(current_value, CORE1, ENABLE)) { + /* CORE 1 is brought up */ + arm_set_cpu_on(1, s->regs[SRC_GPR3], s->regs[SRC_GPR4], + 3, false); + } else { + /* CORE 1 is shut down */ + arm_set_cpu_off(1); + } + /* We clear the reset bits as the processor changed state */ + imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT); + clear_bit(R_CORE1_RST_SHIFT, &change_mask); + } + s->regs[index] =3D current_value; + break; + default: + s->regs[index] =3D current_value; + break; + } +} + +static const struct MemoryRegionOps imx7_src_ops =3D { + .read =3D imx7_src_read, + .write =3D imx7_src_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + /* + * Our device would not work correctly if the guest was doing + * unaligned access. This might not be a limitation on the real + * device but in practice there is no reason for a guest to access + * this device unaligned. + */ + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, +}; + +static void imx7_src_realize(DeviceState *dev, Error **errp) +{ + IMX7SRCState *s =3D IMX7_SRC(dev); + + memory_region_init_io(&s->iomem, OBJECT(dev), &imx7_src_ops, s, + TYPE_IMX7_SRC, 0x1000); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); +} + +static void imx7_src_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D imx7_src_realize; + dc->reset =3D imx7_src_reset; + dc->vmsd =3D &vmstate_imx7_src; + dc->desc =3D "i.MX6 System Reset Controller"; +} + +static const TypeInfo imx7_src_info =3D { + .name =3D TYPE_IMX7_SRC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(IMX7SRCState), + .class_init =3D imx7_src_class_init, +}; + +static void imx7_src_register_types(void) +{ + type_register_static(&imx7_src_info); +} + +type_init(imx7_src_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 892f8b91c57..d9a370c1de2 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -60,6 +60,7 @@ system_ss.add(when: 'CONFIG_IMX', if_true: files( 'imx6_src.c', 'imx6ul_ccm.c', 'imx7_ccm.c', + 'imx7_src.c', 'imx7_gpr.c', 'imx7_snvs.c', 'imx_ccm.c', diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 4d1a0e17af5..e8b2be14c05 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -199,6 +199,10 @@ ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = =3D %d) =3D %d" ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <=3D 0x%" PRIx= 32 ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] =3D> 0x%" PRI= x32 =20 +# imx7_src.c +imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] =3D> 0x%" PRI= x32 +imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <=3D 0x%" PR= Ix32 + # iotkit-sysinfo.c iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit= SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKi= t SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478914; cv=none; d=zohomail.com; s=zohoarc; b=CP/zhrKIv2zChsa3VnAYddOlDTOHfTJw/MTTMfxeXLCa5kHKe7nynaGxCMJSZ4GQUPmHz5PVgv3nx2uS7pg2TkfLelgj241tSlytOsFaOfgGS7RHLMQZf75miXvt/5y3tW885vGEVR2awNgDz4Ow7916tfY3xKTlodakdRqicIw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478914; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QhVdc3OQbrieoN9KEVVJ4cHPM40QA7TFXVC/nD97cgo=; b=BQAEdDuH3xC/452dHDoFo+zJHPlKKrTRmxCr+7qDYvcu7teg8X+VcDRXhBYkHBpH/6qQz+DznHfKTnqufhbXrnEw74Fxdla6AMz43z7o53zawASRX4jwXK0SDJz5oI2zolzaXMjTp+6yOPcODsWKc5ZHqM1irM/uQV2FgeMI9Ps= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16934789140211020.4460035797716; Thu, 31 Aug 2023 03:48:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbfBL-0003rQ-5h; Thu, 31 Aug 2023 06:45:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbfB7-0003ZY-HJ for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:34 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbfB3-00044O-GL for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:32 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-401d24f1f27so6410015e9.1 for ; Thu, 31 Aug 2023 03:45:28 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478728; x=1694083528; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=QhVdc3OQbrieoN9KEVVJ4cHPM40QA7TFXVC/nD97cgo=; b=UGtXE3VU5X0nm5b0Ax1H1ZU+ztX2WIbCpKlHXstWtNo8aadh+Y86dn2r/lGsbVW+Ac 2g9+8pa8koz7B6bD79+Cz5aa6718k/pI/ym02flbEZLj3sAfrnkS/XMoP/cVjxtDXdan 2yxe7qfknHKiNtKt5v4Uu4u15PgeqrkPQa1Edt+xqW+zH9/Sub3WNHscml0VbMZcYeVO cKpN7S0QthAPMBLhVYJ2WO8Ykx4fyEFx7t/TkjM4NJLt+tFnKuNG3tUBzgQaPTFi2TS5 eJMTypLTtN+x5t1GH+hrQLyHzMsrtO03Wt4ziBdXhMg1Fc8oy8G4wvUXZQiGZLRwNJJ7 VkmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478728; x=1694083528; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QhVdc3OQbrieoN9KEVVJ4cHPM40QA7TFXVC/nD97cgo=; b=ViXxsLZxYeVPvVOFyc9+VoNW/bEUHSepC0OB7xs2CE7YUuYNUOZ0W94NtcDmIpMsiu PJTj4BblD69P2XEw9XZRpZAsbU2v5W5MJw+rPzHXDy87JItqhzORQdHPHR2P/piPQ+wH hiQ2CfoVUaBg7cnwoTK/XzkLkL9UKd8J2uppjZyZ2r6eM7I9qlC+iIKztZ1XcU+f6vI3 1WmNCwXZfaKDQHgguP+dH97SGpak31e6PIrZ/bERi9AVk33E8hvrwOj0/wzp+4mOczSR d+VcYCZ4MGEiXQI4qdxcnHsx4NujmAgfPfARCl5X6m5u61MjH9PS1HL0cO3TgzsC1oWi O57A== X-Gm-Message-State: AOJu0YwcDBNbptlIKaGsXnQEyYl1UE9BONa3x1yUK9WNYfzuQcRTW1pb hn5d5DICA8+NhQkpeDb7M1sLFQziU1SZd3KD6Ag= X-Google-Smtp-Source: AGHT+IGqegNlSD4UQa4Ou5EKDEFVl02gFXk7Im51sg9NFmdkbUkcx5jGECNkrs+Evss5d3ch2qsUgg== X-Received: by 2002:a05:600c:cb:b0:3f9:b430:199b with SMTP id u11-20020a05600c00cb00b003f9b430199bmr3853750wmm.15.1693478727863; Thu, 31 Aug 2023 03:45:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/24] target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS Date: Thu, 31 Aug 2023 11:45:12 +0100 Message-Id: <20230831104519.3520658-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478915252100001 Content-Type: text/plain; charset="utf-8" The architecture requires (R_TYTWB) that an attempt to return from EL3 when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This enforces that the CPU can't ever be executing below EL3 with the NSE,NS bits indicating an invalid security state.) We were missing this check; add it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230807150618.101357-1-peter.maydell@linaro.org --- target/arm/tcg/helper-a64.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 1c9370f07bd..0cf56f6dc44 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -780,6 +780,15 @@ void HELPER(exception_return)(CPUARMState *env, uint64= _t new_pc) spsr &=3D ~PSTATE_SS; } =20 + /* + * FEAT_RME forbids return from EL3 with an invalid security state. + * We don't need an explicit check for FEAT_RME here because we enforce + * in scr_write() that you can't set the NSE bit without it. + */ + if (cur_el =3D=3D 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) =3D=3D= SCR_NSE) { + goto illegal_return; + } + new_el =3D el_from_spsr(spsr); if (new_el =3D=3D -1) { goto illegal_return; --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478788; cv=none; d=zohomail.com; s=zohoarc; b=LuL8Hyz7ooNH6CARcHc021eJcrEO+9qX/6wXm1RGD9arGoEXthOjcza6TrXB45XSStmhSTCa73xobwv9f6ytj4ucwJNCKw5RucaQMTvYU4aoiePwx9sLuvjvN/Mnuc1ARGo7N3bpWowa4jjmoqnCHG4CyBNFC3tNBdHVMuCJEA8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478788; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=s00V8qsZzvUC1XcFHALZKjs4t4kYMM3LSzHUfv3Lp2w=; b=S43fEBZGz2SZioZ91Vb7fdC+SNdd2jnBPGwVRdr73lQSC9Xks8TtHOU8gQd5Bqx1uBVu8t6X5nmArOMH/UV45pzYy4p5SHvWoTTyq311sGR5buJW3vkqLoBqeL01w/E7+UA8fm9fbrr347mhdzd2yUDhPA6Elg3m/VwtQXtXgEU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693478788970435.7124846103552; Thu, 31 Aug 2023 03:46:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbfBO-000443-KX; Thu, 31 Aug 2023 06:45:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbfBB-0003dc-BZ for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:37 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbfB4-00044W-8M for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:33 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-401b393df02so6708195e9.1 for ; Thu, 31 Aug 2023 03:45:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478728; x=1694083528; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=s00V8qsZzvUC1XcFHALZKjs4t4kYMM3LSzHUfv3Lp2w=; b=H6tli410nSAl/cOOAylZow8bq0X/PMOuwoh/GUEOCwZWLbaOYXFgUnsmRO95uz0o33 bEyBuIgUrQtNsmnxG1vEKm/bGFdEemyHa6eU/xIxLKjzic9e9dbmjXlYpHRJq3u9s2Gl p37h499FJdBNJj8FzDYRN6pT8HeqZ3fHl8cFECJdE9X8syrNlZYfjcp/DM1bV5cFYIVC CjtDCWfsmt1Jmh8AwLPLwQLjWznbDua1G1WkynN3SIazH095obE3kY6yzCCTzkwkpvpQ LCa6bR7IkeQgp6j3NCqlRz8u5Q6J4k7MIPZn+MU1fx+mO6kqiFi8X7j8XZjzVaIgim8s RMGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478728; x=1694083528; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=s00V8qsZzvUC1XcFHALZKjs4t4kYMM3LSzHUfv3Lp2w=; b=AjrR/DKnLrIHdzZYEQjW4lzQEi+o9JLre3M5jM8MWv/B3JKQg12bUXsmRrt4Ip7Rwv eKh9PQkDOp7cC1WIei5hXTapR+2DYiEuI2iJng7bnduW1I6cMXKYacsoKvaemL0XSnZv nPS371ij1D3jLKq1BnFSn0A624hYHs3ifpRdiucq65mnVa7OnJZcC3ca+m5VJwaVdAKP HCawLCZs65wsrKhOWFqYjAkGwAzG9niEY2/0+DFFYddIunqwK950HHBZqCo/rI/bik9R b/iW4HJiqiaTpCeWXcklkfO810LtkAff4Hbq9JviDjG0ioEyDXMNE1Pc9Y3bVIUSBC7H mKEQ== X-Gm-Message-State: AOJu0YxpQEszlLT4oKT2WzXcT/UZtC14ty3Z0Ftfng1VBsNYmLlvpDZZ 9hj7dspNNPXpoCoNGpER6EhrapFoHmbCaGfKpTg= X-Google-Smtp-Source: AGHT+IHv9BctU1+HNVOmJD8U+nvcwo6FsYbPiroJU/BevvSY1CFmQebJhMnCFDwCK4RBsI2wSX4PGg== X-Received: by 2002:a5d:4088:0:b0:317:3deb:a899 with SMTP id o8-20020a5d4088000000b003173deba899mr3119478wrp.1.1693478728234; Thu, 31 Aug 2023 03:45:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/24] hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm() Date: Thu, 31 Aug 2023 11:45:13 +0100 Message-Id: <20230831104519.3520658-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478790709100005 In the m48t59 device we almost always use 64-bit arithmetic when dealing with time_t deltas. The one exception is in set_alarm(), which currently uses a plain 'int' to hold the difference between two time_t values. Switch to int64_t instead to avoid any possible overflow issues. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/rtc/m48t59.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/rtc/m48t59.c b/hw/rtc/m48t59.c index ec3e56e84fd..2e2c849985c 100644 --- a/hw/rtc/m48t59.c +++ b/hw/rtc/m48t59.c @@ -133,7 +133,7 @@ static void alarm_cb (void *opaque) =20 static void set_alarm(M48t59State *NVRAM) { - int diff; + int64_t diff; if (NVRAM->alrm_timer !=3D NULL) { timer_del(NVRAM->alrm_timer); diff =3D qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478782; cv=none; d=zohomail.com; s=zohoarc; b=kiBZoiDQriAuhji41tBOrKi0sTJE1u5TOZYG/SXgyJ7We5fxu/d7LYHaBSNa+eljUtAG9oTuVQSPk3263khaBorJkTQT0VSVI3OvZLqU5XkQl98DV51AsaXHbpdDA0qTYUcWojz2eUKYPdH2bBu3gpFu6b16+Rulru4FBnOAn1o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478782; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1CYb36QZUIZDu4UGmBLcVUVYCmpeU0BzYEZkkE+tCKU=; b=NXji2uT9g9nqcLJBNmTn6pwvWmbXyslt3/H+6686D11hvy+y0vkDCzO6qMB9p7efPuq5eN5aI4XEMvVCQqzMp/KM4lpBkfiyuHugL7ZB4cpE3K0QUghnsnQ0BTOQlK4noBBeUVZ71m0ZAq2xfIYyY+DkjIkc7YHwosAmvcuCIZs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693478782183891.655701299332; Thu, 31 Aug 2023 03:46:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbfBU-0004Ch-Np; Thu, 31 Aug 2023 06:45:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbfBB-0003df-CR for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:37 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbfB5-00044d-D3 for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:35 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-31c79850df5so498231f8f.1 for ; Thu, 31 Aug 2023 03:45:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478728; x=1694083528; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=1CYb36QZUIZDu4UGmBLcVUVYCmpeU0BzYEZkkE+tCKU=; b=o8Xsi2YT9edqqf71FfZ5T9ibh21NaeXFxDQYjDjtz1SYGKIYw0z0aEYt7ziXID3rgW nW9UgfD75P2EfNPFogBztu9rII/pE7o5oYDCe9/d2cG2OzveD+nDLkaHxTeXnHrGEcZc a7GdeM8cfqU42UF+K6X7KkUaXXVzi3vZ+KA5ncMOWlf5tmi6CCRa+ckhsbcFPJWgUuzp wWsVbOCJVwXB+j4adRE8Plg3sPcypyN2ksFlqX96tMt/OYkjP4yTzRo+sczOpllpHTD0 rpTdV0v8yyD3+hpX7U6w7nEsQq5f6Gz0j1I+X8vrRB2oxzpOKekVcXNqZdqf9v8csCHj fJSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478728; x=1694083528; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1CYb36QZUIZDu4UGmBLcVUVYCmpeU0BzYEZkkE+tCKU=; b=M1mTUWZTq5Vq/MQSRKDbiOTF4eg3kIsN+5CsFnz1k2UHQmsutUajo4rNBG/F8e9hck Md28im/KXHMJD7b4Zc+8XsTArFTL4ARkcR18UikIdS+BPAwGcGeeDS3kV0O2SU4z5jUf SXDYowfywlENTgUPLqndwgiyHGqu3HzcRqsmX5ZOBSy1GkGeQ/hKP6jcHg7+XvsIA4RH 5OSboZo138b3C0AdPc/NUjLtkQlCU2uno2WD+pbyPdgN0S50cdMxbMuPfb1EOg9zary0 6X9L1nroPM/6XvNKj6OuVu+KCsvgVglqmeRfZCGDOVH07wSiH+maFRBlt/622uWdXH3P Ifgg== X-Gm-Message-State: AOJu0YzbFKOwi7bKtZsfzxwHqHQnoIWY8RghUWYNOTvAy/kdtJGAiTEd NDur59sG10zMLSUfd2stKRmxcnFdhfdk2p3Qgbg= X-Google-Smtp-Source: AGHT+IHxNNxm5cn2PoCaBlJzugEsHOVonXpQzyayfpeCwLwCeiVtmtXW2O3Eg0cmJp0AfUQl4/kLmA== X-Received: by 2002:adf:e692:0:b0:319:7abf:d8e2 with SMTP id r18-20020adfe692000000b003197abfd8e2mr3892992wrm.24.1693478728686; Thu, 31 Aug 2023 03:45:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/24] hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec Date: Thu, 31 Aug 2023 11:45:14 +0100 Message-Id: <20230831104519.3520658-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478783122100001 In the twl92230 device, use int64_t for the two state fields sec_offset and alm_sec, because we set these to values that are either time_t or differences between two time_t values. These fields aren't saved in vmstate anywhere, so we can safely widen them. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/rtc/twl92230.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/rtc/twl92230.c b/hw/rtc/twl92230.c index d8534dad949..64c61c3daeb 100644 --- a/hw/rtc/twl92230.c +++ b/hw/rtc/twl92230.c @@ -65,8 +65,8 @@ struct MenelausState { struct tm tm; struct tm new; struct tm alm; - int sec_offset; - int alm_sec; + int64_t sec_offset; + int64_t alm_sec; int next_comp; } rtc; uint16_t rtc_next_vmstate; --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478917; cv=none; d=zohomail.com; s=zohoarc; b=fpXSWcwh2twfDyRTopVOs0s+Tgc0wrw+dEerNiOtv+6kkN3S0PQShFCrZqFcoJsEElV6bdXynB8Eg2KUXOZPQcmJz82VV559iNFvsrqkboruan06HrPLLU8+xtDzkJYLiQ+4YNS6SJbzSIRkda7J5ENcmLajewNKrLOl49hGkSE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478917; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MCjuA8VpBXu0MenkuxVKPe+uHxER/DcfJ0S9UzL2X1E=; b=d1GYJoHOJKn1Kbticqn50QasvaVetMLcDX+CC8PNJmI61f+R1gvj2VPpsO8s9NjbXX2SEW8TV2qsZuZOyuz1gaoK+Y+dYG4gWmb+U7tW0wO0raq6WV7vWIVk66fT4GobQWnsvytsgkJFm5W42cLMLWJA5LUA3g4qBK1H8tY2DHo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693478917136753.067023037674; Thu, 31 Aug 2023 03:48:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbfBO-00042d-DE; Thu, 31 Aug 2023 06:45:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbfBB-0003db-Bx for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:37 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbfB5-000453-Cl for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:34 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-401d2e11dacso11782565e9.0 for ; Thu, 31 Aug 2023 03:45:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478729; x=1694083529; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=MCjuA8VpBXu0MenkuxVKPe+uHxER/DcfJ0S9UzL2X1E=; b=hBgAZB2WBTZ2sMBlxcDudK5djuP0XJW0zDaXg/NK3MFwnOndMqMSrzdJ66dv9l5XWx rpp+Smun2er8hJ75/4AY+gz13jNbr9EOCSH9RKKdyAa4yAjkyuJBvJ/NH3zD4uDcWbnL B3C6nYf59rNzbvsMEQZNn7Xu/gIqJrL1OqbJDXlpXeyEsEwwAK5xUoH1O+jMB7DwO9BD TS0jAG04+ok0MllTA2UVYNVXrBwN3SWhGj52sdT0A/RSJoeQ9isGndiHBTADhtWVFKgN Gaeg31cejjEQ/GJamrrTI5f+RBBP0qWi5srKA1rCwbpIKPECp0mCsAcLzj3TD8chiKjB Nmmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478729; x=1694083529; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MCjuA8VpBXu0MenkuxVKPe+uHxER/DcfJ0S9UzL2X1E=; b=KCzkeIX5G3ef4gEf0i/zLpfiHgwlXtiEzNi6iefx9H3lZHbnkmpfE6xOVnmiCzcqM1 WTdBpXGflMSZHtK60u60VmffADmbkQlRDNLIXSlQx2FFfpxBcALTb10S6Aq6gxugtLAd 7LCsXTRnsKFS30tYWVVL1iv0uBE13JqfrPUZPAJhcVoSQ8qjWMU6/TNxRqdQRZ+YTlGT ikNylh91BXKRvuH7JVXCEVqTXl7PlK22oN869yLgSF2eWQNphtjFFh0CexHVjojvzv37 zzU66Y60dyygIe+kDfWQa54PeqIOGfKsomBA88ixuOvMqVTaz/8VhsnmyGMclA1drDML q7qg== X-Gm-Message-State: AOJu0YylhiIIMfgfkDwn7J8UczTVX/A+ETzZOHnMQ+Pv/GKXxSjeOM1f XH8/2DsrbFICLItL2j48oC0NA3hRTr8CRoS9RSc= X-Google-Smtp-Source: AGHT+IHZxCCrWiBn/JuMdyU3FarSQe3DnSF+as/hEw47asgYg0kuJb4Qnq/GpV3cT2yv7cgHAIdZWQ== X-Received: by 2002:a7b:c84f:0:b0:401:b504:b6a8 with SMTP id c15-20020a7bc84f000000b00401b504b6a8mr1745176wml.2.1693478729209; Thu, 31 Aug 2023 03:45:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/24] hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference Date: Thu, 31 Aug 2023 11:45:15 +0100 Message-Id: <20230831104519.3520658-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478917831100001 In the aspeed_rtc device we store a difference between two time_t values in an 'int'. This is not really correct when time_t could be 64 bits. Enlarge the field to 'int64_t'. This is a migration compatibility break for the aspeed boards. While we are changing the vmstate, remove the accidental duplicate of the offset field. Signed-off-by: Peter Maydell Reviewed-by: C=C3=A9dric Le Goater --- include/hw/rtc/aspeed_rtc.h | 2 +- hw/rtc/aspeed_rtc.c | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/include/hw/rtc/aspeed_rtc.h b/include/hw/rtc/aspeed_rtc.h index df61e46059e..596dfebb46c 100644 --- a/include/hw/rtc/aspeed_rtc.h +++ b/include/hw/rtc/aspeed_rtc.h @@ -18,7 +18,7 @@ struct AspeedRtcState { qemu_irq irq; =20 uint32_t reg[0x18]; - int offset; + int64_t offset; =20 }; =20 diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c index f6da7b666d6..fa861e2d494 100644 --- a/hw/rtc/aspeed_rtc.c +++ b/hw/rtc/aspeed_rtc.c @@ -136,11 +136,10 @@ static const MemoryRegionOps aspeed_rtc_ops =3D { =20 static const VMStateDescription vmstate_aspeed_rtc =3D { .name =3D TYPE_ASPEED_RTC, - .version_id =3D 1, + .version_id =3D 2, .fields =3D (VMStateField[]) { VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18), - VMSTATE_INT32(offset, AspeedRtcState), - VMSTATE_INT32(offset, AspeedRtcState), + VMSTATE_INT64(offset, AspeedRtcState), VMSTATE_END_OF_LIST() } }; --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478941; cv=none; d=zohomail.com; s=zohoarc; b=YUXSOmkDoBeWGJSKTNK3ThEULrfy6c4pEWrZ1KHnpL82A5uNH13Swpw9yk1iSR/MoqQAtJxrIty3+jklpiNgp5vht1+BUlJG6cYl4ZYGg9iClCK7fg7ZBBGlY21RMJ9MzZ3sIgz/pV+rpDe4lifnQ7mjNpLh6Pr6XUAFsxPO+YI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478941; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+VSlQGCsD1Pcew2GJP5QWEZRyhS81cLxeQnfhrofKf0=; b=GNZ09RVe5IAzkZNWy3GUw4Fy2klra2eJs/DARLxRkp91AreDuinypjxhVgVpW4WTGIN6l4Wwa2aA0/s4CCFhLly//p91Uj4ciB+JxGjju3BAXEBC2jQUuOe8nGdLJ4ZIWiv8u7PV2wF0PKCvG+RS525d6UQGQptaRl+wzdYXXZA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693478941766126.35712894903133; Thu, 31 Aug 2023 03:49:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbfBL-0003rO-1F; Thu, 31 Aug 2023 06:45:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbfBB-0003dh-Cl for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:37 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbfB5-00045D-Cy for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:35 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-31dcd553fecso480210f8f.2 for ; Thu, 31 Aug 2023 03:45:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478730; x=1694083530; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=+VSlQGCsD1Pcew2GJP5QWEZRyhS81cLxeQnfhrofKf0=; b=ex4ekol4H36W4ge9il9DwlbDng9niFS7UMF5V7Zh5NpLS8DI64gOBXrRT5TtJVdydn rszjjThaTA5gg0Kpm5+n2CnkoOoS8A3xX0oAssNOMh0yd++NHEVWIVAtoa9LgmUZcEsB q/GJSHZgCYCZOz7f9rQBWmELMSUL5ElKbBxCGYMjbEgjUL5apQMoMXiBq3PVEf8vRX0B Cev9y7ri91X7vahKvcK9cWLgLNAQnt5lQgzvAOg5M9cHCYnGK9nQTQ2W4hdAcSymK9si 4i0acVL06DpJl5FAnU+kR7l98k/3BR1ufT07CwiVfkowLFRyJHjaTskA0rfOZ/+GmjFq akhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478730; x=1694083530; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+VSlQGCsD1Pcew2GJP5QWEZRyhS81cLxeQnfhrofKf0=; b=jJQKDF+FWBPUm8OZBLAMHXQubpyXZZszgDD9ERslGoGQ0IqGe4tWXUt99eHg1I6t0q f1Ur6rDrTC4t0Rig5WvxwQQyHqZXNE9I1uaj0AvQeWayJuTiMq2GNkSItCC0qQ3GwP8L /P4TX7Ejq6sawHqJ7n4zhw5q7RM78r1hLzSQZ3icffWf4MJZ/7zZ+6cGp17EzjUceIRb jT3hNxhHeg6ERYu5WQ4sxcXAMoHxbLM0E+vTXSfZJxM/xVe1dAF85A3FvNDXbRLu1pPI QqYg1RTMLIocS3SnO5jcXmtzRwRzUpjN+rP/EHTrJLV8xRJYWzi3hhLoRZ0xr5K5+45a 3kPA== X-Gm-Message-State: AOJu0YxUE9m1tbIvrv0G4H4b+fm792I1dnpNINuXSOY8EqQpkfXQc9MR nNGqGg2mRt/uFkth+ZRxluxY8vKARDgwHfILUF8= X-Google-Smtp-Source: AGHT+IFmOnSKxs0IHqEKGaA0FE9D8X9tHPr6kMiSu4U4D00p8keMroFUKVHzg8LCNnVT66fsC8zQ1w== X-Received: by 2002:a5d:5487:0:b0:319:8a5a:ab5e with SMTP id h7-20020a5d5487000000b003198a5aab5emr3656194wrv.38.1693478729799; Thu, 31 Aug 2023 03:45:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/24] rtc: Use time_t for passing and returning time offsets Date: Thu, 31 Aug 2023 11:45:16 +0100 Message-Id: <20230831104519.3520658-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478943561100003 The functions qemu_get_timedate() and qemu_timedate_diff() take and return a time offset as an integer. Coverity points out that means that when an RTC device implementation holds an offset as a time_t, as the m48t59 does, the time_t will get truncated. (CID 1507157, 1517772). The functions work with time_t internally, so make them use that type in their APIs. Note that this won't help any Y2038 issues where either the device model itself is keeping the offset in a 32-bit integer, or where the hardware under emulation has Y2038 or other rollover problems. If we missed any cases of the former then hopefully Coverity will warn us about them since after this patch we'd be truncating a time_t in assignments from qemu_timedate_diff().) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/sysemu/rtc.h | 4 ++-- softmmu/rtc.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/sysemu/rtc.h b/include/sysemu/rtc.h index 159702b45b5..0fc8ad6fdf1 100644 --- a/include/sysemu/rtc.h +++ b/include/sysemu/rtc.h @@ -42,7 +42,7 @@ * The behaviour of the clock whose value this function returns will * depend on the -rtc command line option passed by the user. */ -void qemu_get_timedate(struct tm *tm, int offset); +void qemu_get_timedate(struct tm *tm, time_t offset); =20 /** * qemu_timedate_diff: Return difference between a struct tm and the RTC @@ -53,6 +53,6 @@ void qemu_get_timedate(struct tm *tm, int offset); * a timestamp one hour further ahead than the current RTC time * then this function will return 3600. */ -int qemu_timedate_diff(struct tm *tm); +time_t qemu_timedate_diff(struct tm *tm); =20 #endif diff --git a/softmmu/rtc.c b/softmmu/rtc.c index 4b2bf75dd67..4904581abeb 100644 --- a/softmmu/rtc.c +++ b/softmmu/rtc.c @@ -68,7 +68,7 @@ static time_t qemu_ref_timedate(QEMUClockType clock) return value; } =20 -void qemu_get_timedate(struct tm *tm, int offset) +void qemu_get_timedate(struct tm *tm, time_t offset) { time_t ti =3D qemu_ref_timedate(rtc_clock); =20 @@ -85,7 +85,7 @@ void qemu_get_timedate(struct tm *tm, int offset) } } =20 -int qemu_timedate_diff(struct tm *tm) +time_t qemu_timedate_diff(struct tm *tm) { time_t seconds; =20 --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478901; cv=none; d=zohomail.com; s=zohoarc; b=m9HMwasM66NePhMiFwIZ7Kj/iIOxm9Ktx87aqXYxTRBY0NstpzH/MoJlF8rvxGTe0wBLh9k+uBjfqnjQmuT3Fz8MMb9wJtDNPzlX7CpYkZO6CB7af124vqPIm7bTwVUgPekQD9pp9JVX7pIaY90cqj7JCqnVYsPRhL6Z/xxzD7E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478901; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Iww7+LJWf4cwL5sY9fwZhO6FiOKCwKe0fmXzE0E9OwM=; b=FLApKm1IvXUlD4UvVHY5Wwj5vGB4XVbnfjDI9oVzGvE7lMUgTwsOVToSifnTaB1ZAj93oc1yrqfmV92dDQmupNN2zvM+dd1pUnItVMrPH5uDA0Pwjo9GE8I+QVQCqqJvQ+Oul/vJmSzeYpF6snCowTELifANNjde3LiNi1o9ieg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693478901804253.4285291900144; Thu, 31 Aug 2023 03:48:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbfBP-00048g-Ul; Thu, 31 Aug 2023 06:45:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbfBB-0003dj-DE for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:37 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbfB6-00045I-I6 for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:36 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-4018af1038cso6206435e9.0 for ; Thu, 31 Aug 2023 03:45:31 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478730; x=1694083530; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Iww7+LJWf4cwL5sY9fwZhO6FiOKCwKe0fmXzE0E9OwM=; b=JvD3K4bT+a3SnmJWTGNZg1XEjb9X+IyJfGq+qdS3YhsYOAsxvOzLpCbEoontKIUoNF zRPr9m6fGJNzhovYRqCujmC6rLij05RmRh3/MEBsKVByBf8tk7YwX3FCt1b4nIlKoHIA 4LEZRVLqR6N/gDbbYJpy7HFMdvxcDuFLd5TMhp7HwuccusClv2PRoAE8LLU7xKQWROc5 OkdNWvo7kiCzZKN4kH8EDGXz+8JvJ3ntYkW9RqFspKzfpsIPMbTM9CBveXcVHD4ns2Y1 lQgRHso5oli9w+XtULmjmobSx/47cRgnWaL9GKqDHndaBh2sGquuS5Ah2WwYZ/S/BRZA XYZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478730; x=1694083530; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Iww7+LJWf4cwL5sY9fwZhO6FiOKCwKe0fmXzE0E9OwM=; b=ILIWrTWU6t/raDE8/9pVVspxT2/dMewt88vphjk1GcAfFYhUahFp76SPj76AdeZl0f xUOBoOhPs7loFXVDMnPLyYyXtqvhYFbbZmDdSP7f6fZLq5jP5k5aBvK7hcic/9Iyr9AN r49L0oi0snNp/NWe+GzrURHH8k6CfVdfkcbr/VZc35SLr1B0bFg3AL8ln4jvWGy7g59v 4qTt84U1LzStv8OOm2bQYuO+HUNudlX7gL5psj21k8md1/VrdR7uQt6b/TOD32fxy8FP 1Zk4FlYJZJ4KEMCAHT1rms8WokT2G2CMxPmRuXADDtSagxLwTByDiCu+Ve6ksSOCgyNx 3Fgg== X-Gm-Message-State: AOJu0YyYpBeS75jaKbQUpIToWLFEGWftwj0uGiCJNEsFm5XvkE7tb+5w F2xr62p8yiOmHAUFDKZeg5jIEvz/Ti6S051A7VM= X-Google-Smtp-Source: AGHT+IGBwB7s0OtFR+0BjcIQ02fAgU/8Ixse5vnBCYQw5I3h5CfmSEjB8XOSmyqi5SZmmrBN4PMolw== X-Received: by 2002:adf:f2d1:0:b0:314:dc0:2fca with SMTP id d17-20020adff2d1000000b003140dc02fcamr3494265wrp.29.1693478730193; Thu, 31 Aug 2023 03:45:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/24] target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init Date: Thu, 31 Aug 2023 11:45:17 +0100 Message-Id: <20230831104519.3520658-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478903365100001 Content-Type: text/plain; charset="utf-8" Where architecturally one ARM_FEATURE_X flag implies another ARM_FEATURE_Y, we allow the CPU init function to only set X, and then set Y for it. Currently we do this in two places -- we set a few flags in arm_cpu_post_init() because we need them to decide which properties to create on the CPU object, and then we do the rest in arm_cpu_realizefn(). However, this is fragile, because it's easy to add a new property and not notice that this means that an X-implies-Y check now has to move from realize to post-init. As a specific example, the pmsav7-dregion property is conditional on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and rely on V8-implies-V7, which doesn't happen until the realizefn. Move all of these X-implies-Y checks into a new function, which we call at the top of arm_cpu_post_init(), so the feature bits are available at that point. This does now give us the reverse issue, that if there's a feature bit which is enabled or disabled by the setting of a property then then X-implies-Y features that are dependent on that property need to be in realize, not in this new function. But the only one of those is the "EL3 implies VBAR" which is already in the right place, so putting things this way round seems better to me. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org --- target/arm/cpu.c | 179 +++++++++++++++++++++++++---------------------- 1 file changed, 97 insertions(+), 82 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 17540300feb..0bb05854419 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1356,17 +1356,108 @@ unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; } =20 +static void arm_cpu_propagate_feature_implications(ARMCPU *cpu) +{ + CPUARMState *env =3D &cpu->env; + bool no_aa32 =3D false; + + /* + * Some features automatically imply others: set the feature + * bits explicitly for these cases. + */ + + if (arm_feature(env, ARM_FEATURE_M)) { + set_feature(env, ARM_FEATURE_PMSA); + } + + if (arm_feature(env, ARM_FEATURE_V8)) { + if (arm_feature(env, ARM_FEATURE_M)) { + set_feature(env, ARM_FEATURE_V7); + } else { + set_feature(env, ARM_FEATURE_V7VE); + } + } + + /* + * There exist AArch64 cpus without AArch32 support. When KVM + * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. + * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. + * As a general principle, we also do not make ID register + * consistency checks anywhere unless using TCG, because only + * for TCG would a consistency-check failure be a QEMU bug. + */ + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + no_aa32 =3D !cpu_isar_feature(aa64_aa32, cpu); + } + + if (arm_feature(env, ARM_FEATURE_V7VE)) { + /* + * v7 Virtualization Extensions. In real hardware this implies + * EL2 and also the presence of the Security Extensions. + * For QEMU, for backwards-compatibility we implement some + * CPUs or CPU configs which have no actual EL2 or EL3 but do + * include the various other features that V7VE implies. + * Presence of EL2 itself is ARM_FEATURE_EL2, and of the + * Security Extensions is ARM_FEATURE_EL3. + */ + assert(!tcg_enabled() || no_aa32 || + cpu_isar_feature(aa32_arm_div, cpu)); + set_feature(env, ARM_FEATURE_LPAE); + set_feature(env, ARM_FEATURE_V7); + } + if (arm_feature(env, ARM_FEATURE_V7)) { + set_feature(env, ARM_FEATURE_VAPA); + set_feature(env, ARM_FEATURE_THUMB2); + set_feature(env, ARM_FEATURE_MPIDR); + if (!arm_feature(env, ARM_FEATURE_M)) { + set_feature(env, ARM_FEATURE_V6K); + } else { + set_feature(env, ARM_FEATURE_V6); + } + + /* + * Always define VBAR for V7 CPUs even if it doesn't exist in + * non-EL3 configs. This is needed by some legacy boards. + */ + set_feature(env, ARM_FEATURE_VBAR); + } + if (arm_feature(env, ARM_FEATURE_V6K)) { + set_feature(env, ARM_FEATURE_V6); + set_feature(env, ARM_FEATURE_MVFR); + } + if (arm_feature(env, ARM_FEATURE_V6)) { + set_feature(env, ARM_FEATURE_V5); + if (!arm_feature(env, ARM_FEATURE_M)) { + assert(!tcg_enabled() || no_aa32 || + cpu_isar_feature(aa32_jazelle, cpu)); + set_feature(env, ARM_FEATURE_AUXCR); + } + } + if (arm_feature(env, ARM_FEATURE_V5)) { + set_feature(env, ARM_FEATURE_V4T); + } + if (arm_feature(env, ARM_FEATURE_LPAE)) { + set_feature(env, ARM_FEATURE_V7MP); + } + if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { + set_feature(env, ARM_FEATURE_CBAR); + } + if (arm_feature(env, ARM_FEATURE_THUMB2) && + !arm_feature(env, ARM_FEATURE_M)) { + set_feature(env, ARM_FEATURE_THUMB_DSP); + } +} + void arm_cpu_post_init(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); =20 - /* M profile implies PMSA. We have to do this here rather than - * in realize with the other feature-implication checks because - * we look at the PMSA bit to see if we should add some properties. + /* + * Some features imply others. Figure this out now, because we + * are going to look at the feature bits in deciding which + * properties to add. */ - if (arm_feature(&cpu->env, ARM_FEATURE_M)) { - set_feature(&cpu->env, ARM_FEATURE_PMSA); - } + arm_cpu_propagate_feature_implications(cpu); =20 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { @@ -1588,7 +1679,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) CPUARMState *env =3D &cpu->env; int pagebits; Error *local_err =3D NULL; - bool no_aa32 =3D false; =20 /* Use pc-relative instructions in system-mode */ #ifndef CONFIG_USER_ONLY @@ -1869,81 +1959,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) cpu->isar.id_isar3 =3D u; } =20 - /* Some features automatically imply others: */ - if (arm_feature(env, ARM_FEATURE_V8)) { - if (arm_feature(env, ARM_FEATURE_M)) { - set_feature(env, ARM_FEATURE_V7); - } else { - set_feature(env, ARM_FEATURE_V7VE); - } - } - - /* - * There exist AArch64 cpus without AArch32 support. When KVM - * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. - * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. - * As a general principle, we also do not make ID register - * consistency checks anywhere unless using TCG, because only - * for TCG would a consistency-check failure be a QEMU bug. - */ - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - no_aa32 =3D !cpu_isar_feature(aa64_aa32, cpu); - } - - if (arm_feature(env, ARM_FEATURE_V7VE)) { - /* v7 Virtualization Extensions. In real hardware this implies - * EL2 and also the presence of the Security Extensions. - * For QEMU, for backwards-compatibility we implement some - * CPUs or CPU configs which have no actual EL2 or EL3 but do - * include the various other features that V7VE implies. - * Presence of EL2 itself is ARM_FEATURE_EL2, and of the - * Security Extensions is ARM_FEATURE_EL3. - */ - assert(!tcg_enabled() || no_aa32 || - cpu_isar_feature(aa32_arm_div, cpu)); - set_feature(env, ARM_FEATURE_LPAE); - set_feature(env, ARM_FEATURE_V7); - } - if (arm_feature(env, ARM_FEATURE_V7)) { - set_feature(env, ARM_FEATURE_VAPA); - set_feature(env, ARM_FEATURE_THUMB2); - set_feature(env, ARM_FEATURE_MPIDR); - if (!arm_feature(env, ARM_FEATURE_M)) { - set_feature(env, ARM_FEATURE_V6K); - } else { - set_feature(env, ARM_FEATURE_V6); - } - - /* Always define VBAR for V7 CPUs even if it doesn't exist in - * non-EL3 configs. This is needed by some legacy boards. - */ - set_feature(env, ARM_FEATURE_VBAR); - } - if (arm_feature(env, ARM_FEATURE_V6K)) { - set_feature(env, ARM_FEATURE_V6); - set_feature(env, ARM_FEATURE_MVFR); - } - if (arm_feature(env, ARM_FEATURE_V6)) { - set_feature(env, ARM_FEATURE_V5); - if (!arm_feature(env, ARM_FEATURE_M)) { - assert(!tcg_enabled() || no_aa32 || - cpu_isar_feature(aa32_jazelle, cpu)); - set_feature(env, ARM_FEATURE_AUXCR); - } - } - if (arm_feature(env, ARM_FEATURE_V5)) { - set_feature(env, ARM_FEATURE_V4T); - } - if (arm_feature(env, ARM_FEATURE_LPAE)) { - set_feature(env, ARM_FEATURE_V7MP); - } - if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { - set_feature(env, ARM_FEATURE_CBAR); - } - if (arm_feature(env, ARM_FEATURE_THUMB2) && - !arm_feature(env, ARM_FEATURE_M)) { - set_feature(env, ARM_FEATURE_THUMB_DSP); - } =20 /* * We rely on no XScale CPU having VFP so we can use the same bits in = the --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478844; cv=none; d=zohomail.com; s=zohoarc; b=E5ivmcpoYEP/4sTxNgOM/CcbUfd91nWQ+j2lXDBO3y9NHmjHyxtX40JiSqDp6WygY5uI9I/n84aXBUm2QqsiFtmN3q2LZjWp9/tk9ZD/4xTvnZGboNY0wfAZCo/zxLbtR9feC1vOE8kKIAtl02iVsjDeP9/807TeBMEqaVouOSs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478844; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7younOAESMSGZRgRGk0G3tpzN8Y0x16KvD+mTonKpbs=; b=MazE9v1nboTvYnwvnLOZKgFqFn1miqjTb5o/mf6zUnalwuA5C8AWS1LcqPMtKEGLf3EB60xNIXJKh1OejpG7RrvT08I3e1NmTuW89YjjVoFaiVpXBdC97Dsk64rS24RlY5aHeTbtF0T8kal6KdrQgi4bY1U70e/Eg7kM2mZ/47A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693478844647306.7535034509424; Thu, 31 Aug 2023 03:47:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbfBK-0003qj-3v; Thu, 31 Aug 2023 06:45:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbfBD-0003gT-96 for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:40 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbfB7-00045O-8x for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:37 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-401b5516104so5828945e9.2 for ; Thu, 31 Aug 2023 03:45:31 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478730; x=1694083530; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7younOAESMSGZRgRGk0G3tpzN8Y0x16KvD+mTonKpbs=; b=jIVKcokWZDG/z0njsF5GL2nenq/XvHilXAy+unwkzoROPmPtQ+1h7mCI8pwQF4I3Ai Y8TVcEtqhHHRjpiYGFt9ze0rQV5j0GUrADgSdcwJl6DGcA22dvzpCODzzm5YvFhhyw7v pTpsy8vNG8BEJo64MLhac2KBJTsUsFsUPQZy+QFr5+iSSQ/LfaqoLvv+tjM81WG5zUmq NGphtBt3U1Vh3HkhlaN8osWmW+1wS+3NMTWl3W2sExyvUFGUqtq9IEm1ZTjshw8izXeV HX2NhQllfjSqXVXgg692HEi2KXz/RssTDw0UA61/rsPoY/gs65vY2tTn7RGzx+lOuGeg W6Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478730; x=1694083530; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7younOAESMSGZRgRGk0G3tpzN8Y0x16KvD+mTonKpbs=; b=dz+iMM9HRgAnemk3QCqTEL5mVxBcTDjsgXf1j8PbxldaP49cXfAf2P+yKvp1yOR+B6 fMMpybahudhNtq9KkOg5p1NJe0Dy5FPL7ruEQwsABjQWmLe9defORDzXwW6usZbtfDNa g1teX2woKUwNJ56bk66hkRdtoiaq7jgtsG/telBo96vudCgyKyvfJTyAVXTIkSrhhOy1 PHDv0mlABrU2SjBeeDZVeSZj3Jz6axHGhH2h/aKMmGnnyXKbUTG2apEBAWYHZQu6NhWY E/o4eBf0WaJEPESUv1xXcWelDZv4XJbM8k59Jb4wdgu9sWD3MJS7fwfrFklyRtY3J5/k 7AKA== X-Gm-Message-State: AOJu0YySniL32OKG4Pel2Jy+uOCkUyVEC91W88+6Y8i00kgVineHpSXx bjYuciAcdMQjmBasafkTwbS5u2B/gUuoLhoO8RE= X-Google-Smtp-Source: AGHT+IEV7dtCNFR8xICoW/KiZGwQqNVfi1UEgLj4lV1puSY4Ivsvtz1h8qZhZPweNdy4QVESZ7OzOA== X-Received: by 2002:a05:600c:3655:b0:401:b3a5:ec03 with SMTP id y21-20020a05600c365500b00401b3a5ec03mr3740108wmq.1.1693478730639; Thu, 31 Aug 2023 03:45:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/24] hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties Date: Thu, 31 Aug 2023 11:45:18 +0100 Message-Id: <20230831104519.3520658-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478845184100001 M-profile CPUs generally allow configuration of the number of MPU regions that they have. We don't currently model this, so our implementations of some of the board models provide CPUs with the wrong number of regions. RTOSes like Zephyr that hardcode the expected number of regions may therefore not run on the model if they are set up to run on real hardware. Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object, matching the ability of hardware to configure the number of Secure and NonSecure regions separately. Our actual CPU implementation doesn't currently support that, and it happens that none of the MPS boards we model set the number of regions differently for Secure vs NonSecure, so we provide an interface to the boards and SoCs that won't need to change if we ever do add that functionality in future, but make it an error to configure the two properties to different values. (The property name on the CPU is the somewhat misnamed-for-M-profile "pmsav7-dregion", so we don't follow that naming convention for the properties here. The TRM doesn't say what the CPU configuration variable names are, so we pick something, and follow the lowercase convention we already have for properties here.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org --- include/hw/arm/armv7m.h | 8 ++++++++ hw/arm/armv7m.c | 21 +++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index b7ba0ff409c..e2cebbd15c0 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -52,6 +52,12 @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M) * + Property "vfp": enable VFP (forwarded to CPU object) * + Property "dsp": enable DSP (forwarded to CPU object) * + Property "enable-bitband": expose bitbanded IO + * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded + * to CPU object pmsav7-dregion property; default is whatever the default + * for the CPU is) + * + Property "mpu-s-regions": number of Secure MPU regions (default is + * whatever the default for the CPU is; must currently be set to the same + * value as mpu-ns-regions if the CPU implements the Security Extension) * + Clock input "refclk" is the external reference clock for the systick = timers * + Clock input "cpuclk" is the main CPU clock */ @@ -95,6 +101,8 @@ struct ARMv7MState { Object *idau; uint32_t init_svtor; uint32_t init_nsvtor; + uint32_t mpu_ns_regions; + uint32_t mpu_s_regions; bool enable_bitband; bool start_powered_off; bool vfp; diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 50a9507c0bd..bf173b10b8b 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -334,6 +334,25 @@ static void armv7m_realize(DeviceState *dev, Error **e= rrp) } } =20 + /* + * Real M-profile hardware can be configured with a different number of + * MPU regions for Secure vs NonSecure. QEMU's CPU implementation does= n't + * support that yet, so catch attempts to select that. + */ + if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) && + s->mpu_ns_regions !=3D s->mpu_s_regions) { + error_setg(errp, + "mpu-ns-regions and mpu-s-regions properties must have = the same value"); + return; + } + if (s->mpu_ns_regions !=3D UINT_MAX && + object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) { + if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion", + s->mpu_ns_regions, errp)) { + return; + } + } + /* * Tell the CPU where the NVIC is; it will fail realize if it doesn't * have one. Similarly, tell the NVIC where its CPU is. @@ -530,6 +549,8 @@ static Property armv7m_properties[] =3D { false), DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true), DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true), + DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT= _MAX), + DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_M= AX), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.34.1 From nobody Wed May 15 20:45:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1693478827; cv=none; d=zohomail.com; s=zohoarc; b=baAuZxiY6HnsaXw0+O4hN6xeaBV3yKKlF03fwXoZxJvneov0kYeR3ce1rZkcsZo7A+zpFTn+/xlzZt65YNj07kTQrb6SOgY4XZECSLYU85d5tS0nCJ6/PW3TwUQeCYsOAiVX42PGKYs4Bxn8HwI2tPTTQt76LAj2RqtYbUTpx2Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693478827; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MG1KyDGSN+GXNuzLteqYg7H3jegBOGlvPOi05Ssbk0w=; b=nEw2BIcvU5LxPZufFo8SL1ii8Kn2ccoQEVnbyT5PbDgcZUWoluLiSTl0uXL921bHGtGGaM2LYHg8NUdxunuGlNEewIk35qtJ0MVSp9TBqx8aGKxtPCqJvbMbF6cMs5ZmbWfJI1wTLxrNDxhR9UcrBwb7G2frCeWTeiw1ONS9GZs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1693478827731547.8587684981306; Thu, 31 Aug 2023 03:47:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qbfBJ-0003ob-Bk; Thu, 31 Aug 2023 06:45:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qbfBB-0003dm-Fi for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:37 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qbfB7-00045Z-8d for qemu-devel@nongnu.org; Thu, 31 Aug 2023 06:45:37 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-4013454fa93so6503665e9.0 for ; Thu, 31 Aug 2023 03:45:31 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b0031c71693449sm1785524wrm.1.2023.08.31.03.45.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 03:45:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693478731; x=1694083531; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=MG1KyDGSN+GXNuzLteqYg7H3jegBOGlvPOi05Ssbk0w=; b=Q1lnGi2qVOZU6hiQ5R5p7yUiXmhA8tpZvDcgcJ9IcXHN70qsR8nBs4aSrprinGu2R9 A1+7OOLfq7SZ/WY0TG2tDGMIwBCGZkZf/hDdHFPNFSdaPuY7HPY94yV2DFDJQ3subb7V 2DvHErNG0HxCBlVuCi64ALh5e1gqD91gGZzqCZlsCBxiuZ6yULRt884XuzYKW86KjvFm iRAhByX4Mh6W0qkG3s3zsmjSY+AGNfOz6BHuD+y0+lajAlNGiXP7DSTwXuGFV7Tx0S7P IEWgxlsrmh0m5CTATiA/uEPpBdM8IVaZSR1AJ6VOKNZocyFCCGmrH+Uk6PM5eV2gyTT9 4Xow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693478731; x=1694083531; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MG1KyDGSN+GXNuzLteqYg7H3jegBOGlvPOi05Ssbk0w=; b=LLa08Zp5s82Hq4XUCHh8sb/7merZKYc85BSPhUsElxwxjHd2AICoR8rp1KCWZSOLYW T+ZLjlgU7+UGLASKlzAzh3gt42wi7zKq331iQT6UjiCHqZyVKen2BY6PeJ+A1PdyC0Lu dnoA1erNLMkoepJMjOHicdSzjEhzRKmD7IKUeyhnyR3OAy28lNS5kogSMRy7eB0OIgCU Hat2WliyN8WlRVMeFimFWhv8QvE+prdUcvPDTgOBY9fPuYvbSA1S6VBJmFgH6s1KP02G PIYGrZIoz0vkfEVgzlB5HPBLjecK9HB0pYl1DrcP9O//+a4zZIs+ZjVgYN9hK3B5XSyU IEGA== X-Gm-Message-State: AOJu0YwlTAbGqTL3pna8NbCI6hXmljGfPMLrzNR8izKEGjs1F9vmiPCy bHav/D0zdHvaqnn4YJRk3b/2hGwnk0FTFAyPqJ0= X-Google-Smtp-Source: AGHT+IH7W301RL7stZTnExPnBplIPVR9kV4BZPLUJaNZIUZ7x+pjKppqyf6ESuj5okpYmgXTWY+nsw== X-Received: by 2002:a5d:65c8:0:b0:314:1560:cc68 with SMTP id e8-20020a5d65c8000000b003141560cc68mr3436441wrw.56.1693478731021; Thu, 31 Aug 2023 03:45:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/24] hw/arm: Set number of MPU regions correctly for an505, an521, an524 Date: Thu, 31 Aug 2023 11:45:19 +0100 Message-Id: <20230831104519.3520658-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831104519.3520658-1-peter.maydell@linaro.org> References: <20230831104519.3520658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693478828906100001 The IoTKit, SSE200 and SSE300 all default to 8 MPU regions. The MPS2/MPS3 FPGA images don't override these except in the case of AN547, which uses 16 MPU regions. Define properties on the ARMSSE object for the MPU regions (using the same names as the documented RTL configuration settings, and following the pattern we already have for this device of using all-caps names as the RTL does), and set them in the board code. We don't actually need to override the default except on AN547, but it's simpler code to have the board code set them always rather than tracking which board subtypes want to set them to a non-default value separately from what that value is. Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524 we now correctly use 8 MPU regions, while mps3-an547 stays at its current 16 regions. It's possible some guest code wrongly depended on the previous incorrectly modeled number of memory regions. (Such guest code should ideally check the number of regions via the MPU_TYPE register.) The old behaviour can be obtained with additional -global arguments to QEMU: For mps2-an521 and mps2-an524: -global sse-200.CPU0_MPU_NS=3D16 -global sse-200.CPU0_MPU_S=3D16 -global s= se-200.CPU1_MPU_NS=3D16 -global sse-200.CPU1_MPU_S=3D16 For mps2-an505: -global sse-200.CPU0_MPU_NS=3D16 -global sse-200.CPU0_MPU_S=3D16 NB that the way the implementation allows this use of -global is slightly fragile: if the board code explicitly sets the properties on the sse-200 object, this overrides the -global command line option. So we rely on: - the boards that need fixing all happen to use the SSE defaults - we can write the board code to only set the property if it is different from the default, rather than having all boards explicitly set the property - the board that does need to use a non-default value happens to need to set it to the same value (16) we previously used This works, but there are some kinds of refactoring of the mps2-tz.c code that would break the support for -global here. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 5 +++++ hw/arm/armsse.c | 16 ++++++++++++++++ hw/arm/mps2-tz.c | 29 +++++++++++++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index cd0931d0a0b..88b3b759c5a 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -56,6 +56,9 @@ * (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an * SSE-200 both are present; CPU0 in an SSE-200 has neither. * Since the IoTKit has only one CPU, it does not have the CPU1_* prope= rties. + * + QOM properties "CPU0_MPU_NS", "CPU0_MPU_S", "CPU1_MPU_NS" and "CPU1_= MPU_S" + * which set the number of MPU regions on the CPUs. If there is only one + * CPU the CPU1 properties are not present. * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CP= U 0, * which are wired to its NVIC lines 32 .. n+32 * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts f= or @@ -221,6 +224,8 @@ struct ARMSSE { uint32_t exp_numirq; uint32_t sram_addr_width; uint32_t init_svtor; + uint32_t cpu_mpu_ns[SSE_MAX_CPUS]; + uint32_t cpu_mpu_s[SSE_MAX_CPUS]; bool cpu_fpu[SSE_MAX_CPUS]; bool cpu_dsp[SSE_MAX_CPUS]; }; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 0202bad787b..11cd08b6c1e 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -85,6 +85,8 @@ static Property iotkit_properties[] =3D { DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), + DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), + DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), DEFINE_PROP_END_OF_LIST() }; =20 @@ -98,6 +100,10 @@ static Property sse200_properties[] =3D { DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true), DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true), + DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), + DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), + DEFINE_PROP_UINT32("CPU1_MPU_NS", ARMSSE, cpu_mpu_ns[1], 8), + DEFINE_PROP_UINT32("CPU1_MPU_S", ARMSSE, cpu_mpu_s[1], 8), DEFINE_PROP_END_OF_LIST() }; =20 @@ -109,6 +115,8 @@ static Property sse300_properties[] =3D { DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), + DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), + DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), DEFINE_PROP_END_OF_LIST() }; =20 @@ -1029,6 +1037,14 @@ static void armsse_realize(DeviceState *dev, Error *= *errp) return; } } + if (!object_property_set_uint(cpuobj, "mpu-ns-regions", + s->cpu_mpu_ns[i], errp)) { + return; + } + if (!object_property_set_uint(cpuobj, "mpu-s-regions", + s->cpu_mpu_s[i], errp)) { + return; + } =20 if (i > 0) { memory_region_add_subregion_overlap(&s->cpu_container[i], 0, diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 58731073020..eae3639da23 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -124,6 +124,10 @@ struct MPS2TZMachineClass { int uart_overflow_irq; /* number of the combined UART overflow IRQ */ uint32_t init_svtor; /* init-svtor setting for SSE */ uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */ + uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */ + uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */ + uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */ + uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */ const RAMInfo *raminfo; const char *armsse_type; uint32_t boot_ram_size; /* size of ram at address 0; 0 =3D=3D find in = raminfo */ @@ -183,6 +187,9 @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineCl= ass, MPS2TZ_MACHINE) #define MPS3_DDR_SIZE (2 * GiB) #endif =20 +/* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */ +#define MPU_REGION_DEFAULT UINT32_MAX + static const uint32_t an505_oscclk[] =3D { 40000000, 24580000, @@ -828,6 +835,20 @@ static void mps2tz_common_init(MachineState *machine) OBJECT(system_memory), &error_abort); qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor); + if (mmc->cpu0_mpu_ns !=3D MPU_REGION_DEFAULT) { + qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns); + } + if (mmc->cpu0_mpu_s !=3D MPU_REGION_DEFAULT) { + qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s); + } + if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) { + if (mmc->cpu1_mpu_ns !=3D MPU_REGION_DEFAULT) { + qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_n= s); + } + if (mmc->cpu1_mpu_s !=3D MPU_REGION_DEFAULT) { + qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s); + } + } qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_widt= h); qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); @@ -1256,10 +1277,17 @@ static void mps2tz_class_init(ObjectClass *oc, void= *data) { MachineClass *mc =3D MACHINE_CLASS(oc); IDAUInterfaceClass *iic =3D IDAU_INTERFACE_CLASS(oc); + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_CLASS(oc); =20 mc->init =3D mps2tz_common_init; mc->reset =3D mps2_machine_reset; iic->check =3D mps2_tz_idau_check; + + /* Most machines leave these at the SSE defaults */ + mmc->cpu0_mpu_ns =3D MPU_REGION_DEFAULT; + mmc->cpu0_mpu_s =3D MPU_REGION_DEFAULT; + mmc->cpu1_mpu_ns =3D MPU_REGION_DEFAULT; + mmc->cpu1_mpu_s =3D MPU_REGION_DEFAULT; } =20 static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc) @@ -1396,6 +1424,7 @@ static void mps3tz_an547_class_init(ObjectClass *oc, = void *data) mmc->numirq =3D 96; mmc->uart_overflow_irq =3D 48; mmc->init_svtor =3D 0x00000000; + mmc->cpu0_mpu_s =3D mmc->cpu0_mpu_ns =3D 16; mmc->sram_addr_width =3D 21; mmc->raminfo =3D an547_raminfo; mmc->armsse_type =3D TYPE_SSE300; --=20 2.34.1