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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id 4-20020a17090a190400b002680dfd368dsm7932835pjg.51.2023.08.28.11.55.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Aug 2023 11:55:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693248955; x=1693853755; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PXC5tTcUi0lmpfhMw90VKckGWB1iYRWY7/22QuukN5Y=; b=Kd1cLMLDbJlPQlmcLcuLYjtkG7ROMUJoSVcjc1Y2yY5ZivWdgP8FQHmF9bOonW8V/I J3mTuwSYQdYiU0uXQ9XowQI1ar6WrwLCtrAW/HJhlfEqfsCyB8QKztt7fnuoKYgDDs/O nq7jao+hCs/DKd4gHQosqLRrouZHv5QzCJNf3Rh90S8kAxXBLNg1gV0k9rGpYBzVBQWZ RQfvulioYJmPjzISsCbsKxhYgwofAgx5wfKRNxwEW3KYhqXB1iUhmoD+/FATUmHYvFYb MPFdODnk+sJO841ANvbNzh0EgbQACY1Pfi5c7BnCFT1SdTqWjzKXGF4Up9M8qQgkMxAZ 0MRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693248955; x=1693853755; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PXC5tTcUi0lmpfhMw90VKckGWB1iYRWY7/22QuukN5Y=; b=XV7TAwt8+0WYiha2uY8rSibtFhaQ3P2ALFGZs05gRkqOVyd8igikFvt9Uxj2j/RjM0 tscKccj+TWp8iWtHXWzlHxYssyxNGIwHp9O+sGi2liACoLixtro6ujJ4KKD+dxBjzu61 rgTp77EzZ9Mx1HNACDsJra37DzCNNEpkJawDxDC9OGGYh18v9dPZnR9QUoTCNzF/ofJj 0P7J8di2lLj8YKh4CbyaphwAosyQ8aWGCZx8WYAZRROoQORgt5NaoOG5DGHvy9uoX/tw VoV4j3iLy436jo28rX8yz0KPxtqChNnAwCQWYVX//OWFr9aajz0MqsXvcSFrABR8sF5a ZzJQ== X-Gm-Message-State: AOJu0Ywf7/Nml3O7ZqL4TvGrhPswdif5Y19EMHESyGBHY/pfkLOCkYMB rOh7VVBMs6ZFqcTOWN8nS4YfmzaSh56oV8sQU8o= X-Google-Smtp-Source: AGHT+IGgaSz+6lEpxa/DVXUokG50CdASoPWkhsEva/eVzM8g5bSfCuArgQo/dmi7sAPc+LTiAVBCyg== X-Received: by 2002:a17:90a:2f47:b0:268:fc26:73a9 with SMTP id s65-20020a17090a2f4700b00268fc2673a9mr19645961pjd.40.1693248955001; Mon, 28 Aug 2023 11:55:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org Subject: [PATCH 03/10] accel/tcg: Use CPUTLBEntryFull.phys_addr in io_failed Date: Mon, 28 Aug 2023 11:55:43 -0700 Message-Id: <20230828185550.573653-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230828185550.573653-1-richard.henderson@linaro.org> References: <20230828185550.573653-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693249085071100001 Content-Type: text/plain; charset="utf-8" Since the introduction of CPUTLBEntryFull, we can recover the full cpu address space physical address without having to examine the MemoryRegionSection. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/cputlb.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 17987f74e5..fd6c956214 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1385,13 +1385,9 @@ io_prepare(hwaddr *out_offset, CPUArchState *env, hw= addr xlat, =20 static void io_failed(CPUArchState *env, CPUTLBEntryFull *full, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_id= x, - MemTxResult response, uintptr_t retaddr, - MemoryRegionSection *section, hwaddr mr_offset) + MemTxResult response, uintptr_t retaddr) { - hwaddr physaddr =3D (mr_offset + - section->offset_within_address_space - - section->offset_within_region); - + hwaddr physaddr =3D full->phys_addr | (addr & ~TARGET_PAGE_MASK); cpu_transaction_failed(env_cpu(env), physaddr, addr, size, access_type, mmu_idx, full->attrs, response, retaddr); } @@ -1417,7 +1413,7 @@ static uint64_t io_readx(CPUArchState *env, CPUTLBEnt= ryFull *full, =20 if (r !=3D MEMTX_OK) { io_failed(env, full, addr, memop_size(op), access_type, mmu_idx, - r, retaddr, section, mr_offset); + r, retaddr); } return val; } @@ -1442,7 +1438,7 @@ static void io_writex(CPUArchState *env, CPUTLBEntryF= ull *full, =20 if (r !=3D MEMTX_OK) { io_failed(env, full, addr, memop_size(op), MMU_DATA_STORE, mmu_idx, - r, retaddr, section, mr_offset); + r, retaddr); } } =20 --=20 2.34.1