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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id 4-20020a17090a190400b002680dfd368dsm7932835pjg.51.2023.08.28.11.55.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Aug 2023 11:55:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693248954; x=1693853754; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7K3agjAj/5Z9V2az8Pltf/TZABQcnS/GDuSWWPrto4M=; b=FdiXYEtAuIOeWw0FEEU4pTlgXX6bL0Bucwv+mbpNY3N7olA45QBU3ycKPPhDlTqKYL +LUCx6C2CRvewBDUnNccnmTafAnasLzTlyz6rGxRszJ52N/hZVE/GdPei/MhACYKPyst NqFbMUI6nJXf21SaZO7UtZVBkiIeSQDpTfuwenfPw442F4NsV8J3euXN6oUYkfIm9ykA JJOahdO0azAo75+T21ikOUxPBKx+/xwLfusSDYjyvG4U7iB38fwPBSn3wUbi//JB9tqk 2Zxytxxyw8bB2kyOklbhhsVU0zoheysg9hCGX7rnfjL3fwj21k3blKQungl6rA9ywk4q mWKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693248954; x=1693853754; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7K3agjAj/5Z9V2az8Pltf/TZABQcnS/GDuSWWPrto4M=; b=LVYMT0Me/Vc/0mDtZTs1Y1ojVZ9hu9Hmo81x/C34ngbnLi/MNG6/m2tZKFH06EG5e2 pInovv97vIr+v7sXKcxFd9K2OIMSpnqt6oiSvi3lnjVigzFgKwcbBFxjqsuFp9KmD5N/ BYzbyIi22gQeJPCkluJhI+ZGR7JGPmzdP84FP8pcLQx2sKot1UREieif7Bln5aoNaGnd vveZXjJAKtbt2yGcka1NB7wPXm3phEF+891mebsTSAAgEWXUTTCauncNumUlrnqPEu90 r7VVMY57hEAQwRn6HYXgDYSAExub1VCgYt/fdhJsfXDmO0DLsRcRHp2s4IsTqGDH+4KC 9WLg== X-Gm-Message-State: AOJu0YxCkqMsVQrvIrIZZVa0CQgm8sPrVU2WKK17jYFKG/OHC9B3i/lR NBJEoXK7/wdqgNt8xWmUXPFNeSPjf6nqiugNNqQ= X-Google-Smtp-Source: AGHT+IFNQcdw+N0i3wGp7ws/X/WbgJBPFV9FeL0ytDt+qIUzIsIXP2dXFP4M0QNr39+a79IdQPPBzg== X-Received: by 2002:a05:6870:4706:b0:1c8:bfd1:ecc0 with SMTP id b6-20020a056870470600b001c8bfd1ecc0mr12897140oaq.0.1693248954008; Mon, 28 Aug 2023 11:55:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org Subject: [PATCH 02/10] accel/tcg: Split out io_prepare and io_failed Date: Mon, 28 Aug 2023 11:55:42 -0700 Message-Id: <20230828185550.573653-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230828185550.573653-1-richard.henderson@linaro.org> References: <20230828185550.573653-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2b; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1693249021676100001 Content-Type: text/plain; charset="utf-8" These are common code from io_readx and io_writex. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/cputlb.c | 77 +++++++++++++++++++++++++++------------------- 1 file changed, 45 insertions(+), 32 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index fcf6ccebff..17987f74e5 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1264,7 +1264,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, * (non-page-aligned) vaddr of the eventual memory access to get * the MemoryRegion offset for the access. Note that the vaddr we * subtract here is that of the page base, and not the same as the - * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). + * vaddr we add back in io_prepare()/get_page_addr_code(). */ desc->fulltlb[index] =3D *full; full =3D &desc->fulltlb[index]; @@ -1364,37 +1364,60 @@ static inline void cpu_transaction_failed(CPUState = *cpu, hwaddr physaddr, } } =20 -static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full, - int mmu_idx, vaddr addr, uintptr_t retaddr, - MMUAccessType access_type, MemOp op) +static MemoryRegionSection * +io_prepare(hwaddr *out_offset, CPUArchState *env, hwaddr xlat, + MemTxAttrs attrs, vaddr addr, uintptr_t retaddr) { CPUState *cpu =3D env_cpu(env); - hwaddr mr_offset; MemoryRegionSection *section; - MemoryRegion *mr; - uint64_t val; - MemTxResult r; + hwaddr mr_offset; =20 - section =3D iotlb_to_section(cpu, full->xlat_section, full->attrs); - mr =3D section->mr; - mr_offset =3D (full->xlat_section & TARGET_PAGE_MASK) + addr; + section =3D iotlb_to_section(cpu, xlat, attrs); + mr_offset =3D (xlat & TARGET_PAGE_MASK) + addr; cpu->mem_io_pc =3D retaddr; if (!cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); } =20 + *out_offset =3D mr_offset; + return section; +} + +static void io_failed(CPUArchState *env, CPUTLBEntryFull *full, vaddr addr, + unsigned size, MMUAccessType access_type, int mmu_id= x, + MemTxResult response, uintptr_t retaddr, + MemoryRegionSection *section, hwaddr mr_offset) +{ + hwaddr physaddr =3D (mr_offset + + section->offset_within_address_space - + section->offset_within_region); + + cpu_transaction_failed(env_cpu(env), physaddr, addr, size, access_type, + mmu_idx, full->attrs, response, retaddr); +} + +static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full, + int mmu_idx, vaddr addr, uintptr_t retaddr, + MMUAccessType access_type, MemOp op) +{ + MemoryRegionSection *section; + hwaddr mr_offset; + MemoryRegion *mr; + MemTxResult r; + uint64_t val; + + section =3D io_prepare(&mr_offset, env, full->xlat_section, + full->attrs, addr, retaddr); + mr =3D section->mr; + { QEMU_IOTHREAD_LOCK_GUARD(); r =3D memory_region_dispatch_read(mr, mr_offset, &val, op, full->a= ttrs); } =20 if (r !=3D MEMTX_OK) { - hwaddr physaddr =3D mr_offset + - section->offset_within_address_space - - section->offset_within_region; - - cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), access= _type, - mmu_idx, full->attrs, r, retaddr); + io_failed(env, full, addr, memop_size(op), access_type, mmu_idx, + r, retaddr, section, mr_offset); } return val; } @@ -1403,19 +1426,14 @@ static void io_writex(CPUArchState *env, CPUTLBEntr= yFull *full, int mmu_idx, uint64_t val, vaddr addr, uintptr_t retaddr, MemOp op) { - CPUState *cpu =3D env_cpu(env); - hwaddr mr_offset; MemoryRegionSection *section; + hwaddr mr_offset; MemoryRegion *mr; MemTxResult r; =20 - section =3D iotlb_to_section(cpu, full->xlat_section, full->attrs); + section =3D io_prepare(&mr_offset, env, full->xlat_section, + full->attrs, addr, retaddr); mr =3D section->mr; - mr_offset =3D (full->xlat_section & TARGET_PAGE_MASK) + addr; - if (!cpu->can_do_io) { - cpu_io_recompile(cpu, retaddr); - } - cpu->mem_io_pc =3D retaddr; =20 { QEMU_IOTHREAD_LOCK_GUARD(); @@ -1423,13 +1441,8 @@ static void io_writex(CPUArchState *env, CPUTLBEntry= Full *full, } =20 if (r !=3D MEMTX_OK) { - hwaddr physaddr =3D mr_offset + - section->offset_within_address_space - - section->offset_within_region; - - cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), - MMU_DATA_STORE, mmu_idx, full->attrs, r, - retaddr); + io_failed(env, full, addr, memop_size(op), MMU_DATA_STORE, mmu_idx, + r, retaddr, section, mr_offset); } } =20 --=20 2.34.1