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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 35/35] target/arm: Fix 64-bit SSRA
Date: Thu, 24 Aug 2023 10:28:36 +0100
Message-Id: <20230824092836.2239644-36-peter.maydell@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
Typo applied byte-wise shift instead of double-word shift.
Cc: qemu-stable@nongnu.org
Fixes: 631e565450c ("target/arm: Create gen_gvec_[us]sra")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1737
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Message-id: 20230821022025.397682-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index b71ac2d0d53..39541ecdf0a 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -3053,7 +3053,7 @@ void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, ui=
nt32_t rm_ofs,
.vece =3D MO_32 },
{ .fni8 =3D gen_ssra64_i64,
.fniv =3D gen_ssra_vec,
- .fno =3D gen_helper_gvec_ssra_b,
+ .fno =3D gen_helper_gvec_ssra_d,
.prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64,
.opt_opc =3D vecop_list,
.load_dest =3D true,
--=20
2.34.1