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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 32/35] target/arm/helper: Check SCR_EL3.{NSE,
NS} encoding for AT instructions
Date: Thu, 24 Aug 2023 10:28:33 +0100
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From: Jean-Philippe Brucker <jean-philippe@linaro.org>
The AT instruction is UNDEFINED if the {NSE,NS} configuration is
invalid. Add a function to check this on all AT instructions that apply
to an EL lower than 3.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230809123706.1842548-6-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 38 +++++++++++++++++++++++++++-----------
1 file changed, 27 insertions(+), 11 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index de639d40871..b4618ee2b95 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3616,6 +3616,22 @@ static void ats1h_write(CPUARMState *env, const ARMC=
PRegInfo *ri,
#endif /* CONFIG_TCG */
}
=20
+static CPAccessResult at_e012_access(CPUARMState *env, const ARMCPRegInfo =
*ri,
+ bool isread)
+{
+ /*
+ * R_NYXTL: instruction is UNDEFINED if it applies to an Exception lev=
el
+ * lower than EL3 and the combination SCR_EL3.{NSE,NS} is reserved. Th=
is can
+ * only happen when executing at EL3 because that combination also cau=
ses an
+ * illegal exception return. We don't need to check FEAT_RME either, b=
ecause
+ * scr_write() ensures that the NSE bit is not set otherwise.
+ */
+ if ((env->cp15.scr_el3 & (SCR_NSE | SCR_NS)) =3D=3D SCR_NSE) {
+ return CP_ACCESS_TRAP;
+ }
+ return CP_ACCESS_OK;
+}
+
static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo =
*ri,
bool isread)
{
@@ -3623,7 +3639,7 @@ static CPAccessResult at_s1e2_access(CPUARMState *env=
, const ARMCPRegInfo *ri,
!(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) {
return CP_ACCESS_TRAP;
}
- return CP_ACCESS_OK;
+ return at_e012_access(env, ri, isread);
}
=20
static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -5505,38 +5521,38 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D {
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 0,
.access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
.fgt =3D FGT_ATS1E1R,
- .writefn =3D ats_write64 },
+ .accessfn =3D at_e012_access, .writefn =3D ats_write64 },
{ .name =3D "AT_S1E1W", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 1,
.access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
.fgt =3D FGT_ATS1E1W,
- .writefn =3D ats_write64 },
+ .accessfn =3D at_e012_access, .writefn =3D ats_write64 },
{ .name =3D "AT_S1E0R", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 2,
.access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
.fgt =3D FGT_ATS1E0R,
- .writefn =3D ats_write64 },
+ .accessfn =3D at_e012_access, .writefn =3D ats_write64 },
{ .name =3D "AT_S1E0W", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 3,
.access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
.fgt =3D FGT_ATS1E0W,
- .writefn =3D ats_write64 },
+ .accessfn =3D at_e012_access, .writefn =3D ats_write64 },
{ .name =3D "AT_S12E1R", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 4,
.access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
- .writefn =3D ats_write64 },
+ .accessfn =3D at_e012_access, .writefn =3D ats_write64 },
{ .name =3D "AT_S12E1W", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 5,
.access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
- .writefn =3D ats_write64 },
+ .accessfn =3D at_e012_access, .writefn =3D ats_write64 },
{ .name =3D "AT_S12E0R", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 6,
.access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
- .writefn =3D ats_write64 },
+ .accessfn =3D at_e012_access, .writefn =3D ats_write64 },
{ .name =3D "AT_S12E0W", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 7,
.access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
- .writefn =3D ats_write64 },
+ .accessfn =3D at_e012_access, .writefn =3D ats_write64 },
/* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present=
*/
{ .name =3D "AT_S1E3R", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 8, .opc2 =3D 0,
@@ -8079,12 +8095,12 @@ static const ARMCPRegInfo ats1e1_reginfo[] =3D {
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0,
.access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
.fgt =3D FGT_ATS1E1RP,
- .writefn =3D ats_write64 },
+ .accessfn =3D at_e012_access, .writefn =3D ats_write64 },
{ .name =3D "AT_S1E1WP", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1,
.access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
.fgt =3D FGT_ATS1E1WP,
- .writefn =3D ats_write64 },
+ .accessfn =3D at_e012_access, .writefn =3D ats_write64 },
};
=20
static const ARMCPRegInfo ats1cp_reginfo[] =3D {
--=20
2.34.1