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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 31/35] target/arm: Pass security space rather than flag for AT
instructions
Date: Thu, 24 Aug 2023 10:28:32 +0100
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From: Jean-Philippe Brucker <jean-philippe@linaro.org>
At the moment we only handle Secure and Nonsecure security spaces for
the AT instructions. Add support for Realm and Root.
For AArch64, arm_security_space() gives the desired space. ARM DDI0487J
says (R_NYXTL):
If EL3 is implemented, then when an address translation instruction
that applies to an Exception level lower than EL3 is executed, the
Effective value of SCR_EL3.{NSE, NS} determines the target Security
state that the instruction applies to.
For AArch32, some instructions can access NonSecure space from Secure,
so we still need to pass the state explicitly to do_ats_write().
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230809123706.1842548-5-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/internals.h | 18 +++++++++---------
target/arm/helper.c | 27 ++++++++++++---------------
target/arm/ptw.c | 12 ++++++------
3 files changed, 27 insertions(+), 30 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index fc90c364f77..cf13bb94f59 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1217,24 +1217,24 @@ bool get_phys_addr(CPUARMState *env, target_ulong a=
ddress,
__attribute__((nonnull));
=20
/**
- * get_phys_addr_with_secure_nogpc: get the physical address for a virtual
- * address
+ * get_phys_addr_with_space_nogpc: get the physical address for a virtual
+ * address
* @env: CPUARMState
* @address: virtual address to get physical address for
* @access_type: 0 for read, 1 for write, 2 for execute
* @mmu_idx: MMU index indicating required translation regime
- * @is_secure: security state for the access
+ * @space: security space for the access
* @result: set on translation success.
* @fi: set to fault info if the translation fails
*
- * Similar to get_phys_addr, but use the given security regime and don't p=
erform
+ * Similar to get_phys_addr, but use the given security space and don't pe=
rform
* a Granule Protection Check on the resulting address.
*/
-bool get_phys_addr_with_secure_nogpc(CPUARMState *env, target_ulong addres=
s,
- MMUAccessType access_type,
- ARMMMUIdx mmu_idx, bool is_secure,
- GetPhysAddrResult *result,
- ARMMMUFaultInfo *fi)
+bool get_phys_addr_with_space_nogpc(CPUARMState *env, target_ulong address,
+ MMUAccessType access_type,
+ ARMMMUIdx mmu_idx, ARMSecuritySpace sp=
ace,
+ GetPhysAddrResult *result,
+ ARMMMUFaultInfo *fi)
__attribute__((nonnull));
=20
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e8a232a1f89..de639d40871 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3357,7 +3357,7 @@ static int par_el1_shareability(GetPhysAddrResult *re=
s)
=20
static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- bool is_secure)
+ ARMSecuritySpace ss)
{
bool ret;
uint64_t par64;
@@ -3369,8 +3369,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64=
_t value,
* I_MXTJT: Granule protection checks are not performed on the final a=
ddress
* of a successful translation.
*/
- ret =3D get_phys_addr_with_secure_nogpc(env, value, access_type, mmu_i=
dx,
- is_secure, &res, &fi);
+ ret =3D get_phys_addr_with_space_nogpc(env, value, access_type, mmu_id=
x, ss,
+ &res, &fi);
=20
/*
* ATS operations only do S1 or S1+S2 translations, so we never
@@ -3535,7 +3535,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe=
gInfo *ri, uint64_t value)
uint64_t par64;
ARMMMUIdx mmu_idx;
int el =3D arm_current_el(env);
- bool secure =3D arm_is_secure_below_el3(env);
+ ARMSecuritySpace ss =3D arm_security_space(env);
=20
switch (ri->opc2 & 6) {
case 0:
@@ -3543,10 +3543,9 @@ static void ats_write(CPUARMState *env, const ARMCPR=
egInfo *ri, uint64_t value)
switch (el) {
case 3:
mmu_idx =3D ARMMMUIdx_E3;
- secure =3D true;
break;
case 2:
- g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */
+ g_assert(ss !=3D ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit o=
nly */
/* fall through */
case 1:
if (ri->crm =3D=3D 9 && (env->uncached_cpsr & CPSR_PAN)) {
@@ -3564,10 +3563,9 @@ static void ats_write(CPUARMState *env, const ARMCPR=
egInfo *ri, uint64_t value)
switch (el) {
case 3:
mmu_idx =3D ARMMMUIdx_E10_0;
- secure =3D true;
break;
case 2:
- g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */
+ g_assert(ss !=3D ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit o=
nly */
mmu_idx =3D ARMMMUIdx_Stage1_E0;
break;
case 1:
@@ -3580,18 +3578,18 @@ static void ats_write(CPUARMState *env, const ARMCP=
RegInfo *ri, uint64_t value)
case 4:
/* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
mmu_idx =3D ARMMMUIdx_E10_1;
- secure =3D false;
+ ss =3D ARMSS_NonSecure;
break;
case 6:
/* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
mmu_idx =3D ARMMMUIdx_E10_0;
- secure =3D false;
+ ss =3D ARMSS_NonSecure;
break;
default:
g_assert_not_reached();
}
=20
- par64 =3D do_ats_write(env, value, access_type, mmu_idx, secure);
+ par64 =3D do_ats_write(env, value, access_type, mmu_idx, ss);
=20
A32_BANKED_CURRENT_REG_SET(env, par, par64);
#else
@@ -3608,7 +3606,8 @@ static void ats1h_write(CPUARMState *env, const ARMCP=
RegInfo *ri,
uint64_t par64;
=20
/* There is no SecureEL2 for AArch32. */
- par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2, false);
+ par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2,
+ ARMSS_NonSecure);
=20
A32_BANKED_CURRENT_REG_SET(env, par, par64);
#else
@@ -3633,7 +3632,6 @@ static void ats_write64(CPUARMState *env, const ARMCP=
RegInfo *ri,
#ifdef CONFIG_TCG
MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA=
_LOAD;
ARMMMUIdx mmu_idx;
- int secure =3D arm_is_secure_below_el3(env);
uint64_t hcr_el2 =3D arm_hcr_el2_eff(env);
bool regime_e20 =3D (hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | =
HCR_TGE);
=20
@@ -3653,7 +3651,6 @@ static void ats_write64(CPUARMState *env, const ARMCP=
RegInfo *ri,
break;
case 6: /* AT S1E3R, AT S1E3W */
mmu_idx =3D ARMMMUIdx_E3;
- secure =3D true;
break;
default:
g_assert_not_reached();
@@ -3673,7 +3670,7 @@ static void ats_write64(CPUARMState *env, const ARMCP=
RegInfo *ri,
}
=20
env->cp15.par_el[1] =3D do_ats_write(env, value, access_type,
- mmu_idx, secure);
+ mmu_idx, arm_security_space(env));
#else
/* Handled by hardware accelerator. */
g_assert_not_reached();
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index ca4de6e3999..bfbab26b9b4 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -3420,15 +3420,15 @@ static bool get_phys_addr_gpc(CPUARMState *env, S1T=
ranslate *ptw,
return false;
}
=20
-bool get_phys_addr_with_secure_nogpc(CPUARMState *env, target_ulong addres=
s,
- MMUAccessType access_type,
- ARMMMUIdx mmu_idx, bool is_secure,
- GetPhysAddrResult *result,
- ARMMMUFaultInfo *fi)
+bool get_phys_addr_with_space_nogpc(CPUARMState *env, target_ulong address,
+ MMUAccessType access_type,
+ ARMMMUIdx mmu_idx, ARMSecuritySpace sp=
ace,
+ GetPhysAddrResult *result,
+ ARMMMUFaultInfo *fi)
{
S1Translate ptw =3D {
.in_mmu_idx =3D mmu_idx,
- .in_space =3D arm_secure_to_space(is_secure),
+ .in_space =3D space,
};
return get_phys_addr_nogpc(env, &ptw, address, access_type, result, fi=
);
}
--=20
2.34.1