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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 27/35] target/arm: Adjust PAR_EL1.SH for Device and Normal-NC
memory types
Date: Thu, 24 Aug 2023 10:28:28 +0100
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The PAR_EL1.SH field documents that for the cases of:
* Device memory
* Normal memory with both Inner and Outer Non-Cacheable
the field should be 0b10 rather than whatever was in the
translation table descriptor field. (In the pseudocode this
is handled by PAREncodeShareability().) Perform this
adjustment when assembling a PAR value.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-16-peter.maydell@linaro.org
---
target/arm/helper.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8290ca0aaad..da5db6d3ff6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3342,6 +3342,19 @@ static CPAccessResult ats_access(CPUARMState *env, c=
onst ARMCPRegInfo *ri,
}
=20
#ifdef CONFIG_TCG
+static int par_el1_shareability(GetPhysAddrResult *res)
+{
+ /*
+ * The PAR_EL1.SH field must be 0b10 for Device or Normal-NC
+ * memory -- see pseudocode PAREncodeShareability().
+ */
+ if (((res->cacheattrs.attrs & 0xf0) =3D=3D 0) ||
+ res->cacheattrs.attrs =3D=3D 0x44 || res->cacheattrs.attrs =3D=3D =
0x40) {
+ return 2;
+ }
+ return res->cacheattrs.shareability;
+}
+
static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
bool is_secure)
@@ -3470,7 +3483,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64=
_t value,
par64 |=3D (1 << 9); /* NS */
}
par64 |=3D (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */
- par64 |=3D res.cacheattrs.shareability << 7; /* SH */
+ par64 |=3D par_el1_shareability(&res) << 7; /* SH */
} else {
uint32_t fsr =3D arm_fi_to_lfsc(&fi);
=20
--=20
2.34.1