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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 24/35] target/arm/ptw: Set attributes correctly for MMU
disabled data accesses
Date: Thu, 24 Aug 2023 10:28:25 +0100
Message-Id: <20230824092836.2239644-25-peter.maydell@linaro.org>
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When the MMU is disabled, data accesses should be Device nGnRnE,
Outer Shareable, Untagged. We handle the other cases from
AArch64.S1DisabledOutput() correctly but missed this one.
Device nGnRnE is memattr =3D=3D 0, so the only part we were missing
was that shareability should be set to 2 for both insn fetches
and data accesses.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-13-peter.maydell@linaro.org
---
target/arm/ptw.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 312ccabe92e..7f217a31895 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -3108,11 +3108,13 @@ static bool get_phys_addr_disabled(CPUARMState *env,
}
}
}
- if (memattr =3D=3D 0 && access_type =3D=3D MMU_INST_FETCH) {
- if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
- memattr =3D 0xee; /* Normal, WT, RA, NT */
- } else {
- memattr =3D 0x44; /* Normal, NC, No */
+ if (memattr =3D=3D 0) {
+ if (access_type =3D=3D MMU_INST_FETCH) {
+ if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
+ memattr =3D 0xee; /* Normal, WT, RA, NT */
+ } else {
+ memattr =3D 0x44; /* Normal, NC, No */
+ }
}
shareability =3D 2; /* outer shareable */
}
--=20
2.34.1