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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 23/35] target/arm/ptw: Drop S1Translate::out_secure
Date: Thu, 24 Aug 2023 10:28:24 +0100
Message-Id: <20230824092836.2239644-24-peter.maydell@linaro.org>
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We only use S1Translate::out_secure in two places, where we are
setting up MemTxAttrs for a page table load. We can use
arm_space_is_secure(ptw->out_space) instead, which guarantees
that we're setting the MemTxAttrs secure and space fields
consistently, and allows us to drop the out_secure field in
S1Translate entirely.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-12-peter.maydell@linaro.org
---
target/arm/ptw.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 78bc679deef..312ccabe92e 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -63,7 +63,6 @@ typedef struct S1Translate {
* Stage 2 is indicated by in_mmu_idx set to ARMMMUIdx_Stage2{,_S}.
*/
bool in_s1_is_el0;
- bool out_secure;
bool out_rw;
bool out_be;
ARMSecuritySpace out_space;
@@ -553,7 +552,6 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl=
ate *ptw,
pte_attrs =3D s2.cacheattrs.attrs;
ptw->out_host =3D NULL;
ptw->out_rw =3D false;
- ptw->out_secure =3D s2.f.attrs.secure;
ptw->out_space =3D s2.f.attrs.space;
} else {
#ifdef CONFIG_TCG
@@ -572,7 +570,6 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl=
ate *ptw,
ptw->out_phys =3D full->phys_addr | (addr & ~TARGET_PAGE_MASK);
ptw->out_rw =3D full->prot & PAGE_WRITE;
pte_attrs =3D full->pte_attrs;
- ptw->out_secure =3D full->attrs.secure;
ptw->out_space =3D full->attrs.space;
#else
g_assert_not_reached();
@@ -630,8 +627,8 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, S1Transla=
te *ptw,
} else {
/* Page tables are in MMIO. */
MemTxAttrs attrs =3D {
- .secure =3D ptw->out_secure,
.space =3D ptw->out_space,
+ .secure =3D arm_space_is_secure(ptw->out_space),
};
AddressSpace *as =3D arm_addressspace(cs, attrs);
MemTxResult result =3D MEMTX_OK;
@@ -676,8 +673,8 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Transla=
te *ptw,
} else {
/* Page tables are in MMIO. */
MemTxAttrs attrs =3D {
- .secure =3D ptw->out_secure,
.space =3D ptw->out_space,
+ .secure =3D arm_space_is_secure(ptw->out_space),
};
AddressSpace *as =3D arm_addressspace(cs, attrs);
MemTxResult result =3D MEMTX_OK;
--=20
2.34.1