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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 22/35] target/arm/ptw: Remove S1Translate::in_secure
Date: Thu, 24 Aug 2023 10:28:23 +0100
Message-Id: <20230824092836.2239644-23-peter.maydell@linaro.org>
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We no longer look at the in_secure field of the S1Translate struct
anyway, so we can remove it and all the code which sets it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-11-peter.maydell@linaro.org
---
target/arm/ptw.c | 13 -------------
1 file changed, 13 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 1ca25438c3c..78bc679deef 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -51,13 +51,6 @@ typedef struct S1Translate {
* value being Stage2 vs Stage2_S distinguishes those.
*/
ARMSecuritySpace in_space;
- /*
- * in_secure: whether the translation regime is a Secure one.
- * This is always equal to arm_space_is_secure(in_space).
- * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
- * this field is updated accordingly.
- */
- bool in_secure;
/*
* in_debug: is this a QEMU debug access (gdbstub, etc)? Debug
* accesses will not update the guest page table access flags
@@ -547,7 +540,6 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl=
ate *ptw,
S1Translate s2ptw =3D {
.in_mmu_idx =3D s2_mmu_idx,
.in_ptw_idx =3D ptw_idx_for_stage_2(env, s2_mmu_idx),
- .in_secure =3D arm_space_is_secure(s2_space),
.in_space =3D s2_space,
.in_debug =3D true,
};
@@ -1784,7 +1776,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr=
anslate *ptw,
QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_S + 1 !=3D ARMMMUIdx_Phys_NS);
QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 !=3D ARMMMUIdx_Stage2);
ptw->in_ptw_idx +=3D 1;
- ptw->in_secure =3D false;
ptw->in_space =3D ARMSS_NonSecure;
}
=20
@@ -3167,7 +3158,6 @@ static bool get_phys_addr_twostage(CPUARMState *env, =
S1Translate *ptw,
=20
ptw->in_s1_is_el0 =3D ptw->in_mmu_idx =3D=3D ARMMMUIdx_Stage1_E0;
ptw->in_mmu_idx =3D ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
- ptw->in_secure =3D ipa_secure;
ptw->in_space =3D ipa_space;
ptw->in_ptw_idx =3D ptw_idx_for_stage_2(env, ptw->in_mmu_idx);
=20
@@ -3403,7 +3393,6 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ=
et_ulong address,
{
S1Translate ptw =3D {
.in_mmu_idx =3D mmu_idx,
- .in_secure =3D is_secure,
.in_space =3D arm_secure_to_space(is_secure),
};
return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi);
@@ -3475,7 +3464,6 @@ bool get_phys_addr(CPUARMState *env, target_ulong add=
ress,
}
=20
ptw.in_space =3D ss;
- ptw.in_secure =3D arm_space_is_secure(ss);
return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi);
}
=20
@@ -3489,7 +3477,6 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs=
, vaddr addr,
S1Translate ptw =3D {
.in_mmu_idx =3D mmu_idx,
.in_space =3D ss,
- .in_secure =3D arm_space_is_secure(ss),
.in_debug =3D true,
};
GetPhysAddrResult res =3D {};
--=20
2.34.1