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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 17/35] target/arm/ptw: Pass ARMSecurityState to
regime_translation_disabled()
Date: Thu, 24 Aug 2023 10:28:18 +0100
Message-Id: <20230824092836.2239644-18-peter.maydell@linaro.org>
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Plumb the ARMSecurityState through to regime_translation_disabled()
rather than just a bool is_secure.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-6-peter.maydell@linaro.org
---
target/arm/ptw.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index a873fbe0239..63dd8e3cbe1 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -206,9 +206,10 @@ static uint64_t regime_ttbr(CPUARMState *env, ARMMMUId=
x mmu_idx, int ttbrn)
=20
/* Return true if the specified stage of address translation is disabled */
static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_id=
x,
- bool is_secure)
+ ARMSecuritySpace space)
{
uint64_t hcr_el2;
+ bool is_secure =3D arm_space_is_secure(space);
=20
if (arm_feature(env, ARM_FEATURE_M)) {
switch (env->v7m.mpu_ctrl[is_secure] &
@@ -2057,9 +2058,8 @@ static bool get_phys_addr_pmsav5(CPUARMState *env,
uint32_t base;
ARMMMUIdx mmu_idx =3D ptw->in_mmu_idx;
bool is_user =3D regime_is_user(env, mmu_idx);
- bool is_secure =3D arm_space_is_secure(ptw->in_space);
=20
- if (regime_translation_disabled(env, mmu_idx, is_secure)) {
+ if (regime_translation_disabled(env, mmu_idx, ptw->in_space)) {
/* MPU disabled. */
result->f.phys_addr =3D address;
result->f.prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC;
@@ -2231,7 +2231,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env,
result->f.lg_page_size =3D TARGET_PAGE_BITS;
result->f.prot =3D 0;
=20
- if (regime_translation_disabled(env, mmu_idx, secure) ||
+ if (regime_translation_disabled(env, mmu_idx, ptw->in_space) ||
m_is_ppb_region(env, address)) {
/*
* MPU disabled or M profile PPB access: use default memory map.
@@ -2475,7 +2475,8 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add=
ress,
* are done in arm_v7m_load_vector(), which always does a direct
* read using address_space_ldl(), rather than going via this function.
*/
- if (regime_translation_disabled(env, mmu_idx, secure)) { /* MPU disabl=
ed */
+ if (regime_translation_disabled(env, mmu_idx, arm_secure_to_space(secu=
re))) {
+ /* MPU disabled */
hit =3D true;
} else if (m_is_ppb_region(env, address)) {
hit =3D true;
@@ -3303,7 +3304,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1T=
ranslate *ptw,
*/
ptw->in_mmu_idx =3D mmu_idx =3D s1_mmu_idx;
if (arm_feature(env, ARM_FEATURE_EL2) &&
- !regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)=
) {
+ !regime_translation_disabled(env, ARMMMUIdx_Stage2, ptw->in_sp=
ace)) {
return get_phys_addr_twostage(env, ptw, address, access_type,
result, fi);
}
@@ -3362,7 +3363,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1T=
ranslate *ptw,
=20
/* Definitely a real MMU, not an MPU */
=20
- if (regime_translation_disabled(env, mmu_idx, is_secure)) {
+ if (regime_translation_disabled(env, mmu_idx, ptw->in_space)) {
return get_phys_addr_disabled(env, ptw, address, access_type,
result, fi);
}
--=20
2.34.1