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([2602:47:d483:7301:72f0:1ea7:85d2:141e]) by smtp.gmail.com with ESMTPSA id iz22-20020a170902ef9600b001b9da42cd7dsm11418641plb.279.2023.08.23.13.23.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Aug 2023 13:23:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1692822218; x=1693427018; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=m32t45SXSN5mAoXF6SAGM5jFZ/43uDf4E7JMPMdT2hs=; b=Hh2WLv3F0ZtJCHCEOzNDgYmaq9voSAFwHlOCU88WZ8Q8ZLJ/e6HA13yJZQgx0QQCWb MIRRRwCLNB63bX3vbgkkKVyd7H/xj17QNkBWPi5YYNM+N+GABHKu/bdaLKhwwBy5zGzq umW0rwh/aDtWeKdS32PwZiOlIYxfY8lk3idJxdQTnsWUHDXPN8PWpSEPzSGbKSrmHgcX LvFakOebIFairX5Qcxlc2dZYy28S3EZboJUtogkGWj/FncD4cqyFEwwq9as2pDL5Thym H7VAiABHu+IHqihpMNaconawflHr1JHrM8aqJOVhZPWX8I1z06BF6bA+z3magWQCmGaR U4tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692822218; x=1693427018; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m32t45SXSN5mAoXF6SAGM5jFZ/43uDf4E7JMPMdT2hs=; b=SVOYYnpfe0CoXK0KoMZKgpdlFNRBIXjnbO5jM2bh7EuQfaNYQbKaQCSRCunTHF8Lg3 J57OX5wxeyElSoUvXbYo7E13W64yttBXMl1V9wZt6pAjv8HV2UGw+5N1HxCSbY9IWOQG BwqHEGrvWHRv+2U4SdCYrA41cHsae389e06lEGEuNpvPv0wlQVa+RAE3qZk6Nt1YbtJX 9XpIiCBXBdp0rY16JfjwoJ80m15xOjwXIMaoqLCGVEycBFCkT4xTli2R9X0whrKFwFMw yq/RTxgCAfvZdVxgtYr/OgReR0cwaXeINbtqHXJSO5l3234IfXSKtxPPUiLPSBqETTMq KNtg== X-Gm-Message-State: AOJu0YyrHijPVTPdzr65wPUIueaPFDuQ71sjyivVl9ilYjus+qop8DoB 1zuA/bJSB4w42yiHIhXJ0nKFuAaRyhP9EvdJelQ= X-Google-Smtp-Source: AGHT+IGGT9tD21aEYZnfbM+RI8gvgoeDISQuDEUHvLnJNkr8gpTTpP6Y6U+r2DudJX23Ur0+6rOEPg== X-Received: by 2002:a17:902:9a4a:b0:1bd:ba57:5a8f with SMTP id x10-20020a1709029a4a00b001bdba575a8fmr10866321plv.13.1692822218459; Wed, 23 Aug 2023 13:23:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 11/48] tcg/i386: Drop BYTEH deposits for 64-bit Date: Wed, 23 Aug 2023 13:22:49 -0700 Message-Id: <20230823202326.1353645-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230823202326.1353645-1-richard.henderson@linaro.org> References: <20230823202326.1353645-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1692822366972100002 Content-Type: text/plain; charset="utf-8" It is more useful to allow low-part deposits into all registers than to restrict allocation for high-byte deposits. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/i386/tcg-target-con-set.h | 2 +- tcg/i386/tcg-target-con-str.h | 1 - tcg/i386/tcg-target.h | 4 ++-- tcg/i386/tcg-target.c.inc | 7 +++---- 4 files changed, 6 insertions(+), 8 deletions(-) diff --git a/tcg/i386/tcg-target-con-set.h b/tcg/i386/tcg-target-con-set.h index 5ea3a292f0..3949d49538 100644 --- a/tcg/i386/tcg-target-con-set.h +++ b/tcg/i386/tcg-target-con-set.h @@ -33,7 +33,7 @@ C_O1_I1(r, q) C_O1_I1(r, r) C_O1_I1(x, r) C_O1_I1(x, x) -C_O1_I2(Q, 0, Q) +C_O1_I2(q, 0, q) C_O1_I2(q, r, re) C_O1_I2(r, 0, ci) C_O1_I2(r, 0, r) diff --git a/tcg/i386/tcg-target-con-str.h b/tcg/i386/tcg-target-con-str.h index 24e6bcb80d..95a30e58cd 100644 --- a/tcg/i386/tcg-target-con-str.h +++ b/tcg/i386/tcg-target-con-str.h @@ -19,7 +19,6 @@ REGS('D', 1u << TCG_REG_EDI) REGS('r', ALL_GENERAL_REGS) REGS('x', ALL_VECTOR_REGS) REGS('q', ALL_BYTEL_REGS) /* regs that can be used as a byte operand */ -REGS('Q', ALL_BYTEH_REGS) /* regs with a second byte (e.g. %ah) */ REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_ld/st */ REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_st8_i32 data = */ =20 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 2a2e3fffa8..30cce01ca4 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -227,8 +227,8 @@ typedef enum { #define TCG_TARGET_HAS_cmpsel_vec -1 =20 #define TCG_TARGET_deposit_i32_valid(ofs, len) \ - (((ofs) =3D=3D 0 && (len) =3D=3D 8) || ((ofs) =3D=3D 8 && (len) =3D=3D= 8) || \ - ((ofs) =3D=3D 0 && (len) =3D=3D 16)) + (((ofs) =3D=3D 0 && ((len) =3D=3D 8 || (len) =3D=3D 16)) || \ + (TCG_TARGET_REG_BITS =3D=3D 32 && (ofs) =3D=3D 8 && (len) =3D=3D 8)) #define TCG_TARGET_deposit_i64_valid TCG_TARGET_deposit_i32_valid =20 /* Check for the possibility of high-byte extraction and, for 64-bit, diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index a6b2eae995..ba40dd0f4d 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -144,7 +144,6 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKin= d kind, int slot) # define TCG_REG_L1 TCG_REG_EDX #endif =20 -#define ALL_BYTEH_REGS 0x0000000fu #if TCG_TARGET_REG_BITS =3D=3D 64 # define ALL_GENERAL_REGS 0x0000ffffu # define ALL_VECTOR_REGS 0xffff0000u @@ -152,7 +151,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKin= d kind, int slot) #else # define ALL_GENERAL_REGS 0x000000ffu # define ALL_VECTOR_REGS 0x00ff0000u -# define ALL_BYTEL_REGS ALL_BYTEH_REGS +# define ALL_BYTEL_REGS 0x0000000fu #endif #ifdef CONFIG_SOFTMMU # define SOFTMMU_RESERVE_REGS ((1 << TCG_REG_L0) | (1 << TCG_REG_L1)) @@ -2752,7 +2751,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, if (args[3] =3D=3D 0 && args[4] =3D=3D 8) { /* load bits 0..7 */ tcg_out_modrm(s, OPC_MOVB_EvGv | P_REXB_R | P_REXB_RM, a2, a0); - } else if (args[3] =3D=3D 8 && args[4] =3D=3D 8) { + } else if (TCG_TARGET_REG_BITS =3D=3D 32 && args[3] =3D=3D 8 && ar= gs[4] =3D=3D 8) { /* load bits 8..15 */ tcg_out_modrm(s, OPC_MOVB_EvGv, a2, a0 + 4); } else if (args[3] =3D=3D 0 && args[4] =3D=3D 16) { @@ -3312,7 +3311,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return C_O1_I2(Q, 0, Q); + return C_O1_I2(q, 0, q); =20 case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: --=20 2.34.1