From nobody Thu Nov 28 12:59:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1692773854060199.34522011250988; Tue, 22 Aug 2023 23:57:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qYhlR-0004At-GK; Wed, 23 Aug 2023 02:54:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qYhkz-00045V-EC for qemu-devel@nongnu.org; Wed, 23 Aug 2023 02:54:26 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qYhkx-00019c-Dx for qemu-devel@nongnu.org; Wed, 23 Aug 2023 02:54:21 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 6E2491C405 for ; Wed, 23 Aug 2023 09:54:21 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 985F8212A7; Wed, 23 Aug 2023 09:54:01 +0300 (MSK) Received: (nullmailer pid 1919466 invoked by uid 1000); Wed, 23 Aug 2023 06:54:00 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: Michael Tokarev Subject: [PATCH 11/24] hexagon: spelling fixes Date: Wed, 23 Aug 2023 09:53:22 +0300 Message-Id: <20230823065335.1919380-10-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230823055155.1917375-1-mjt@tls.msk.ru> References: <20230823055155.1917375-1-mjt@tls.msk.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1692773855191100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Michael Tokarev Reviewed-by: Brian Cain --- target/hexagon/README | 2 +- target/hexagon/fma_emu.c | 2 +- target/hexagon/idef-parser/README.rst | 2 +- target/hexagon/idef-parser/idef-parser.h | 2 +- target/hexagon/idef-parser/parser-helpers.c | 6 +++--- target/hexagon/imported/alu.idef | 8 ++++---- target/hexagon/imported/macros.def | 2 +- target/hexagon/imported/mmvec/ext.idef | 10 +++++----- tests/tcg/hexagon/fpstuff.c | 2 +- tests/tcg/hexagon/test_clobber.S | 2 +- 10 files changed, 19 insertions(+), 19 deletions(-) diff --git a/target/hexagon/README b/target/hexagon/README index 43811178e9..e757bcb64a 100644 --- a/target/hexagon/README +++ b/target/hexagon/README @@ -240,5 +240,5 @@ helper_funcs_generated.c.inc. There are also several h= elpers used for debugging VLIW packet semantics differ from serial semantics in that all input opera= nds are read, then the operations are performed, then all the results are writ= ten. -For exmaple, this packet performs a swap of registers r0 and r1 +For example, this packet performs a swap of registers r0 and r1 { r0 =3D r1; r1 =3D r0 } Note that the result is different if the instructions are executed seriall= y. diff --git a/target/hexagon/fma_emu.c b/target/hexagon/fma_emu.c index d3b45d494f..05a56d8c10 100644 --- a/target/hexagon/fma_emu.c +++ b/target/hexagon/fma_emu.c @@ -416,5 +416,5 @@ static SUFFIX accum_round_##SUFFIX(Accum a, float_statu= s * fp_status) \ * Theoretically, we only need to shift a maximum of one to the left i= f we \ * shifted out lots of bits from B, or if we had no shift / 1 shift st= icky \ - * shoudl be 0 \ + * should be 0 \ */ \ while ((int128_getlo(a.mant) & (1ULL << MANTBITS)) =3D=3D 0) { \ diff --git a/target/hexagon/idef-parser/README.rst b/target/hexagon/idef-pa= rser/README.rst index debeddfde5..d0aa34309b 100644 --- a/target/hexagon/idef-parser/README.rst +++ b/target/hexagon/idef-parser/README.rst @@ -441,5 +441,5 @@ interested part of the grammar. Run-time errors can be divided between lexing and parsing errors, lexing e= rrors are hard to detect, since the ``var`` token will catch everything which is= not -catched by other tokens, but easy to fix, because most of the time a simple +caught by other tokens, but easy to fix, because most of the time a simple regex editing will be enough. =20 diff --git a/target/hexagon/idef-parser/idef-parser.h b/target/hexagon/idef= -parser/idef-parser.h index d23e71f13b..3faa1deecd 100644 --- a/target/hexagon/idef-parser/idef-parser.h +++ b/target/hexagon/idef-parser/idef-parser.h @@ -74,5 +74,5 @@ typedef struct HexTmp { =20 /** - * Enum of the possible immediated, an immediate is a value which is known + * Enum of the possible immediate, an immediate is a value which is known * at tinycode generation time, e.g. an integer value, not a TCGv */ diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/i= def-parser/parser-helpers.c index 7b5ebafec2..ec43343801 100644 --- a/target/hexagon/idef-parser/parser-helpers.c +++ b/target/hexagon/idef-parser/parser-helpers.c @@ -460,5 +460,5 @@ static bool try_find_variable(Context *c, YYLTYPE *locp, } =20 -/* Calls `try_find_variable` and asserts succcess. */ +/* Calls `try_find_variable` and asserts success. */ static void find_variable(Context *c, YYLTYPE *locp, HexValue *dst, @@ -550,5 +550,5 @@ HexValue gen_bin_cmp(Context *c, break; default: - fprintf(stderr, "Error in evalutating immediateness!"); + fprintf(stderr, "Error in evaluating immediateness!"); abort(); } @@ -1165,5 +1165,5 @@ void gen_rdeposit_op(Context *c, /* * Otherwise if the width is not known, we fallback on reimplementing - * desposit in TCG. + * deposit in TCG. */ HexValue begin_m =3D *begin; diff --git a/target/hexagon/imported/alu.idef b/target/hexagon/imported/alu= .idef index 58477ae40a..12d2aac5d4 100644 --- a/target/hexagon/imported/alu.idef +++ b/target/hexagon/imported/alu.idef @@ -293,14 +293,14 @@ Q6INSN(A4_combineii,"Rdd32=3Dcombine(#s8,#U6)",ATTRIB= S(),"Set two small immediates =20 Q6INSN(A2_combine_hh,"Rd32=3Dcombine(Rt.H32,Rs.H32)",ATTRIBS(), -"Combine two halfs into a register", {RdV =3D (fGETUHALF(1,RtV)<<16) | fGE= TUHALF(1,RsV);}) +"Combine two halves into a register", {RdV =3D (fGETUHALF(1,RtV)<<16) | fG= ETUHALF(1,RsV);}) =20 Q6INSN(A2_combine_hl,"Rd32=3Dcombine(Rt.H32,Rs.L32)",ATTRIBS(), -"Combine two halfs into a register", {RdV =3D (fGETUHALF(1,RtV)<<16) | fGE= TUHALF(0,RsV);}) +"Combine two halves into a register", {RdV =3D (fGETUHALF(1,RtV)<<16) | fG= ETUHALF(0,RsV);}) =20 Q6INSN(A2_combine_lh,"Rd32=3Dcombine(Rt.L32,Rs.H32)",ATTRIBS(), -"Combine two halfs into a register", {RdV =3D (fGETUHALF(0,RtV)<<16) | fGE= TUHALF(1,RsV);}) +"Combine two halves into a register", {RdV =3D (fGETUHALF(0,RtV)<<16) | fG= ETUHALF(1,RsV);}) =20 Q6INSN(A2_combine_ll,"Rd32=3Dcombine(Rt.L32,Rs.L32)",ATTRIBS(), -"Combine two halfs into a register", {RdV =3D (fGETUHALF(0,RtV)<<16) | fGE= TUHALF(0,RsV);}) +"Combine two halves into a register", {RdV =3D (fGETUHALF(0,RtV)<<16) | fG= ETUHALF(0,RsV);}) =20 Q6INSN(A2_tfril,"Rx.L32=3D#u16",ATTRIBS(), diff --git a/target/hexagon/imported/macros.def b/target/hexagon/imported/m= acros.def index e23f91562e..4bbcfdd5e1 100755 --- a/target/hexagon/imported/macros.def +++ b/target/hexagon/imported/macros.def @@ -903,5 +903,5 @@ DEF_MACRO( =20 DEF_MACRO( - fEA_GPI, /* Calculate EA with Global Poitner + Immediate */ + fEA_GPI, /* Calculate EA with Global Pointer + Immediate */ do { EA=3DfREAD_GP()+IMM; fGP_DOCHKPAGECROSS(fREAD_GP(),EA); } while (= 0), () diff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/import= ed/mmvec/ext.idef index ead32c243b..98daabfb07 100644 --- a/target/hexagon/imported/mmvec/ext.idef +++ b/target/hexagon/imported/mmvec/ext.idef @@ -18,5 +18,5 @@ /*************************************************************************= ***** * - * HOYA: MULTI MEDIA INSTRUCITONS + * HOYA: MULTI MEDIA INSTRUCTIONS * *************************************************************************= *****/ @@ -296,5 +296,5 @@ MMVEC_COND_EACH_EA(vS32Ub,"Unaligned Vector Store",ATTR= IBS(ATTR_VMEMU,A_STORE,A_ MMVEC_EACH_EA(vS32b_new,"Aligned Vector Store New",ATTRIBS(ATTR_VMEM,A_STO= RE,A_CVI_NEW,A_DOTNEWVALUE,A_RESTRICT_SLOT0ONLY),,"vmem","=3DOs8.new",fSTOR= EMMV(EA,fNEWVREG(OsN))) =20 -// V65 store relase, zero byte store +// V65 store release, zero byte store MMVEC_EACH_EA(vS32b_srls,"Aligned Vector Scatter Release",ATTRIBS(ATTR_VME= M,A_STORE,A_CVI_SCATTER_RELEASE,A_CVI_NEW,A_RESTRICT_SLOT0ONLY),,"vmem",":s= catter_release",fSTORERELEASE(EA,0)) =20 @@ -2046,9 +2046,9 @@ VxV.uw[0] =3D RtV;) =20 =20 -ITERATOR_INSN_MPY_SLOT_LATE(32,lvsplatw, "Vd32=3Dvsplat(Rt32)", "Replicate= s scalar accross words in vector", VdV.uw[i] =3D RtV) +ITERATOR_INSN_MPY_SLOT_LATE(32,lvsplatw, "Vd32=3Dvsplat(Rt32)", "Replicate= s scalar across words in vector", VdV.uw[i] =3D RtV) =20 -ITERATOR_INSN_MPY_SLOT_LATE(16,lvsplath, "Vd32.h=3Dvsplat(Rt32)", "Replica= tes scalar accross halves in vector", VdV.uh[i] =3D RtV) +ITERATOR_INSN_MPY_SLOT_LATE(16,lvsplath, "Vd32.h=3Dvsplat(Rt32)", "Replica= tes scalar across halves in vector", VdV.uh[i] =3D RtV) =20 -ITERATOR_INSN_MPY_SLOT_LATE(8,lvsplatb, "Vd32.b=3Dvsplat(Rt32)", "Replicat= es scalar accross bytes in vector", VdV.ub[i] =3D RtV) +ITERATOR_INSN_MPY_SLOT_LATE(8,lvsplatb, "Vd32.b=3Dvsplat(Rt32)", "Replicat= es scalar across bytes in vector", VdV.ub[i] =3D RtV) =20 =20 diff --git a/tests/tcg/hexagon/fpstuff.c b/tests/tcg/hexagon/fpstuff.c index 344b9f7772..6aadaccabd 100644 --- a/tests/tcg/hexagon/fpstuff.c +++ b/tests/tcg/hexagon/fpstuff.c @@ -53,5 +53,5 @@ static void check_compare_exception(void) uint32_t usr; =20 - /* Check that FP compares are quiet (don't raise any execptions) */ + /* Check that FP compares are quiet (don't raise any exceptions) */ asm (CLEAR_FPSTATUS "p0 =3D sfcmp.eq(%2, %3)\n\t" diff --git a/tests/tcg/hexagon/test_clobber.S b/tests/tcg/hexagon/test_clob= ber.S index a7aeb2b60c..10046c30d2 100644 --- a/tests/tcg/hexagon/test_clobber.S +++ b/tests/tcg/hexagon/test_clobber.S @@ -1,4 +1,4 @@ /* - * Purpose: demonstrate the succesful operation of the register save mecha= nism, + * Purpose: demonstrate the successful operation of the register save mech= anism, * in which the caller saves the registers that will be clobbered, and res= tores * them after the call. --=20 2.39.2