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([2602:47:d483:7301:4e3c:f4a4:b92a:b5ab]) by smtp.gmail.com with ESMTPSA id 27-20020a17090a031b00b00264040322desm8761121pje.40.2023.08.22.10.02.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Aug 2023 10:02:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1692723732; x=1693328532; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jVHhYuUKW52ubI148rbZcLTzbA6J0OmH3AziT1EPcOU=; b=XMnQBulDR4Ustiqol4myQIFiIOepUtO3YNk1jNTdWULlrrRjHTDaoMH7qyfedBcokR w2JDYrivaWMb8XVbjX+VHbd6za7n6bldANm8SngfSG+FYqmPRm14+wqT8LHIWe8D2wEC EHBjuprO4G36Wg8TR46ThSjxqENMPNEkQxG0JzcQAN6DFGc3bjaPLvC7fWyCqV4vQiD1 llBbJO5nMRWleoMU3QIlmdS0pYrv2p5HQB7iOUufZgvSj6BgyW77GvLFI06YAmpAPhkK h1dfTQ5Mc/t7CWkwUtfQmPo8jSvdBSbpBawYmUISUFfQPo4yI9PhHSvnItdrnrSZXphO vMLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692723732; x=1693328532; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jVHhYuUKW52ubI148rbZcLTzbA6J0OmH3AziT1EPcOU=; b=GWUr7rDkIREEeyd8UMGQU01ZdnV+Xo8biQpdI9Z2Y/3DZ6RpzEh7ygwdpP4QHUPgVW 8A5HtNyYyWWvSN2u5jf1EJvcj2Q8GUcNFuaJlsAEfmh5sCXxzlqi/BoOKPjbkZDEs4h+ cMlolvJMb5JffSL8HH1+UFofEmbVYqfoEAr6zFRlzFNpAqt+bEKtOx/8talF5xm9DUOv u12FFb9PAaImHjwcTbvFKn34IBKnOs8iZGIF3aTOQ4hNQpsUBJssRUK6UbbV8rgPVbkO r0oB417Fv5KKo+pabXSiKEMyqOnA7+WbcXLPlpUdF7Bx48YlbRc3MV+tfkraoi9/MkVN WqQQ== X-Gm-Message-State: AOJu0YzqwYTSfmUGK/irTYTr4XQo7VDEvRKZeq5nvmVbNBosIXyjrhJQ JTKxWtR1uguvmdRnPx1Kyr0Sjjp40YmqJINqyK0= X-Google-Smtp-Source: AGHT+IH5vZ+iq9e2/moJ+aEuvtAOTe1Pqjenyu54E5IPgy17Vm3wobdEog31vjhtqTIpDstQHYazjw== X-Received: by 2002:a17:90a:e7cd:b0:26b:5758:8a04 with SMTP id kb13-20020a17090ae7cd00b0026b57588a04mr8860306pjb.29.1692723731936; Tue, 22 Aug 2023 10:02:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 1/3] linux-user/aarch64: Add ESR signal frame for SIGSEGV, SIGBUS Date: Tue, 22 Aug 2023 10:02:07 -0700 Message-Id: <20230822170209.1130173-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230822170209.1130173-1-richard.henderson@linaro.org> References: <20230822170209.1130173-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1692723842073100001 Content-Type: text/plain; charset="utf-8" These are all synchronous exceptions for which the kernel passes on ESR to the user signal handler. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 48 ++++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index b265cfd470..b2280fa9e3 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -21,6 +21,7 @@ #include "user-internals.h" #include "signal-common.h" #include "linux-user/trace.h" +#include "target/arm/syndrome.h" =20 struct target_sigcontext { uint64_t fault_address; @@ -64,6 +65,13 @@ struct target_fpsimd_context { uint64_t vregs[32 * 2]; /* really uint128_t vregs[32] */ }; =20 +#define TARGET_ESR_MAGIC 0x45535201 + +struct target_esr_context { + struct target_aarch64_ctx head; + uint64_t esr; +}; + #define TARGET_EXTRA_MAGIC 0x45585401 =20 struct target_extra_context { @@ -191,6 +199,14 @@ static void target_setup_end_record(struct target_aarc= h64_ctx *end) __put_user(0, &end->size); } =20 +static void target_setup_esr_record(struct target_esr_context *esr, + CPUARMState *env) +{ + __put_user(TARGET_ESR_MAGIC, &esr->head.magic); + __put_user(sizeof(struct target_esr_context), &esr->head.size); + __put_user(env->exception.syndrome, &esr->esr); +} + static void target_setup_sve_record(struct target_sve_context *sve, CPUARMState *env, int size) { @@ -443,6 +459,10 @@ static int target_restore_sigframe(CPUARMState *env, fpsimd =3D (struct target_fpsimd_context *)ctx; break; =20 + case TARGET_ESR_MAGIC: + /* ignore */ + break; + case TARGET_SVE_MAGIC: if (sve || size < sizeof(struct target_sve_context)) { goto err; @@ -558,6 +578,23 @@ static int alloc_sigframe_space(int this_size, target_= sigframe_layout *l) return this_loc; } =20 +static bool need_save_esr(target_siginfo_t *info, CPUARMState *env) +{ + int sig =3D info->si_signo; + int type =3D info->si_code >> 16; + + if (type !=3D QEMU_SI_FAULT) { + return false; + } + + /* See arch/arm64/mm/fault.c, set_thread_esr. */ + if (sig =3D=3D TARGET_SIGSEGV || sig =3D=3D TARGET_SIGBUS) { + return true; + } + + return false; +} + static void target_setup_frame(int usig, struct target_sigaction *ka, target_siginfo_t *info, target_sigset_t *se= t, CPUARMState *env) @@ -567,7 +604,7 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, .total_size =3D offsetof(struct target_rt_sigframe, uc.tuc_mcontext.__reserved), }; - int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, za_ofs =3D 0; + int fpsimd_ofs, fr_ofs, esr_ofs =3D 0, sve_ofs =3D 0, za_ofs =3D 0; int sve_size =3D 0, za_size =3D 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; @@ -577,6 +614,12 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, fpsimd_ofs =3D alloc_sigframe_space(sizeof(struct target_fpsimd_contex= t), &layout); =20 + /* ESR state needs saving only for certain signals. */ + if (need_save_esr(info, env)) { + esr_ofs =3D alloc_sigframe_space(sizeof(struct target_esr_context), + &layout); + } + /* SVE state needs saving only if it exists. */ if (cpu_isar_feature(aa64_sve, env_archcpu(env)) || cpu_isar_feature(aa64_sme, env_archcpu(env))) { @@ -637,6 +680,9 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, layout.extra_size); target_setup_end_record((void *)frame + layout.extra_end_ofs); } + if (esr_ofs) { + target_setup_esr_record((void *)frame + esr_ofs, env); + } if (sve_ofs) { target_setup_sve_record((void *)frame + sve_ofs, env, sve_size); } --=20 2.34.1