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Iglesias" , Richard Henderson , Greg Kurz , Aurelien Jarno , Peter Maydell , qemu-ppc@nongnu.org, Daniel Henrique Barboza , Aleksandar Rikalo , Paolo Bonzini , David Gibson , Jiaxun Yang , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Yoshinori Sato , Nicholas Piggin , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH 01/12] tcg/tcg-op: Factor tcg_gen_hrev32_i32() out Date: Tue, 22 Aug 2023 14:40:31 +0200 Message-ID: <20230822124042.54739-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230822124042.54739-1-philmd@linaro.org> References: <20230822124042.54739-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1692708130178100002 Byteswapping each halfword is a common operation, so extract to a new tcg_gen_hrev32_i32() generic helper. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- docs/devel/tcg-ops.rst | 4 ++++ include/tcg/tcg-op-common.h | 1 + tcg/tcg-op.c | 29 +++++++++++++++++++++++------ 3 files changed, 28 insertions(+), 6 deletions(-) diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst index 7ea6aba502..17965faa03 100644 --- a/docs/devel/tcg-ops.rst +++ b/docs/devel/tcg-ops.rst @@ -490,6 +490,10 @@ Misc into 32-bit output *t0*. Depending on the host, this may be a si= mple shift, or may require additional canonicalization. =20 + * - hrev32_i32 *t0*, *t1* + + - | Byteswap each halfword within a 32-bit value. + * - hswap_i32/i64 *t0*, *t1* =20 - | Swap 16-bit halfwords within a 32/64-bit value. diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index be382bbf77..bb515dfd51 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -360,6 +360,7 @@ void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags); void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_hrev32_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index c436c5e263..b1b5d9b45b 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1073,14 +1073,9 @@ void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) } else { TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); TCGv_i32 t1 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 t2 =3D tcg_constant_i32(0x00ff00ff); =20 /* arg =3D abcd */ - tcg_gen_shri_i32(t0, arg, 8); /* t0 =3D .abc */ - tcg_gen_and_i32(t1, arg, t2); /* t1 =3D .b.d */ - tcg_gen_and_i32(t0, t0, t2); /* t0 =3D .a.c */ - tcg_gen_shli_i32(t1, t1, 8); /* t1 =3D b.d. */ - tcg_gen_or_i32(ret, t0, t1); /* ret =3D badc */ + tcg_gen_hrev32_i32(ret, arg); /* ret =3D badc */ =20 tcg_gen_shri_i32(t0, ret, 16); /* t0 =3D ..ba */ tcg_gen_shli_i32(t1, ret, 16); /* t1 =3D dc.. */ @@ -1102,6 +1097,28 @@ void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg) tcg_gen_rotli_i32(ret, arg, 16); } =20 +/* + * hswap_i32: Byteswap each halfword within a 32-bit value. + * + * Byte pattern: hswap_i32(abcd) -> badc + */ +void tcg_gen_hrev32_i32(TCGv_i32 ret, TCGv_i32 arg) +{ + TCGv_i32 mask =3D tcg_constant_i32(0x00ff00ff); + TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); + TCGv_i32 t1 =3D tcg_temp_ebb_new_i32(); + + /* arg =3D abcd */ + tcg_gen_shri_i32(t0, arg, 8); /* t0 =3D .abc */ + tcg_gen_and_i32(t1, arg, mask); /* t1 =3D .b.d */ + tcg_gen_and_i32(t0, t0, mask); /* t0 =3D .a.c */ + tcg_gen_shli_i32(t1, t1, 8); /* t1 =3D b.d. */ + tcg_gen_or_i32(ret, t0, t1); /* ret =3D badc */ + + tcg_temp_free_i32(t0); + tcg_temp_free_i32(t1); +} + void tcg_gen_smin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) { tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, a, b); --=20 2.41.0