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Tue, 22 Aug 2023 00:11:08 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Song Gao Cc: Huacai Chen , Jiajie Chen , Xiaojuan Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 08/19] target/loongarch: Extract set_pc() helper Date: Tue, 22 Aug 2023 09:10:01 +0200 Message-ID: <20230822071013.34884-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230822071013.34884-1-philmd@linaro.org> References: <20230822071013.34884-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1692688311166100003 From: Jiajie Chen Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/loongarch/cpu.h | 5 +++++ target/loongarch/cpu.c | 16 ++++++++-------- target/loongarch/gdbstub.c | 2 +- target/loongarch/op_helper.c | 4 ++-- 4 files changed, 16 insertions(+), 11 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 72109095e4..e1562695e8 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -443,6 +443,11 @@ static inline bool is_va32(CPULoongArchState *env) return va32; } =20 +static inline void set_pc(CPULoongArchState *env, uint64_t value) +{ + env->pc =3D value; +} + /* * LoongArch CPUs hardware flags. */ diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 822f2a72e5..67eb6c3135 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -81,7 +81,7 @@ static void loongarch_cpu_set_pc(CPUState *cs, vaddr valu= e) LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); CPULoongArchState *env =3D &cpu->env; =20 - env->pc =3D value; + set_pc(env, value); } =20 static vaddr loongarch_cpu_get_pc(CPUState *cs) @@ -168,7 +168,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) set_DERA: env->CSR_DERA =3D env->pc; env->CSR_DBG =3D FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); - env->pc =3D env->CSR_EENTRY + 0x480; + set_pc(env, env->CSR_EENTRY + 0x480); break; case EXCCODE_INT: if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { @@ -249,7 +249,8 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) =20 /* Find the highest-priority interrupt. */ vector =3D 31 - clz32(pending); - env->pc =3D env->CSR_EENTRY + (EXCCODE_EXTERNAL_INT + vector) * ve= c_size; + set_pc(env, env->CSR_EENTRY + \ + (EXCCODE_EXTERNAL_INT + vector) * vec_size); qemu_log_mask(CPU_LOG_INT, "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx " cause %d\n" " A " TARGET_FMT_lx " D " @@ -260,10 +261,9 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) env->CSR_ECFG, env->CSR_ESTAT); } else { if (tlbfill) { - env->pc =3D env->CSR_TLBRENTRY; + set_pc(env, env->CSR_TLBRENTRY); } else { - env->pc =3D env->CSR_EENTRY; - env->pc +=3D EXCODE_MCODE(cause) * vec_size; + set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size); } qemu_log_mask(CPU_LOG_INT, "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx @@ -324,7 +324,7 @@ static void loongarch_cpu_synchronize_from_tb(CPUState = *cs, CPULoongArchState *env =3D &cpu->env; =20 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); - env->pc =3D tb->pc; + set_pc(env, tb->pc); } =20 static void loongarch_restore_state_to_opc(CPUState *cs, @@ -334,7 +334,7 @@ static void loongarch_restore_state_to_opc(CPUState *cs, LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); CPULoongArchState *env =3D &cpu->env; =20 - env->pc =3D data[0]; + set_pc(env, data[0]); } #endif /* CONFIG_TCG */ =20 diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c index a462e25737..e20b20f99b 100644 --- a/target/loongarch/gdbstub.c +++ b/target/loongarch/gdbstub.c @@ -77,7 +77,7 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_= t *mem_buf, int n) env->gpr[n] =3D tmp; length =3D read_length; } else if (n =3D=3D 33) { - env->pc =3D tmp; + set_pc(env, tmp); length =3D read_length; } return length; diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c index 60335a05e2..cf84f20aba 100644 --- a/target/loongarch/op_helper.c +++ b/target/loongarch/op_helper.c @@ -114,14 +114,14 @@ void helper_ertn(CPULoongArchState *env) env->CSR_TLBRERA =3D FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, IST= LBR, 0); env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 0); env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 1); - env->pc =3D env->CSR_TLBRERA; + set_pc(env, env->CSR_TLBRERA); qemu_log_mask(CPU_LOG_INT, "%s: TLBRERA " TARGET_FMT_lx "\n", __func__, env->CSR_TLBRERA); } else { csr_pplv =3D FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PPLV); csr_pie =3D FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PIE); =20 - env->pc =3D env->CSR_ERA; + set_pc(env, env->CSR_ERA); qemu_log_mask(CPU_LOG_INT, "%s: ERA " TARGET_FMT_lx "\n", __func__, env->CSR_ERA); } --=20 2.41.0