From nobody Sat Sep 21 03:26:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1692688294; cv=none; d=zohomail.com; s=zohoarc; b=ZnfKtTnSNbG8IO36S8cspNfobRASJkOR80CRuAZfD4rjQtYq0NNIY1PQKQfHabFLS/2z7/NFxOoij/wlhVTYrlGUIARNORU/0S8L1gbJZcYzXWQ2Fy4Cz2vFTifP3fk5h1y34vOGYl6PzMfXArOzzXlvy32/+Uo4y3oFMipljDQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1692688294; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fvQZedijPtJ34ELRwqSS7RfwCk60jvhcOCv1VkYXcvk=; b=BCbr32CXBWvhrXWbOAxsLvvgYjUZqAzNx0JqpAvrULhfsLOmKq4f1TgYw9rSBrUVxxzho2Wl9FqYHYtcPjb8dK6rmo3C3VKU7CFuQKDdqYah2TtvBYFn5QyL1/rc4GBlpglbMxmzpWeK9n1yqoBIH79mWdXiSx544TfmDbHGmoo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1692688294498313.43321260212235; Tue, 22 Aug 2023 00:11:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qYLXj-0003Bl-RZ; Tue, 22 Aug 2023 03:11:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qYLXY-0002zM-84 for qemu-devel@nongnu.org; Tue, 22 Aug 2023 03:11:05 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qYLXV-0002Oh-Bd for qemu-devel@nongnu.org; Tue, 22 Aug 2023 03:10:59 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-3feef504ccbso19123055e9.2 for ; Tue, 22 Aug 2023 00:10:56 -0700 (PDT) Received: from localhost.localdomain ([37.19.214.4]) by smtp.gmail.com with ESMTPSA id x20-20020a05600c2a5400b003fef60005b5sm2505947wme.9.2023.08.22.00.10.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Aug 2023 00:10:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1692688256; x=1693293056; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fvQZedijPtJ34ELRwqSS7RfwCk60jvhcOCv1VkYXcvk=; b=gCTVVogpCHk7m/jexss5Prvsk4+BnfVR/S3cPnxREuxQy89Oyg9RioJLZYA80eavwd 1LMq6C6pbilFnNtEHR7gQ0CmeMVQnF+2sNQ7ZXu8eVCUS5n8oj0/DimFl1HLyAgwLoA5 l8nHsfXq/iB3NT4rVOE4hRhQiJNGmBP1zVcOn/Ca1U92q3nbGYO8OfI789S92g3kgg0B AAUhsL1fiPJV0kvLQOLtUrMAy7gN0+dzVk3Od75paCusTG57togM+joildzHnYqmumHy ANAF+vpFJPOW5jN20siU46gtmaeRZN7x3X7t2Gp9NoQ/d6/wv3vb+mOJ26ZijJxcbIty YTXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692688256; x=1693293056; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fvQZedijPtJ34ELRwqSS7RfwCk60jvhcOCv1VkYXcvk=; b=XsvTj8weR4428Yqk6mW3z6JYChScGdw0KjxsljsNs780dzEmnDCD5q2f3+qdwQAcIr PK0saEsG3H2TCXn/8YJvfOXHREyZt0pyWpdyHItylfAIazZbCqz1DFh6iLRjcFUt2Jiz xCyxyM0CfUqy3n76saE9NuKO2kd5jvtbu1qVzZHjs/R04irjRt9HQI8RucDrGTKx+xx1 0mdQZqi/ln4DQJw8mQa3+QU16a3PI+Y02zChUzREul6MKTmHHnbbOo+BBIOyDWiPVeFp zbLO/xUg3ynOxYeywAedrbNu9MK1Nc/+Er6zfAnSIauDjrKgwcITfdI7HYqra3Zcvmup 7pEw== X-Gm-Message-State: AOJu0YzXO8B2GtAxAbuzMtLd343MMj8Gg+Jux1PNmglC0UsfrCXVHfP8 iRM6tcQ3oeg/nJlB/+kkgvE45vo3bNRXvVrWclBBkQ== X-Google-Smtp-Source: AGHT+IHhYxRgROw+XiJPR3kg0/R51r2bhND2lyKq6A6bkF2Im3DJSeOgoGZzCHultghhYxSukFogig== X-Received: by 2002:a1c:7907:0:b0:3fe:1bef:4034 with SMTP id l7-20020a1c7907000000b003fe1bef4034mr7305924wme.37.1692688255756; Tue, 22 Aug 2023 00:10:55 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Song Gao Cc: Huacai Chen , Jiajie Chen , Xiaojuan Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 06/19] target/loongarch: Extract make_address_i() helper Date: Tue, 22 Aug 2023 09:09:59 +0200 Message-ID: <20230822071013.34884-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230822071013.34884-1-philmd@linaro.org> References: <20230822071013.34884-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1692688295109100001 From: Jiajie Chen Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/loongarch/translate.c | 6 ++++ .../loongarch/insn_trans/trans_atomic.c.inc | 5 +-- .../loongarch/insn_trans/trans_branch.c.inc | 3 +- .../loongarch/insn_trans/trans_fmemory.c.inc | 12 ++----- target/loongarch/insn_trans/trans_lsx.c.inc | 32 +++++-------------- .../loongarch/insn_trans/trans_memory.c.inc | 28 +++++----------- 6 files changed, 29 insertions(+), 57 deletions(-) diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index a68a979a55..acc54d7587 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -220,6 +220,12 @@ static TCGv make_address_x(DisasContext *ctx, TCGv bas= e, TCGv addend) return base; } =20 +static TCGv make_address_i(DisasContext *ctx, TCGv base, target_long ofs) +{ + TCGv addend =3D ofs ? tcg_constant_tl(ofs) : NULL; + return make_address_x(ctx, base, addend); +} + #include "decode-insns.c.inc" #include "insn_trans/trans_arith.c.inc" #include "insn_trans/trans_shift.c.inc" diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loonga= rch/insn_trans/trans_atomic.c.inc index 612709f2a7..fbc081448d 100644 --- a/target/loongarch/insn_trans/trans_atomic.c.inc +++ b/target/loongarch/insn_trans/trans_atomic.c.inc @@ -7,9 +7,8 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mo= p) { TCGv dest =3D gpr_dst(ctx, a->rd, EXT_NONE); TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); - TCGv t0 =3D tcg_temp_new(); + TCGv t0 =3D make_address_i(ctx, src1, a->imm); =20 - tcg_gen_addi_tl(t0, src1, a->imm); tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, mop); tcg_gen_st_tl(t0, cpu_env, offsetof(CPULoongArchState, lladdr)); tcg_gen_st_tl(dest, cpu_env, offsetof(CPULoongArchState, llval)); @@ -62,6 +61,8 @@ static bool gen_am(DisasContext *ctx, arg_rrr *a, return false; } =20 + addr =3D make_address_i(ctx, addr, 0); + func(dest, addr, val, ctx->mem_idx, mop); gen_set_gpr(a->rd, dest, EXT_NONE); =20 diff --git a/target/loongarch/insn_trans/trans_branch.c.inc b/target/loonga= rch/insn_trans/trans_branch.c.inc index a860f7e733..3ad34bcc05 100644 --- a/target/loongarch/insn_trans/trans_branch.c.inc +++ b/target/loongarch/insn_trans/trans_branch.c.inc @@ -23,7 +23,8 @@ static bool trans_jirl(DisasContext *ctx, arg_jirl *a) TCGv dest =3D gpr_dst(ctx, a->rd, EXT_NONE); TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); =20 - tcg_gen_addi_tl(cpu_pc, src1, a->imm); + TCGv addr =3D make_address_i(ctx, src1, a->imm); + tcg_gen_mov_tl(cpu_pc, addr); tcg_gen_movi_tl(dest, ctx->base.pc_next + 4); gen_set_gpr(a->rd, dest, EXT_NONE); tcg_gen_lookup_and_goto_ptr(); diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loong= arch/insn_trans/trans_fmemory.c.inc index 88ad209338..bd3aba2c49 100644 --- a/target/loongarch/insn_trans/trans_fmemory.c.inc +++ b/target/loongarch/insn_trans/trans_fmemory.c.inc @@ -17,11 +17,7 @@ static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, = MemOp mop) =20 CHECK_FPE; =20 - if (a->imm) { - TCGv temp =3D tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } + addr =3D make_address_i(ctx, addr, a->imm); =20 tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); maybe_nanbox_load(dest, mop); @@ -37,11 +33,7 @@ static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a,= MemOp mop) =20 CHECK_FPE; =20 - if (a->imm) { - TCGv temp =3D tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } + addr =3D make_address_i(ctx, addr, a->imm); =20 tcg_gen_qemu_st_tl(src, addr, ctx->mem_idx, mop); =20 diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch= /insn_trans/trans_lsx.c.inc index 875cb7d51d..50153d6d0b 100644 --- a/target/loongarch/insn_trans/trans_lsx.c.inc +++ b/target/loongarch/insn_trans/trans_lsx.c.inc @@ -4255,7 +4255,7 @@ TRANS(vextrins_d, gen_vv_i, gen_helper_vextrins_d) =20 static bool trans_vld(DisasContext *ctx, arg_vr_i *a) { - TCGv addr, temp; + TCGv addr; TCGv_i64 rl, rh; TCGv_i128 val; =20 @@ -4266,11 +4266,7 @@ static bool trans_vld(DisasContext *ctx, arg_vr_i *a) rl =3D tcg_temp_new_i64(); rh =3D tcg_temp_new_i64(); =20 - if (a->imm) { - temp =3D tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } + addr =3D make_address_i(ctx, addr, a->imm); =20 tcg_gen_qemu_ld_i128(val, addr, ctx->mem_idx, MO_128 | MO_TE); tcg_gen_extr_i128_i64(rl, rh, val); @@ -4282,7 +4278,7 @@ static bool trans_vld(DisasContext *ctx, arg_vr_i *a) =20 static bool trans_vst(DisasContext *ctx, arg_vr_i *a) { - TCGv addr, temp; + TCGv addr; TCGv_i128 val; TCGv_i64 ah, al; =20 @@ -4293,11 +4289,7 @@ static bool trans_vst(DisasContext *ctx, arg_vr_i *a) ah =3D tcg_temp_new_i64(); al =3D tcg_temp_new_i64(); =20 - if (a->imm) { - temp =3D tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } + addr =3D make_address_i(ctx, addr, a->imm); =20 get_vreg64(ah, a->vd, 1); get_vreg64(al, a->vd, 0); @@ -4356,7 +4348,7 @@ static bool trans_vstx(DisasContext *ctx, arg_vrr *a) #define VLDREPL(NAME, MO) \ static bool trans_## NAME (DisasContext *ctx, arg_vr_i *a) \ { \ - TCGv addr, temp; \ + TCGv addr; \ TCGv_i64 val; \ \ CHECK_SXE; \ @@ -4364,11 +4356,7 @@ static bool trans_## NAME (DisasContext *ctx, arg_vr= _i *a) \ addr =3D gpr_src(ctx, a->rj, EXT_NONE); = \ val =3D tcg_temp_new_i64(); = \ \ - if (a->imm) { \ - temp =3D tcg_temp_new(); = \ - tcg_gen_addi_tl(temp, addr, a->imm); \ - addr =3D temp; = \ - } \ + addr =3D make_address_i(ctx, addr, a->imm); = \ \ tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, MO); \ tcg_gen_gvec_dup_i64(MO, vec_full_offset(a->vd), 16, ctx->vl/8, val); \ @@ -4384,7 +4372,7 @@ VLDREPL(vldrepl_d, MO_64) #define VSTELM(NAME, MO, E) = \ static bool trans_## NAME (DisasContext *ctx, arg_vr_ii *a) = \ { = \ - TCGv addr, temp; = \ + TCGv addr; = \ TCGv_i64 val; = \ = \ CHECK_SXE; = \ @@ -4392,11 +4380,7 @@ static bool trans_## NAME (DisasContext *ctx, arg_vr= _ii *a) \ addr =3D gpr_src(ctx, a->rj, EXT_NONE); = \ val =3D tcg_temp_new_i64(); = \ = \ - if (a->imm) { = \ - temp =3D tcg_temp_new(); = \ - tcg_gen_addi_tl(temp, addr, a->imm); = \ - addr =3D temp; = \ - } = \ + addr =3D make_address_i(ctx, addr, a->imm); = \ = \ tcg_gen_ld_i64(val, cpu_env, = \ offsetof(CPULoongArchState, fpr[a->vd].vreg.E(a->imm2))= ); \ diff --git a/target/loongarch/insn_trans/trans_memory.c.inc b/target/loonga= rch/insn_trans/trans_memory.c.inc index ccebd0a4e0..88953f0ab0 100644 --- a/target/loongarch/insn_trans/trans_memory.c.inc +++ b/target/loongarch/insn_trans/trans_memory.c.inc @@ -8,11 +8,7 @@ static bool gen_load(DisasContext *ctx, arg_rr_i *a, MemOp= mop) TCGv dest =3D gpr_dst(ctx, a->rd, EXT_NONE); TCGv addr =3D gpr_src(ctx, a->rj, EXT_NONE); =20 - if (a->imm) { - TCGv temp =3D tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } + addr =3D make_address_i(ctx, addr, a->imm); =20 tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); gen_set_gpr(a->rd, dest, EXT_NONE); @@ -24,11 +20,7 @@ static bool gen_store(DisasContext *ctx, arg_rr_i *a, Me= mOp mop) TCGv data =3D gpr_src(ctx, a->rd, EXT_NONE); TCGv addr =3D gpr_src(ctx, a->rj, EXT_NONE); =20 - if (a->imm) { - TCGv temp =3D tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } + addr =3D make_address_i(ctx, addr, a->imm); =20 tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop); return true; @@ -66,6 +58,7 @@ static bool gen_load_gt(DisasContext *ctx, arg_rrr *a, Me= mOp mop) TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); =20 gen_helper_asrtgt_d(cpu_env, src1, src2); + src1 =3D make_address_i(ctx, src1, 0); tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop); gen_set_gpr(a->rd, dest, EXT_NONE); =20 @@ -79,6 +72,7 @@ static bool gen_load_le(DisasContext *ctx, arg_rrr *a, Me= mOp mop) TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); =20 gen_helper_asrtle_d(cpu_env, src1, src2); + src1 =3D make_address_i(ctx, src1, 0); tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop); gen_set_gpr(a->rd, dest, EXT_NONE); =20 @@ -92,6 +86,7 @@ static bool gen_store_gt(DisasContext *ctx, arg_rrr *a, M= emOp mop) TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); =20 gen_helper_asrtgt_d(cpu_env, src1, src2); + src1 =3D make_address_i(ctx, src1, 0); tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop); =20 return true; @@ -104,6 +99,7 @@ static bool gen_store_le(DisasContext *ctx, arg_rrr *a, = MemOp mop) TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); =20 gen_helper_asrtle_d(cpu_env, src1, src2); + src1 =3D make_address_i(ctx, src1, 0); tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop); =20 return true; @@ -131,11 +127,7 @@ static bool gen_ldptr(DisasContext *ctx, arg_rr_i *a, = MemOp mop) TCGv dest =3D gpr_dst(ctx, a->rd, EXT_NONE); TCGv addr =3D gpr_src(ctx, a->rj, EXT_NONE); =20 - if (a->imm) { - TCGv temp =3D tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } + addr =3D make_address_i(ctx, addr, a->imm); =20 tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); gen_set_gpr(a->rd, dest, EXT_NONE); @@ -147,11 +139,7 @@ static bool gen_stptr(DisasContext *ctx, arg_rr_i *a, = MemOp mop) TCGv data =3D gpr_src(ctx, a->rd, EXT_NONE); TCGv addr =3D gpr_src(ctx, a->rj, EXT_NONE); =20 - if (a->imm) { - TCGv temp =3D tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } + addr =3D make_address_i(ctx, addr, a->imm); =20 tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop); return true; --=20 2.41.0