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Tue, 22 Aug 2023 00:10:49 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Song Gao Cc: Huacai Chen , Jiajie Chen , Xiaojuan Yang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 05/19] target/loongarch: Extract make_address_x() helper Date: Tue, 22 Aug 2023 09:09:58 +0200 Message-ID: <20230822071013.34884-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230822071013.34884-1-philmd@linaro.org> References: <20230822071013.34884-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1692688298194100003 From: Jiajie Chen Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/loongarch/translate.c | 12 ++++++++++++ .../loongarch/insn_trans/trans_fmemory.c.inc | 18 ++++++------------ target/loongarch/insn_trans/trans_lsx.c.inc | 6 ++---- target/loongarch/insn_trans/trans_memory.c.inc | 6 ++---- 4 files changed, 22 insertions(+), 20 deletions(-) diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index ac847745df..a68a979a55 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -208,6 +208,18 @@ static void set_fpr(int reg_num, TCGv val) offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0))); } =20 +static TCGv make_address_x(DisasContext *ctx, TCGv base, TCGv addend) +{ + TCGv temp =3D NULL; + + if (addend) { + temp =3D tcg_temp_new(); + tcg_gen_add_tl(temp, base, addend); + base =3D temp; + } + return base; +} + #include "decode-insns.c.inc" #include "insn_trans/trans_arith.c.inc" #include "insn_trans/trans_shift.c.inc" diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loong= arch/insn_trans/trans_fmemory.c.inc index 91c09fb6d9..88ad209338 100644 --- a/target/loongarch/insn_trans/trans_fmemory.c.inc +++ b/target/loongarch/insn_trans/trans_fmemory.c.inc @@ -57,8 +57,7 @@ static bool gen_floadx(DisasContext *ctx, arg_frr *a, Mem= Op mop) =20 CHECK_FPE; =20 - addr =3D tcg_temp_new(); - tcg_gen_add_tl(addr, src1, src2); + addr =3D make_address_x(ctx, src1, src2); tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); maybe_nanbox_load(dest, mop); set_fpr(a->fd, dest); @@ -75,8 +74,7 @@ static bool gen_fstorex(DisasContext *ctx, arg_frr *a, Me= mOp mop) =20 CHECK_FPE; =20 - addr =3D tcg_temp_new(); - tcg_gen_add_tl(addr, src1, src2); + addr =3D make_address_x(ctx, src1, src2); tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop); =20 return true; @@ -91,9 +89,8 @@ static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, M= emOp mop) =20 CHECK_FPE; =20 - addr =3D tcg_temp_new(); gen_helper_asrtgt_d(cpu_env, src1, src2); - tcg_gen_add_tl(addr, src1, src2); + addr =3D make_address_x(ctx, src1, src2); tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); maybe_nanbox_load(dest, mop); set_fpr(a->fd, dest); @@ -110,9 +107,8 @@ static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a= , MemOp mop) =20 CHECK_FPE; =20 - addr =3D tcg_temp_new(); gen_helper_asrtgt_d(cpu_env, src1, src2); - tcg_gen_add_tl(addr, src1, src2); + addr =3D make_address_x(ctx, src1, src2); tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop); =20 return true; @@ -127,9 +123,8 @@ static bool gen_fload_le(DisasContext *ctx, arg_frr *a,= MemOp mop) =20 CHECK_FPE; =20 - addr =3D tcg_temp_new(); gen_helper_asrtle_d(cpu_env, src1, src2); - tcg_gen_add_tl(addr, src1, src2); + addr =3D make_address_x(ctx, src1, src2); tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); maybe_nanbox_load(dest, mop); set_fpr(a->fd, dest); @@ -146,9 +141,8 @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a= , MemOp mop) =20 CHECK_FPE; =20 - addr =3D tcg_temp_new(); gen_helper_asrtle_d(cpu_env, src1, src2); - tcg_gen_add_tl(addr, src1, src2); + addr =3D make_address_x(ctx, src1, src2); tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop); =20 return true; diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch= /insn_trans/trans_lsx.c.inc index 68779daff6..875cb7d51d 100644 --- a/target/loongarch/insn_trans/trans_lsx.c.inc +++ b/target/loongarch/insn_trans/trans_lsx.c.inc @@ -4315,14 +4315,13 @@ static bool trans_vldx(DisasContext *ctx, arg_vrr *= a) =20 CHECK_SXE; =20 - addr =3D tcg_temp_new(); src1 =3D gpr_src(ctx, a->rj, EXT_NONE); src2 =3D gpr_src(ctx, a->rk, EXT_NONE); val =3D tcg_temp_new_i128(); rl =3D tcg_temp_new_i64(); rh =3D tcg_temp_new_i64(); =20 - tcg_gen_add_tl(addr, src1, src2); + addr =3D make_address_x(ctx, src1, src2); tcg_gen_qemu_ld_i128(val, addr, ctx->mem_idx, MO_128 | MO_TE); tcg_gen_extr_i128_i64(rl, rh, val); set_vreg64(rh, a->vd, 1); @@ -4339,14 +4338,13 @@ static bool trans_vstx(DisasContext *ctx, arg_vrr *= a) =20 CHECK_SXE; =20 - addr =3D tcg_temp_new(); src1 =3D gpr_src(ctx, a->rj, EXT_NONE); src2 =3D gpr_src(ctx, a->rk, EXT_NONE); val =3D tcg_temp_new_i128(); ah =3D tcg_temp_new_i64(); al =3D tcg_temp_new_i64(); =20 - tcg_gen_add_tl(addr, src1, src2); + addr =3D make_address_x(ctx, src1, src2); get_vreg64(ah, a->vd, 1); get_vreg64(al, a->vd, 0); tcg_gen_concat_i64_i128(val, al, ah); diff --git a/target/loongarch/insn_trans/trans_memory.c.inc b/target/loonga= rch/insn_trans/trans_memory.c.inc index 75cfdf59ad..ccebd0a4e0 100644 --- a/target/loongarch/insn_trans/trans_memory.c.inc +++ b/target/loongarch/insn_trans/trans_memory.c.inc @@ -39,9 +39,8 @@ static bool gen_loadx(DisasContext *ctx, arg_rrr *a, MemO= p mop) TCGv dest =3D gpr_dst(ctx, a->rd, EXT_NONE); TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); - TCGv addr =3D tcg_temp_new(); + TCGv addr =3D make_address_x(ctx, src1, src2); =20 - tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); gen_set_gpr(a->rd, dest, EXT_NONE); =20 @@ -53,9 +52,8 @@ static bool gen_storex(DisasContext *ctx, arg_rrr *a, Mem= Op mop) TCGv data =3D gpr_src(ctx, a->rd, EXT_NONE); TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); - TCGv addr =3D tcg_temp_new(); + TCGv addr =3D make_address_x(ctx, src1, src2); =20 - tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop); =20 return true; --=20 2.41.0