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([2602:47:d483:7301:cf24:6daf:2b9e:7972]) by smtp.gmail.com with ESMTPSA id y7-20020a17090322c700b001bdb85291casm2231417plg.208.2023.08.18.15.13.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Aug 2023 15:13:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1692396819; x=1693001619; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y7y0D0sEaL0VTSukWCoFv1RFuNJvu9hO7InBuIwdRw4=; b=o94zIxRzh+E8UzkEVttPuwQ8pbhDgIKJAZPf3IvwL7qLiH9IOQpLmME2kLhsLfcTQc kkHFORx24pieNmRTdAFMcNv/zvTWSZ02FwmuHZk1hhhOdEGmYtAyOsQk9k1bOIkmyROb vXDnnwbTvqT4N23/3bMDxDLMlmg2Kb1fl6oi7vNjL09nVL2ARGj5cRCrx+Da1Svv3jYE v3eW3XqcRMzj2V4PucJDOqRnM+ggqjQQgK9i0751s8f0tzMrxKhFCRhJZspDrVHQfb0V l+cxdEbM/WUC9pLS+HB2dRWG3png17UHpr+qOFnJoIjJgGrbNI9Qgi4hYTGaNqXF7AVh 6BWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692396819; x=1693001619; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y7y0D0sEaL0VTSukWCoFv1RFuNJvu9hO7InBuIwdRw4=; b=QZS2h4ke2drrm0M8fz/ZPQWjT5D1pDBXPZ9vOHsVRrjtUU2Zpb1r0FjwjTOPOt2pt4 RXg/aV4c0udZ078gYUu8PNBCvcIs0edsae4vQPVwEeVG0wUWapbCBbx+l8Yh2yJTDMHC ZINbfTX/EC++/UewrKZ/z3rJoKZovGvfHvMQs2KwVx1u/1k4tfksqOD9LxsyM7cXnDOt Vl04sNHGQ5S7Ihgipu9yH/k01qtEI+n52AHWkCbAc9vAttQvaQoW964PocGSux33jeMi onkw0v6FDr9dyBGou/innzyvywVleb3/FmnGKyIaHx2YybOM9Wcy48E6TvEurE39WsCJ xgqQ== X-Gm-Message-State: AOJu0YypXOl+7STZhFlafBAemwQzUOQB0ZqkadH+U8Y0K+K7jR8rJHWo 8IsztAEKTqSmM7yBlt/R7ZtDAtNz69VNA3ZEHuM= X-Google-Smtp-Source: AGHT+IHlYfKFYKwkb7MGVxUQ5zMsX5T1k+UkdEYLoshSeoe0tjya46nhGERVaTqsFUPPFhsPI9Z7rA== X-Received: by 2002:a17:903:22cd:b0:1bb:2093:efb1 with SMTP id y13-20020a17090322cd00b001bb2093efb1mr628274plg.27.1692396819322; Fri, 18 Aug 2023 15:13:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PATCH v2 12/23] tcg/aarch64: Implement negsetcond_* Date: Fri, 18 Aug 2023 15:13:16 -0700 Message-Id: <20230818221327.150194-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230818221327.150194-1-richard.henderson@linaro.org> References: <20230818221327.150194-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1692397136366100009 Content-Type: text/plain; charset="utf-8" Trivial, as aarch64 has an instruction for this: CSETM. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 4 ++-- tcg/aarch64/tcg-target.c.inc | 12 ++++++++++++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 6080fddf73..e3faa9cff4 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -94,7 +94,7 @@ typedef enum { #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_extrl_i64_i32 0 #define TCG_TARGET_HAS_extrh_i64_i32 0 -#define TCG_TARGET_HAS_negsetcond_i32 0 +#define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 #define TCG_TARGET_HAS_div_i64 1 @@ -130,7 +130,7 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 -#define TCG_TARGET_HAS_negsetcond_i64 0 +#define TCG_TARGET_HAS_negsetcond_i64 1 =20 /* * Without FEAT_LSE2, we must use LDXP+STXP to implement atomic 128-bit lo= ad, diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 35ca80cd56..7d8d114c9e 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2262,6 +2262,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCG_REG_XZR, tcg_invert_cond(args[3])); break; =20 + case INDEX_op_negsetcond_i32: + a2 =3D (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_negsetcond_i64: + tcg_out_cmp(s, ext, a1, a2, c2); + /* Use CSETM alias of CSINV Wd, WZR, WZR, invert(cond). */ + tcg_out_insn(s, 3506, CSINV, ext, a0, TCG_REG_XZR, + TCG_REG_XZR, tcg_invert_cond(args[3])); + break; + case INDEX_op_movcond_i32: a2 =3D (int32_t)a2; /* FALLTHRU */ @@ -2868,6 +2878,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_sub_i64: case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: + case INDEX_op_negsetcond_i32: + case INDEX_op_negsetcond_i64: return C_O1_I2(r, r, rA); =20 case INDEX_op_mul_i32: --=20 2.34.1