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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::629; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20221208.gappssmtp.com) X-ZM-MESSAGEID: 1692330155442100001 riscv_trigger_init() had been called on reset events that can happen several times for a CPU and it allocated timers for itrigger. If old timers were present, they were simply overwritten by the new timers, resulting in a memory leak. Divide riscv_trigger_init() into two functions, namely riscv_trigger_realize() and riscv_trigger_reset() and call them in appropriate timing. The timer allocation will happen only once for a CPU in riscv_trigger_realize(). Fixes: 5a4ae64cac ("target/riscv: Add itrigger support when icount is enabl= ed") Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: LIU Zhiwei --- target/riscv/debug.h | 3 ++- target/riscv/cpu.c | 8 +++++++- target/riscv/debug.c | 15 ++++++++++++--- 3 files changed, 21 insertions(+), 5 deletions(-) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index c471748d5a..5794aa6ee5 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -143,7 +143,8 @@ void riscv_cpu_debug_excp_handler(CPUState *cs); bool riscv_cpu_debug_check_breakpoint(CPUState *cs); bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); =20 -void riscv_trigger_init(CPURISCVState *env); +void riscv_trigger_realize(CPURISCVState *env); +void riscv_trigger_reset_hold(CPURISCVState *env); =20 bool riscv_itrigger_enabled(CPURISCVState *env); void riscv_itrigger_update_priv(CPURISCVState *env); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e12b6ef7f6..7e0512dd5f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -904,7 +904,7 @@ static void riscv_cpu_reset_hold(Object *obj) =20 #ifndef CONFIG_USER_ONLY if (cpu->cfg.debug) { - riscv_trigger_init(env); + riscv_trigger_reset_hold(env); } =20 if (kvm_enabled()) { @@ -1475,6 +1475,12 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) =20 riscv_cpu_register_gdb_regs_for_features(cs); =20 +#ifndef CONFIG_USER_ONLY + if (cpu->cfg.debug) { + riscv_trigger_realize(&cpu->env); + } +#endif + qemu_init_vcpu(cs); cpu_reset(cs); =20 diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 75ee1c4971..ddd46b2d3e 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -903,7 +903,17 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CP= UWatchpoint *wp) return false; } =20 -void riscv_trigger_init(CPURISCVState *env) +void riscv_trigger_realize(CPURISCVState *env) +{ + int i; + + for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { + env->itrigger_timer[i] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + riscv_itrigger_timer_cb, env= ); + } +} + +void riscv_trigger_reset_hold(CPURISCVState *env) { target_ulong tdata1 =3D build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0); int i; @@ -928,7 +938,6 @@ void riscv_trigger_init(CPURISCVState *env) env->tdata3[i] =3D 0; env->cpu_breakpoint[i] =3D NULL; env->cpu_watchpoint[i] =3D NULL; - env->itrigger_timer[i] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, - riscv_itrigger_timer_cb, env= ); + timer_del(env->itrigger_timer[i]); } } --=20 2.41.0