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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id q9-20020a9d4b09000000b006b9f26b9b94sm5655668otf.28.2023.08.15.15.48.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 15:48:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692139686; x=1692744486; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=61rviudoS0tPwh5erQkA5DyOXPmz9WRzdOuGC0M2QpM=; b=QR/QIphGjmBNBtDc7jBpoC9rP1KIPJarq92uYFRfsSHx+MJaFL4ssGxeHbJNCRCE4g OaBZl2P2XwJkjeFGjxMq7YRx18bEvulP0puvoOpavjJQ6nJENIpR5cS4N2l+4cQY8Lh1 jsho5kNTh1jtgisiHm7Md1GlT3N17tiLFSIchyKT0dRC6QGEyKK1jp6gIAY26gBJW/ju 7su2z57ktK0eP+wyjODpKsynMUsHVwgd2n0u70YlTcZRUlN1h7Tt/74jKWSq8Uf06vtd 802cLk0EHfdUKjnpto1N3LH9eO3VcCzOq8OzUwZX6qJkzaJ4ABOXM0UV9CpBgx2eYaot YVjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692139686; x=1692744486; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=61rviudoS0tPwh5erQkA5DyOXPmz9WRzdOuGC0M2QpM=; b=ImqaoD9gNzU3jk5hBwxDFJninVL8pWlbE/2cWlRwkhFPybn+/ql5/Shg2g9xizrmPV esBdHa/TNg0lWFAaa1xAQTXshHy10Ad1qZsfk1/eImakh2kNu4QOwNMjdaBS/ebEHQzC L+OK3hO5LkdRYd1Z0gmvJ00pWSih7SJ+mkYKlWQBJ9geDM1bOb4lQ4WHT0i+MIC+mKH5 FtwDkWvf4k3g+Uu++h6vb7GfHZmiZ12gTmGBF2sz9ERbhOyBpuEzBVj7Xqh7AJlgseAG Z3z7ARjBmtv3uEhVivQYgS4jHYPndX/96HO/gHV6JyxRz6LykiAMzj53wW7R7jd8X7y1 ZkTA== X-Gm-Message-State: AOJu0Yy4P7xpRpySnQmX7M8NYd1lJ2mlg+PONM7V4VWitXBFtWgT0nTc T9q/ieBwi0C6mpIm+qyX2mTiXOFnYdUl60KIbK4= X-Google-Smtp-Source: AGHT+IEGa4iHbzPBRfHGOBEDgS7iBvwqGV27Qar95TfQXv1DSP0U7oS0lNP77mSEsuqxFc2L01gQHA== X-Received: by 2002:a9d:5a96:0:b0:6b8:b83c:a1f8 with SMTP id w22-20020a9d5a96000000b006b8b83ca1f8mr2075626oth.19.1692139686616; Tue, 15 Aug 2023 15:48:06 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v3 6/8] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions() Date: Tue, 15 Aug 2023 19:47:31 -0300 Message-ID: <20230815224733.434682-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815224733.434682-1-dbarboza@ventanamicro.com> References: <20230815224733.434682-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1692139754643100003 Content-Type: text/plain; charset="utf-8" Before adding support to detect if an extension was user set we need to handle how we're enabling extensions in riscv_init_max_cpu_extensions(). object_property_set_bool() calls the set() callback for the property, and we're going to use this callback to set the 'multi_ext_user_opts' hash. This means that, as is today, all extensions we're setting for the 'max' CPU will be seen as user set in the future. Let's change set_bool() to isa_ext_update_enabled() that will just enable/disable the flag on a certain offset. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f8be03a536..e24085fd64 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2101,24 +2101,24 @@ static void riscv_init_max_cpu_extensions(Object *o= bj) set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); =20 for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { - object_property_set_bool(obj, prop->name, true, NULL); + isa_ext_update_enabled(cpu, prop->offset, true); } =20 /* set vector version */ env->vext_ver =3D VEXT_VERSION_1_00_0; =20 /* Zfinx is not compatible with F. Disable it */ - object_property_set_bool(obj, "zfinx", false, NULL); - object_property_set_bool(obj, "zdinx", false, NULL); - object_property_set_bool(obj, "zhinx", false, NULL); - object_property_set_bool(obj, "zhinxmin", false, NULL); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); =20 - object_property_set_bool(obj, "zce", false, NULL); - object_property_set_bool(obj, "zcmp", false, NULL); - object_property_set_bool(obj, "zcmt", false, NULL); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); =20 if (env->misa_mxl !=3D MXL_RV32) { - object_property_set_bool(obj, "zcf", false, NULL); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); } } =20 --=20 2.41.0