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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id q9-20020a9d4b09000000b006b9f26b9b94sm5655668otf.28.2023.08.15.15.47.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 15:47:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692139678; x=1692744478; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/ptRsaNn0JKdnbBbzTMAAGNdMdbl9qxio1/dFLsmws8=; b=MU7MBAiuxuaPJGMrwGGqDk37tAKjkV4T9FPFaxcc1W10s8jsGtljzILvZ2Ciy5fHpI NwpzKtcit8p4zHkoHg565M0ndAbR6tWmxH43lgcvV/JldIZZJmNnfhXlvHiEzZbwW22N je6ronGQU7UycElEivB6FXXaOg/LZEJVkvf5v6imJIFGG8E9hJMXHgFwZZ7jAeUzoBmF 6Qt8fWNkrE+URqRyrCj/xATbqnhrgNZWt11t1GwPIAZez86hF9DrsOBbRXNoRcLRLOmp uP0skNrSAMbk6HqZs+BuBOBNeluSwYKas9h3hOCXxGw+ipr9tC2AV3mIxTCyQsyiMPnv 6vcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692139678; x=1692744478; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/ptRsaNn0JKdnbBbzTMAAGNdMdbl9qxio1/dFLsmws8=; b=gd6HTnAb2JukXr9QWtXQaFIKhpE7I8qLV/ZISvtDkiSx5dnnYhnzRis08qIwFDghYs JmY0npSKRAntgXOjKCtMZynkkgundWQTX0YZwKYAYd6o1kymHBhk0CjQAtXHBBPA961L QSaggLjsyY1h8L7K+a9uwKtMkdvjex0dfkrIAumUvv7j/R4p2DK+lNMyNu9hAvqf0aPG X8fv1Pyz7+FzsbA0oc9pUuqqTNJhu88PnYFF4ztWFlyc548WnUGKkFx9uVWj9jMsVVb/ q/Dko3B9JNeQPqFynNqvFqnfbF5jkCOIiykwDRackMOyoWGtelmLykwsaTWupXc+zuSA di1A== X-Gm-Message-State: AOJu0Yx2BZpYADqo1FKzjZjm7xX9bgK4l+doQrKUYqK+PYqjxQt5YSz7 2LyQnhb6up+eqh6UE/7HuHPt2gYpM+6wOKvcPAY= X-Google-Smtp-Source: AGHT+IGYOISG433K+fk/RZF+SelcPw862agP4c1Cp2vfM/oy1TiG4JHfcdi63dKg6CPzyPt1skOxBQ== X-Received: by 2002:a05:6830:4693:b0:6bc:f5b7:f1d with SMTP id ay19-20020a056830469300b006bcf5b70f1dmr42337otb.28.1692139677870; Tue, 15 Aug 2023 15:47:57 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v3 3/8] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update() Date: Tue, 15 Aug 2023 19:47:28 -0300 Message-ID: <20230815224733.434682-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815224733.434682-1-dbarboza@ventanamicro.com> References: <20230815224733.434682-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32f; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1692139732750100005 Content-Type: text/plain; charset="utf-8" During realize() time we're activating a lot of extensions based on some criteria, e.g.: if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn =3D true; cpu->cfg.ext_zkr =3D true; cpu->cfg.ext_zkt =3D true; } This practice resulted in at least one case where we ended up enabling something we shouldn't: RVC enabling zca/zcd/zcf when using a CPU that has priv_spec older than 1.12.0. We're also not considering user choice. There's no way of doing it now but this is about to change in the next few patches. cpu_cfg_ext_auto_update() will check for priv version mismatches before enabling extensions. If we have a mismatch between the current priv version and the extension we want to enable, do not enable it. In the near future, this same function will also consider user choice when deciding if we're going to enable/disable an extension or not. For now let's use it to handle zca/zcd/zcf enablement if RVC is enabled. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 44 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 249673600c..0c1964c853 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -166,6 +166,44 @@ static void isa_ext_update_enabled(RISCVCPU *cpu, uint= 32_t ext_offset, *ext_enabled =3D en; } =20 +static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { + if (isa_edata_arr[i].ext_enable_offset !=3D ext_offset) { + continue; + } + + return isa_edata_arr[i].min_version; + } + + /* Default to oldest priv spec if no match found */ + return PRIV_VERSION_1_10_0; +} + +static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, + bool value) +{ + CPURISCVState *env =3D &cpu->env; + bool prev_val =3D isa_ext_is_enabled(cpu, ext_offset); + int min_version; + + if (prev_val =3D=3D value) { + return; + } + + if (value && env->priv_ver !=3D PRIV_VERSION_LATEST) { + /* Do not enable it if priv_ver is older than min_version */ + min_version =3D cpu_cfg_ext_get_min_version(ext_offset); + if (env->priv_ver < min_version) { + return; + } + } + + isa_ext_update_enabled(cpu, ext_offset, value); +} + const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -1246,12 +1284,12 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cp= u, Error **errp) =20 /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ if (riscv_has_ext(env, RVC) && env->priv_ver >=3D PRIV_VERSION_1_12_0)= { - cpu->cfg.ext_zca =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { - cpu->cfg.ext_zcf =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } if (riscv_has_ext(env, RVD)) { - cpu->cfg.ext_zcd =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); } } =20 --=20 2.41.0