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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id q9-20020a9d4b09000000b006b9f26b9b94sm5655668otf.28.2023.08.15.15.47.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 15:47:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692139675; x=1692744475; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IhvcFkSQHfSP5xPDNX9zNDgeGBnjeRojAT1WX4lK2fk=; b=dsulog4HOh72Vnaw33Uie/A06xrv/vmXZnxi8fWBIUGZ8g4rXVRbEjCp1UyGGE2C2M UJpZt6u5xIJl6Whqu2OjAxt5nm8JAi6n4eKg+BEQpQEDR+J5Dp3SDv04QIrtcKI/tzIw O76sZoL+S7/JqOGaXO+bAzzS7ASS5SG5E1qGzhUBsYP3K2ySi19Gs/NGHzuwuXUR3giz FGDLbpukrCF8pyVNalNbfp+3s9U/hExTJjhFBLmy8O+QJEZ5jRCPOg9YyWtcr8RXsG8F ydL/Vlax35FlbuC8Hk6TPxRGRxod35FbsUsGPDv5J6p8U+7gfqUKoc8Dg3wZGESOXlUg K7RA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692139675; x=1692744475; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IhvcFkSQHfSP5xPDNX9zNDgeGBnjeRojAT1WX4lK2fk=; b=kwyaN4n6KMh6GB9cspe6x7del7ws7IrILBgofiG3iFphGGB5cEocbSiBrqvxMxwVzY HAV4AyfpAzPtOOgFPoEB3mQCbN1GvbHzbErycVx0hrToXiHj3vaP7qn2kDOfuk7CB29L 6cy9QJfieWoQ84daSPF4RIeFmYwsIEDNPyND41/6WagNybKlWy1NdCJ4dDOzlfQZmiqU Xqkudk+eBHZrf6jhPbGIm1S6jBwkmmo45NCkhmiOZCBxajlB66wZ/wBxLufY6HsuXjpY ByY/OAFUf7Jl0zWnLKuufQEGPNwJ2mrKh+kCGq2OjaSdNOemknFJ7xCHcw6DkI2dXSMN UtZg== X-Gm-Message-State: AOJu0Yx99DCRGhn4BzEz8NjfkLaANz839G+abfNsTzUGuerW9bvHSxOG zBVs/PjLuSuZuJYxkAMAquiV4wLm9XhcT7qFSlU= X-Google-Smtp-Source: AGHT+IF0w0x9oCrO7T0oB5VX1u/Hr35ZKwhnv3tt42UVf+32WVyE/dTUBV993QcKEuwcNrinauzjWA== X-Received: by 2002:a9d:6b10:0:b0:6bc:fa76:f150 with SMTP id g16-20020a9d6b10000000b006bcfa76f150mr226856otp.12.1692139674906; Tue, 15 Aug 2023 15:47:54 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v3 2/8] target/riscv: make CPUCFG() macro public Date: Tue, 15 Aug 2023 19:47:27 -0300 Message-ID: <20230815224733.434682-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815224733.434682-1-dbarboza@ventanamicro.com> References: <20230815224733.434682-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1692139710959100003 Content-Type: text/plain; charset="utf-8" The RISC-V KVM driver uses a CPUCFG() macro that calculates the offset of a certain field in the struct RISCVCPUConfig. We're going to use this macro in target/riscv/cpu.c as well in the next patches. Make it public. Rename it to CPU_CFG_OFFSET() for more clarity while we're at it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 ++ target/riscv/kvm.c | 8 +++----- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 26d1acdf04..249673600c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -48,7 +48,7 @@ struct isa_ext_data { }; =20 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ - {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} + {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} =20 /* * From vector_helper.c diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6ea22e0eea..577abcd724 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -62,6 +62,8 @@ const char *riscv_get_misa_ext_name(uint32_t bit); const char *riscv_get_misa_ext_description(uint32_t bit); =20 +#define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) + /* Privileged specification version */ enum { PRIV_VERSION_1_10_0 =3D 0, diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index b1fd2233c0..c16b7fe3c7 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -198,10 +198,8 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cp= u, CPUState *cs) } } =20 -#define CPUCFG(_prop) offsetof(struct RISCVCPUConfig, _prop) - #define KVM_EXT_CFG(_name, _prop, _reg_id) \ - {.name =3D _name, .offset =3D CPUCFG(_prop), \ + {.name =3D _name, .offset =3D CPU_CFG_OFFSET(_prop), \ .kvm_reg_id =3D _reg_id} =20 static KVMCPUConfig kvm_multi_ext_cfgs[] =3D { @@ -278,13 +276,13 @@ static void kvm_cpu_set_multi_ext_cfg(Object *obj, Vi= sitor *v, =20 static KVMCPUConfig kvm_cbom_blocksize =3D { .name =3D "cbom_blocksize", - .offset =3D CPUCFG(cbom_blocksize), + .offset =3D CPU_CFG_OFFSET(cbom_blocksize), .kvm_reg_id =3D KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) }; =20 static KVMCPUConfig kvm_cboz_blocksize =3D { .name =3D "cboz_blocksize", - .offset =3D CPUCFG(cboz_blocksize), + .offset =3D CPU_CFG_OFFSET(cboz_blocksize), .kvm_reg_id =3D KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) }; =20 --=20 2.41.0