From nobody Sat May 18 04:30:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1692139779; cv=none; d=zohomail.com; s=zohoarc; b=NF3ttJUpe1AU4X0Oa5bvIViMubXPIVZ7zVpilEJ79hbTD6IAW2u3CUTk4JDhCVykSMmxJ4JCs4Jlus+FP0+f43rFA88pdscq88ginpGiM8IFQ7jTKeEkZD8MSUGmj/hPENBgYsIR3RDU8WHoX/0N5K5i25uE4/J2QJ2DnJ+x0sI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1692139779; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wt4H+c9A1AA7nxzTApReJL6p9dR9+sJsdIunenyUh08=; b=elL4buDe347zvu391ajRweBDt7/uAO3q+iblFBwwIlneSO9D9m2Si//8Ystwsy086402BNg1qBNMtTIesIa55xRhg79RPpXsC5ZCW6OkMMLSNzGPgTlsEys8KQdXa3TmMnl0MnsDL9sn/KOhQFVN4cm/8eBLUHI3srnKo3/2PJA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1692139779142506.8061066436712; Tue, 15 Aug 2023 15:49:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qW2pX-0006kf-UE; Tue, 15 Aug 2023 18:48:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qW2pX-0006k9-4F for qemu-devel@nongnu.org; Tue, 15 Aug 2023 18:48:03 -0400 Received: from mail-ot1-x32f.google.com ([2607:f8b0:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qW2pU-0008FU-Sy for qemu-devel@nongnu.org; Tue, 15 Aug 2023 18:48:02 -0400 Received: by mail-ot1-x32f.google.com with SMTP id 46e09a7af769-6bd0425ad4fso4951883a34.2 for ; Tue, 15 Aug 2023 15:47:52 -0700 (PDT) Received: from grind.. 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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id q9-20020a9d4b09000000b006b9f26b9b94sm5655668otf.28.2023.08.15.15.47.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 15:47:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692139671; x=1692744471; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wt4H+c9A1AA7nxzTApReJL6p9dR9+sJsdIunenyUh08=; b=X2/xRLj/8OsT8vZDXL4YUyjQouDzUNBv3BQUoGNN9UGvpf1jvPXD0nF2hxIDvO7k0I /IgQ2IoHVr0pw3kk0Z5h/Bdg2WuRHn/Xqa1RBSZsZZQuV0jinS9mqO6DEXxNDYb8Nlrx ++HAVRi6YkyiapSwoWfDW/XcqK9Vj9MdRVm6SindtFb+OuGLqdcq+PGkpRKOQnFGLFVL iJuZ4I5GbAG8r36p8qeDmfvypRT+5KvKGaZ7VUNNOn6Ca9HAxG3pNIsm23BLyqNZwAod LAOi4KjjEh/Ls2dxWxgrSLd8An1UPXWURyialu0bx9RreZAIf9vlCWRBTKbBseOHUkCP +qpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692139671; x=1692744471; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wt4H+c9A1AA7nxzTApReJL6p9dR9+sJsdIunenyUh08=; b=doyTlfSkI1Ag652+MSE1FgCmY8VnsAIzABhspFEDuYr2VoX+yETx+mLbAStUusTYqC 0Ld2b+Szt6pTVQU3XE+Up7tW5d7TgsOQV/9a+hSVS4ZKQVxo6tSxqt4FEM1vJIswP3l7 0G8fyA/biHgAQX6WG7Y2NzafSMiqPaDGHO73TKBJfETIQhgJ0cp4UKZBIrjj3aGkoVsu /5dgUH6EXhO6SbZnP+xb5KkJT2oyOoG3rUlJ5rO2PxWJzAMBpjAGUl3SWxH4ZfWxiI0W ql6aHfAAT4Oz43I/ZB2mwGGAv3z+cXwogSkNehnf7pvY6vrilmPYZ3U8iVwmB7mZhIsD yT+g== X-Gm-Message-State: AOJu0YxseqVhMaKaIY6Aeg4G7toZwEqef6qvvDvXNHxFpByMjsPr6GZ7 C/f9hqPm7e+zqqdtHpE1NLPowPCCD8lhBbjy+vI= X-Google-Smtp-Source: AGHT+IHTf7+33tmFLa7FypQHZVc8gXSRRL+gX2YMTwt1l3xFUfeWpx1xSs8MSXL3l1K2MeIvCMcUhQ== X-Received: by 2002:a9d:7dcb:0:b0:6b2:ac44:bf8e with SMTP id k11-20020a9d7dcb000000b006b2ac44bf8emr83758otn.8.1692139671680; Tue, 15 Aug 2023 15:47:51 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v3 1/8] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled Date: Tue, 15 Aug 2023 19:47:26 -0300 Message-ID: <20230815224733.434682-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815224733.434682-1-dbarboza@ventanamicro.com> References: <20230815224733.434682-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32f; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1692139780735100003 Content-Type: text/plain; charset="utf-8" We'll have future usage for a function where, given an offset of the struct RISCVCPUConfig, the flag is updated to a certain val. Change all existing callers to use edata->ext_enable_offset instead of 'edata'. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 59bd37e033..26d1acdf04 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -151,18 +151,17 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaC= ondOps), }; =20 -static bool isa_ext_is_enabled(RISCVCPU *cpu, - const struct isa_ext_data *edata) +static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) { - bool *ext_enabled =3D (void *)&cpu->cfg + edata->ext_enable_offset; + bool *ext_enabled =3D (void *)&cpu->cfg + ext_offset; =20 return *ext_enabled; } =20 -static void isa_ext_update_enabled(RISCVCPU *cpu, - const struct isa_ext_data *edata, bool = en) +static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, + bool en) { - bool *ext_enabled =3D (void *)&cpu->cfg + edata->ext_enable_offset; + bool *ext_enabled =3D (void *)&cpu->cfg + ext_offset; =20 *ext_enabled =3D en; } @@ -1023,9 +1022,10 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RIS= CVCPU *cpu) =20 /* Force disable extensions if priv spec version does not match */ for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && + if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) && (env->priv_ver < isa_edata_arr[i].min_version)) { - isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); + isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset, + false); #ifndef CONFIG_USER_ONLY warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx " because privilege spec version does not match", @@ -2274,7 +2274,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char = **isa_str, int i; =20 for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { + if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) { new =3D g_strconcat(old, "_", isa_edata_arr[i].name, NULL); g_free(old); old =3D new; --=20 2.41.0 From nobody Sat May 18 04:30:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1692139708; cv=none; d=zohomail.com; s=zohoarc; b=GBlj0LIAn4GtDpkj3nf4foz/VqtOMtVycveIDW/a5Bdy6v0IeiS0VpjkwlPF/tjH460+osZTqcX05XDyYncfxpJtLgorMO+9+FU9vgYIO7AUroLYro9xkTzl+bn4pK0C1ta5PYsp34mr4B4+JXptbuXAgWs7OnbDh/YKAunyjVY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1692139708; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IhvcFkSQHfSP5xPDNX9zNDgeGBnjeRojAT1WX4lK2fk=; b=ikRJBKV3z1Y9iZ+sL4tY6WctAqSgp3mjycgrLhvnEu3/9GWS/boiosb8ipdgc4YupjsdShTbTKQ90k7fg5+/VGwYOToDIfFUu0e0yJe1MI6sFWa3pQwzo1M1SVQJg6oHSelrj9Vfh3w/JLAC8Z6Govo7iI95gKQB+r2vO9D5ieo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1692139708320500.13372593424424; Tue, 15 Aug 2023 15:48:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qW2pa-0006mQ-S6; Tue, 15 Aug 2023 18:48:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qW2pZ-0006kv-8y for qemu-devel@nongnu.org; Tue, 15 Aug 2023 18:48:05 -0400 Received: from mail-ot1-x32a.google.com ([2607:f8b0:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qW2pU-0008Fo-Uh for qemu-devel@nongnu.org; Tue, 15 Aug 2023 18:48:05 -0400 Received: by mail-ot1-x32a.google.com with SMTP id 46e09a7af769-6bcb15aa074so3565232a34.0 for ; Tue, 15 Aug 2023 15:47:55 -0700 (PDT) Received: from grind.. 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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id q9-20020a9d4b09000000b006b9f26b9b94sm5655668otf.28.2023.08.15.15.47.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 15:47:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692139675; x=1692744475; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IhvcFkSQHfSP5xPDNX9zNDgeGBnjeRojAT1WX4lK2fk=; b=dsulog4HOh72Vnaw33Uie/A06xrv/vmXZnxi8fWBIUGZ8g4rXVRbEjCp1UyGGE2C2M UJpZt6u5xIJl6Whqu2OjAxt5nm8JAi6n4eKg+BEQpQEDR+J5Dp3SDv04QIrtcKI/tzIw O76sZoL+S7/JqOGaXO+bAzzS7ASS5SG5E1qGzhUBsYP3K2ySi19Gs/NGHzuwuXUR3giz FGDLbpukrCF8pyVNalNbfp+3s9U/hExTJjhFBLmy8O+QJEZ5jRCPOg9YyWtcr8RXsG8F ydL/Vlax35FlbuC8Hk6TPxRGRxod35FbsUsGPDv5J6p8U+7gfqUKoc8Dg3wZGESOXlUg K7RA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692139675; x=1692744475; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IhvcFkSQHfSP5xPDNX9zNDgeGBnjeRojAT1WX4lK2fk=; b=kwyaN4n6KMh6GB9cspe6x7del7ws7IrILBgofiG3iFphGGB5cEocbSiBrqvxMxwVzY HAV4AyfpAzPtOOgFPoEB3mQCbN1GvbHzbErycVx0hrToXiHj3vaP7qn2kDOfuk7CB29L 6cy9QJfieWoQ84daSPF4RIeFmYwsIEDNPyND41/6WagNybKlWy1NdCJ4dDOzlfQZmiqU Xqkudk+eBHZrf6jhPbGIm1S6jBwkmmo45NCkhmiOZCBxajlB66wZ/wBxLufY6HsuXjpY ByY/OAFUf7Jl0zWnLKuufQEGPNwJ2mrKh+kCGq2OjaSdNOemknFJ7xCHcw6DkI2dXSMN UtZg== X-Gm-Message-State: AOJu0Yx99DCRGhn4BzEz8NjfkLaANz839G+abfNsTzUGuerW9bvHSxOG zBVs/PjLuSuZuJYxkAMAquiV4wLm9XhcT7qFSlU= X-Google-Smtp-Source: AGHT+IF0w0x9oCrO7T0oB5VX1u/Hr35ZKwhnv3tt42UVf+32WVyE/dTUBV993QcKEuwcNrinauzjWA== X-Received: by 2002:a9d:6b10:0:b0:6bc:fa76:f150 with SMTP id g16-20020a9d6b10000000b006bcfa76f150mr226856otp.12.1692139674906; Tue, 15 Aug 2023 15:47:54 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v3 2/8] target/riscv: make CPUCFG() macro public Date: Tue, 15 Aug 2023 19:47:27 -0300 Message-ID: <20230815224733.434682-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815224733.434682-1-dbarboza@ventanamicro.com> References: <20230815224733.434682-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1692139710959100003 Content-Type: text/plain; charset="utf-8" The RISC-V KVM driver uses a CPUCFG() macro that calculates the offset of a certain field in the struct RISCVCPUConfig. We're going to use this macro in target/riscv/cpu.c as well in the next patches. Make it public. Rename it to CPU_CFG_OFFSET() for more clarity while we're at it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 ++ target/riscv/kvm.c | 8 +++----- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 26d1acdf04..249673600c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -48,7 +48,7 @@ struct isa_ext_data { }; =20 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ - {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} + {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} =20 /* * From vector_helper.c diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6ea22e0eea..577abcd724 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -62,6 +62,8 @@ const char *riscv_get_misa_ext_name(uint32_t bit); const char *riscv_get_misa_ext_description(uint32_t bit); =20 +#define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) + /* Privileged specification version */ enum { PRIV_VERSION_1_10_0 =3D 0, diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index b1fd2233c0..c16b7fe3c7 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -198,10 +198,8 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cp= u, CPUState *cs) } } =20 -#define CPUCFG(_prop) offsetof(struct RISCVCPUConfig, _prop) - #define KVM_EXT_CFG(_name, _prop, _reg_id) \ - {.name =3D _name, .offset =3D CPUCFG(_prop), \ + {.name =3D _name, .offset =3D CPU_CFG_OFFSET(_prop), \ .kvm_reg_id =3D _reg_id} =20 static KVMCPUConfig kvm_multi_ext_cfgs[] =3D { @@ -278,13 +276,13 @@ static void kvm_cpu_set_multi_ext_cfg(Object *obj, Vi= sitor *v, =20 static KVMCPUConfig kvm_cbom_blocksize =3D { .name =3D "cbom_blocksize", - .offset =3D CPUCFG(cbom_blocksize), + .offset =3D CPU_CFG_OFFSET(cbom_blocksize), .kvm_reg_id =3D KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) }; =20 static KVMCPUConfig kvm_cboz_blocksize =3D { .name =3D "cboz_blocksize", - .offset =3D CPUCFG(cboz_blocksize), + .offset =3D CPU_CFG_OFFSET(cboz_blocksize), .kvm_reg_id =3D KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) }; =20 --=20 2.41.0 From nobody Sat May 18 04:30:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1692139732; cv=none; d=zohomail.com; s=zohoarc; b=iUzbFIjUWV4ikgOygCXc2E47PoaaTKPLWnqYtfFuVZ9vDTEYaCn6OAN2GibDOywN+P8b8zw3mtAG15D1H/lrVMbLZzEaHqPaZJq/inmN5GkqEqoIYDJrXdBq9dyaF8Hx8qNaFjjwdxShtM9XLqqknQ0Qj4q23hr3OMvrnT1xMiY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1692139732; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/ptRsaNn0JKdnbBbzTMAAGNdMdbl9qxio1/dFLsmws8=; b=WdFEBzqWVh5FuwN3zCtKtrzhcJfTeBE/po0NH7SJ3+VBUaKD5MWUlETVFd7RIHX4klqRjzc3ke9ZvuZ23Z13Uj+tEm8fYueqgy9KvGAZatvoIg7q2MINItCYVWMYyJs91jmNIPlaIfs3ZlGNq9qtFdP2TQ+t4k8/CedaLUFfEUk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1692139732001620.5573589931697; Tue, 15 Aug 2023 15:48:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qW2pa-0006mb-UW; Tue, 15 Aug 2023 18:48:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qW2pZ-0006ky-Aw for qemu-devel@nongnu.org; Tue, 15 Aug 2023 18:48:05 -0400 Received: from mail-ot1-x32f.google.com ([2607:f8b0:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qW2pU-0008G4-U1 for qemu-devel@nongnu.org; Tue, 15 Aug 2023 18:48:05 -0400 Received: by mail-ot1-x32f.google.com with SMTP id 46e09a7af769-6bd0a0a6766so4722228a34.2 for ; Tue, 15 Aug 2023 15:47:58 -0700 (PDT) Received: from grind.. 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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id q9-20020a9d4b09000000b006b9f26b9b94sm5655668otf.28.2023.08.15.15.47.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 15:47:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692139678; x=1692744478; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/ptRsaNn0JKdnbBbzTMAAGNdMdbl9qxio1/dFLsmws8=; b=MU7MBAiuxuaPJGMrwGGqDk37tAKjkV4T9FPFaxcc1W10s8jsGtljzILvZ2Ciy5fHpI NwpzKtcit8p4zHkoHg565M0ndAbR6tWmxH43lgcvV/JldIZZJmNnfhXlvHiEzZbwW22N je6ronGQU7UycElEivB6FXXaOg/LZEJVkvf5v6imJIFGG8E9hJMXHgFwZZ7jAeUzoBmF 6Qt8fWNkrE+URqRyrCj/xATbqnhrgNZWt11t1GwPIAZez86hF9DrsOBbRXNoRcLRLOmp uP0skNrSAMbk6HqZs+BuBOBNeluSwYKas9h3hOCXxGw+ipr9tC2AV3mIxTCyQsyiMPnv 6vcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692139678; x=1692744478; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/ptRsaNn0JKdnbBbzTMAAGNdMdbl9qxio1/dFLsmws8=; b=gd6HTnAb2JukXr9QWtXQaFIKhpE7I8qLV/ZISvtDkiSx5dnnYhnzRis08qIwFDghYs JmY0npSKRAntgXOjKCtMZynkkgundWQTX0YZwKYAYd6o1kymHBhk0CjQAtXHBBPA961L QSaggLjsyY1h8L7K+a9uwKtMkdvjex0dfkrIAumUvv7j/R4p2DK+lNMyNu9hAvqf0aPG X8fv1Pyz7+FzsbA0oc9pUuqqTNJhu88PnYFF4ztWFlyc548WnUGKkFx9uVWj9jMsVVb/ q/Dko3B9JNeQPqFynNqvFqnfbF5jkCOIiykwDRackMOyoWGtelmLykwsaTWupXc+zuSA di1A== X-Gm-Message-State: AOJu0Yx2BZpYADqo1FKzjZjm7xX9bgK4l+doQrKUYqK+PYqjxQt5YSz7 2LyQnhb6up+eqh6UE/7HuHPt2gYpM+6wOKvcPAY= X-Google-Smtp-Source: AGHT+IGYOISG433K+fk/RZF+SelcPw862agP4c1Cp2vfM/oy1TiG4JHfcdi63dKg6CPzyPt1skOxBQ== X-Received: by 2002:a05:6830:4693:b0:6bc:f5b7:f1d with SMTP id ay19-20020a056830469300b006bcf5b70f1dmr42337otb.28.1692139677870; Tue, 15 Aug 2023 15:47:57 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v3 3/8] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update() Date: Tue, 15 Aug 2023 19:47:28 -0300 Message-ID: <20230815224733.434682-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815224733.434682-1-dbarboza@ventanamicro.com> References: <20230815224733.434682-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32f; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1692139732750100005 Content-Type: text/plain; charset="utf-8" During realize() time we're activating a lot of extensions based on some criteria, e.g.: if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn =3D true; cpu->cfg.ext_zkr =3D true; cpu->cfg.ext_zkt =3D true; } This practice resulted in at least one case where we ended up enabling something we shouldn't: RVC enabling zca/zcd/zcf when using a CPU that has priv_spec older than 1.12.0. We're also not considering user choice. There's no way of doing it now but this is about to change in the next few patches. cpu_cfg_ext_auto_update() will check for priv version mismatches before enabling extensions. If we have a mismatch between the current priv version and the extension we want to enable, do not enable it. In the near future, this same function will also consider user choice when deciding if we're going to enable/disable an extension or not. For now let's use it to handle zca/zcd/zcf enablement if RVC is enabled. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 44 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 249673600c..0c1964c853 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -166,6 +166,44 @@ static void isa_ext_update_enabled(RISCVCPU *cpu, uint= 32_t ext_offset, *ext_enabled =3D en; } =20 +static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { + if (isa_edata_arr[i].ext_enable_offset !=3D ext_offset) { + continue; + } + + return isa_edata_arr[i].min_version; + } + + /* Default to oldest priv spec if no match found */ + return PRIV_VERSION_1_10_0; +} + +static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, + bool value) +{ + CPURISCVState *env =3D &cpu->env; + bool prev_val =3D isa_ext_is_enabled(cpu, ext_offset); + int min_version; + + if (prev_val =3D=3D value) { + return; + } + + if (value && env->priv_ver !=3D PRIV_VERSION_LATEST) { + /* Do not enable it if priv_ver is older than min_version */ + min_version =3D cpu_cfg_ext_get_min_version(ext_offset); + if (env->priv_ver < min_version) { + return; + } + } + + isa_ext_update_enabled(cpu, ext_offset, value); +} + const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -1246,12 +1284,12 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cp= u, Error **errp) =20 /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ if (riscv_has_ext(env, RVC) && env->priv_ver >=3D PRIV_VERSION_1_12_0)= { - cpu->cfg.ext_zca =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { - cpu->cfg.ext_zcf =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } if (riscv_has_ext(env, RVD)) { - cpu->cfg.ext_zcd =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); } } =20 --=20 2.41.0 From nobody Sat May 18 04:30:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1692139753; cv=none; d=zohomail.com; s=zohoarc; b=EhKGdw1Z0h7qfkyk0zqVABEDdEmuRHwFDMCr84Gy1VQhnz6hR5HMdiuLrP1H9OptmD9ntSRzHSax9S0xh5qsAI9BYOHdKEYSgZzVo41TcL9eO6Y4ucxZCic2fEHUrOLtHnC5uDf6l+4FDmjMoKS6N4yif/SJOw1HK1rahOgVGQg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1692139753; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KhXyGoI8uLke9BRy7WQmyJDuGcQ9S6S/HCp56DZjxuU=; b=dVFCHdSfFyLMVa1ojl0P7JiRsadLvGXj20jKmVCljnkqev4piTFHKmOjI6cD5OluA1kKBeZqyRl02T9IFyYwcDi+tSeMmaUQh06q0Aw/kGFx0j8B1SaxZ4tuK1Q1cdbuCjgce3YCYz1JBfI08vpzesTZqRpesf5t778vTDupLSw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1692139753179371.5197723440782; Tue, 15 Aug 2023 15:49:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qW2pc-0006nS-RY; Tue, 15 Aug 2023 18:48:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qW2pb-0006mj-F9 for qemu-devel@nongnu.org; Tue, 15 Aug 2023 18:48:07 -0400 Received: from mail-ot1-x32d.google.com ([2607:f8b0:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qW2pW-0008GT-76 for qemu-devel@nongnu.org; Tue, 15 Aug 2023 18:48:07 -0400 Received: by mail-ot1-x32d.google.com with SMTP id 46e09a7af769-6bca6c06e56so5145692a34.1 for ; Tue, 15 Aug 2023 15:48:01 -0700 (PDT) Received: from grind.. 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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id q9-20020a9d4b09000000b006b9f26b9b94sm5655668otf.28.2023.08.15.15.47.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 15:48:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692139681; x=1692744481; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KhXyGoI8uLke9BRy7WQmyJDuGcQ9S6S/HCp56DZjxuU=; b=gylGvHZn0fzTu2kcAe39o0IlbMB5YyYpyazu5NmGPukuElfCunW9ILUVFADUBZ38nt YKjtv+k/HNhE+0D/YYsLRLrRhbi7EEQ/0Moq36ZhaV/y3ihgeeEaRPvi+EOtoHKmGdmk 12wJYQ/g4bMrubvHR94ZQbUSirULc1BcDaq60hyVnggSQVmp7DhvwdsJxSocbxYasb8l EWZPQZskgcEQxX1xvmNAcn4mCBdng27bda4Jo7DBVqWzBoUuxTCSMTY6RM+MtL7TgVt+ KEl0tFRDIdKLI4KdiFK9dAy/4lAGJZJk86waXFs7m4XWw2SQRoRZj9KtLdrhsA8PkO43 X85g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692139681; x=1692744481; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KhXyGoI8uLke9BRy7WQmyJDuGcQ9S6S/HCp56DZjxuU=; b=Xo58dybnNYwcOW8R96CNWkDDVtcgm2BSwE/ZQFR1exu7RxNtdpjbFrOy3Hr2Wgndjm Nny0eiZJVB7Gz6EeQk4Ildz576xDJ23C7rivlGnvpIduRjV+cGJYpQjWydIE9sXNRalh zUIIL59TEP09I6Wkl8R+qqVl0ya1WxOb7huV3cfc9mEJROFBCR1Y1XeHt+2GG5BApCLi C1Nyug7ZzDpQajK1V0Dbo86o98BUy1MZ29Qzof02ku9+vGCPheLXkVFDa9OwBy4blg4E 6d2ExyH5PP3q8WwM3hMybOaVQIX27XGDWm9uxvx9rb2rHoDJnRrx1eczhltdCG6QvLOW rp5Q== X-Gm-Message-State: AOJu0YyG+fMfTPcXn9o6T3eKnwvuu9Sbo8UZoqoHFRaXY+sOaf5WnPty UUiy1sTYZiPVc+JeO68fglUI9YSNxZoWBUsalLQ= X-Google-Smtp-Source: AGHT+IF3rgBdloIV+9nZag+BUF4Se8rVBhsSnHb2TX9Iu9x0jRa55bufBm/IWxfHNKuS5/b5A5l/ZA== X-Received: by 2002:a9d:6ad7:0:b0:6af:7760:f2d0 with SMTP id m23-20020a9d6ad7000000b006af7760f2d0mr74840otq.32.1692139680729; Tue, 15 Aug 2023 15:48:00 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v3 4/8] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize() Date: Tue, 15 Aug 2023 19:47:29 -0300 Message-ID: <20230815224733.434682-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815224733.434682-1-dbarboza@ventanamicro.com> References: <20230815224733.434682-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32d; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1692139754899100005 Content-Type: text/plain; charset="utf-8" Let's change the other instances in realize() where we're enabling an extension based on a certain criteria (e.g. it's a dependency of another extension). We're leaving icsr and ifencei being enabled during RVG for later - we'll want to error out in that case. Every other extension enablement during realize is now done via cpu_cfg_ext_auto_update(). The end goal is that only cpu init() functions will handle extension flags directly via "cpu->cfg.ext_N =3D true|false". Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 50 +++++++++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0c1964c853..f8f0b8f2c9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1172,7 +1172,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) } =20 if (cpu->cfg.ext_zfh) { - cpu->cfg.ext_zfhmin =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true); } =20 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { @@ -1198,17 +1198,17 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cp= u, Error **errp) } =20 /* The V vector extension depends on the Zve64d extension */ - cpu->cfg.ext_zve64d =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true); } =20 /* The Zve64d extension depends on the Zve64f extension */ if (cpu->cfg.ext_zve64d) { - cpu->cfg.ext_zve64f =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true); } =20 /* The Zve64f extension depends on the Zve32f extension */ if (cpu->cfg.ext_zve64f) { - cpu->cfg.ext_zve32f =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true); } =20 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { @@ -1222,7 +1222,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) } =20 if (cpu->cfg.ext_zvfh) { - cpu->cfg.ext_zvfhmin =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true); } =20 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { @@ -1252,7 +1252,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) =20 /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_zhinx) { - cpu->cfg.ext_zhinxmin =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); } =20 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfi= nx) { @@ -1273,12 +1273,12 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cp= u, Error **errp) } =20 if (cpu->cfg.ext_zce) { - cpu->cfg.ext_zca =3D true; - cpu->cfg.ext_zcb =3D true; - cpu->cfg.ext_zcmp =3D true; - cpu->cfg.ext_zcmt =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { - cpu->cfg.ext_zcf =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } } =20 @@ -1327,26 +1327,26 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cp= u, Error **errp) } =20 if (cpu->cfg.ext_zk) { - cpu->cfg.ext_zkn =3D true; - cpu->cfg.ext_zkr =3D true; - cpu->cfg.ext_zkt =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true); } =20 if (cpu->cfg.ext_zkn) { - cpu->cfg.ext_zbkb =3D true; - cpu->cfg.ext_zbkc =3D true; - cpu->cfg.ext_zbkx =3D true; - cpu->cfg.ext_zkne =3D true; - cpu->cfg.ext_zknd =3D true; - cpu->cfg.ext_zknh =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true); } =20 if (cpu->cfg.ext_zks) { - cpu->cfg.ext_zbkb =3D true; - cpu->cfg.ext_zbkc =3D true; - cpu->cfg.ext_zbkx =3D true; - cpu->cfg.ext_zksed =3D true; - cpu->cfg.ext_zksh =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true); 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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id q9-20020a9d4b09000000b006b9f26b9b94sm5655668otf.28.2023.08.15.15.48.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 15:48:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692139684; x=1692744484; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NdFYdE+8zG859zrBVZP+oPpVrC/pGqESV66SjeP3UlA=; b=SyXduwt0dfE0Onj648dV2pvwwc5V2Ei59JNOAGGHX1hCqfQIhGeN07cdpwJgAdzITO HZPJ5xfywEfBIw+iwtzjl7owXWgX0igiNBiSa+DJJaIbNfrM6MDrZpzXSztpVr9VI9Kv H5AUlKC7R2wXQSE4fpFyARLnqfiDgg9nH6Z2dgma9gphjTsCrrATgNqN0QtQ+3gsgek/ DSF6RlDJ7sjS+Jxi/XixEuLiqFWD/F646Qi9xQU2IwUeVd6J+P0ozcz5uLyyneKKpdFQ qjeEvSA4Zn49TXHMGyGgCtkeHNG2Kk1xTIW0tsZm96Uat+qxQ7BvTmHGscDq1PahfWI0 IHGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692139684; x=1692744484; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NdFYdE+8zG859zrBVZP+oPpVrC/pGqESV66SjeP3UlA=; b=as2Hvk+z3f+FieFBghj08yQT/dOK09pZOPQYpUV8fjH4Icn4ph+HKVPoyLX2z07/oy G0MJZg1ilaRQoW6NCRQjZ/4HLh07subPFwL3IJpVg6p/OMvGNAWbRLtT4SCmij+kd4nx jUbjlPi+Ae0k2w1MIx1CPFFZ+tLSm6w3MxiHCsvMPrb6hI1x8jwyjyOZ6rSzW4tvVedn M+aFrtpQ43IZZ67Whh+2rS3QwXvfsyz6Jq/FCNtRlsv9c0WhovoWgePleyy0EyMkZkmN Py2SzVWvlVcvSHXmGZQEXWSBqkN1oNBCdzxxP8MG38BDlJO+flpy3DolkqOzFrsN3+tc UOlg== X-Gm-Message-State: AOJu0YwJlQW+Oxobq2ciOmQ8ZBlkhhDryERMAJ44y3SbVq2RaAESxWDC z3H60ggk9z+3pQC63tbv2w8ZkHLURFbJI9PEBr4= X-Google-Smtp-Source: AGHT+IFqZOV9rYp/yFeNgvY0zfWN3bTerow1gL7k6v9NO8cC2KOc3yMmQ8JfBGzGIFXq3KHCHYsR4Q== X-Received: by 2002:a05:6830:13c6:b0:6b9:b665:7f with SMTP id e6-20020a05683013c600b006b9b665007fmr85375otq.17.1692139683746; Tue, 15 Aug 2023 15:48:03 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v3 5/8] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig Date: Tue, 15 Aug 2023 19:47:30 -0300 Message-ID: <20230815224733.434682-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815224733.434682-1-dbarboza@ventanamicro.com> References: <20230815224733.434682-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1692139770852100001 Content-Type: text/plain; charset="utf-8" If we want to make better decisions when auto-enabling extensions during realize() we need a way to tell if an user set an extension manually. The RISC-V KVM driver has its own solution via a KVMCPUConfig struct that has an 'user_set' flag that is set during the Property set() callback. The set() callback also does init() time validations based on the current KVM driver capabilities. For TCG we would want a 'user_set' mechanic too, but we would look ad-hoc via cpu_cfg_ext_auto_update() if a certain extension was user set or not. If we copy what was made in the KVM side we would look for 'user_set' for one into 60+ extension structs spreaded in 3 arrays (riscv_cpu_extensions, riscv_cpu_experimental_exts, riscv_cpu_vendor_exts). We'll still need an extension struct but we won't be using the 'user_set' flag: - 'RISCVCPUMultiExtConfig' will be our specialized structure, similar to wh= at we're already doing with the MISA extensions in 'RISCVCPUMisaExtConfig'. DEFINE_PROP_BOOL() for all 3 extensions arrays were replaced by MULTI_EXT_CFG_BOOL(), a macro that will init our specialized struct; - the 'multi_ext_user_opts' hash will be used to store the offset of each extension that the user set via the set() callback, cpu_set_multi_ext_cfg(). For now we're just initializing and populating it - next patch will use it to determine if a certain extension was user set; - cpu_add_multi_ext_prop() is a new helper that will replace the qdev_property_add_static() calls that our macros are doing to populate user properties. The macro was renamed to ADD_CPU_MULTIEXT_PROPS_ARRAY() for clarity. Note that the non-extension properties in riscv_cpu_options[] still need to be declared via qdev(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 240 ++++++++++++++++++++++++++++----------------- 1 file changed, 150 insertions(+), 90 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f8f0b8f2c9..f8be03a536 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -151,6 +151,9 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaC= ondOps), }; =20 +/* Hash that stores user set extensions */ +static GHashTable *multi_ext_user_opts; + static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) { bool *ext_enabled =3D (void *)&cpu->cfg + ext_offset; @@ -1661,6 +1664,8 @@ static void riscv_cpu_init(Object *obj) qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); #endif /* CONFIG_USER_ONLY */ + + multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); } =20 typedef struct RISCVCPUMisaExtConfig { @@ -1812,98 +1817,108 @@ static void riscv_cpu_add_misa_properties(Object *= cpu_obj) } } =20 -static Property riscv_cpu_extensions[] =3D { +typedef struct RISCVCPUMultiExtConfig { + const char *name; + uint32_t offset; + bool enabled; +} RISCVCPUMultiExtConfig; + +#define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \ + {.name =3D _name, .offset =3D CPU_CFG_OFFSET(_prop), \ + .enabled =3D _defval} + +static RISCVCPUMultiExtConfig riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ - DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), - DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), - DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), - DEFINE_PROP_BOOL("Zfa", RISCVCPU, cfg.ext_zfa, true), - DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), - DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), - DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), - DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), - DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), - DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), - - DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false), - DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), - DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), - DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), - DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), - - DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), - DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), - DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), - DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), - DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), - DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), - DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), - DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), - DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), - DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), - DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), - DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), - DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), - DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), - DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), - DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), - DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), - - DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), - DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), - DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), - DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), - - DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true), - DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), - - DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), - - DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false), - DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false), - DEFINE_PROP_BOOL("zcd", RISCVCPU, cfg.ext_zcd, false), - DEFINE_PROP_BOOL("zce", RISCVCPU, cfg.ext_zce, false), - DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false), - DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false), - DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false), + MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), + MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true), + MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true), + MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true), + MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true), + MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true), + MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false), + MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false), + MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false), + MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false), + MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false), + MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), + + MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), + MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true), + MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false), + MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false), + MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false), + + MULTI_EXT_CFG_BOOL("zba", ext_zba, true), + MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true), + MULTI_EXT_CFG_BOOL("zbc", ext_zbc, true), + MULTI_EXT_CFG_BOOL("zbkb", ext_zbkb, false), + MULTI_EXT_CFG_BOOL("zbkc", ext_zbkc, false), + MULTI_EXT_CFG_BOOL("zbkx", ext_zbkx, false), + MULTI_EXT_CFG_BOOL("zbs", ext_zbs, true), + MULTI_EXT_CFG_BOOL("zk", ext_zk, false), + MULTI_EXT_CFG_BOOL("zkn", ext_zkn, false), + MULTI_EXT_CFG_BOOL("zknd", ext_zknd, false), + MULTI_EXT_CFG_BOOL("zkne", ext_zkne, false), + MULTI_EXT_CFG_BOOL("zknh", ext_zknh, false), + MULTI_EXT_CFG_BOOL("zkr", ext_zkr, false), + MULTI_EXT_CFG_BOOL("zks", ext_zks, false), + MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false), + MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false), + MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false), + + MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false), + MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false), + MULTI_EXT_CFG_BOOL("zhinx", ext_zhinx, false), + MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false), + + MULTI_EXT_CFG_BOOL("zicbom", ext_icbom, true), + MULTI_EXT_CFG_BOOL("zicboz", ext_icboz, true), + + MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false), + + MULTI_EXT_CFG_BOOL("zca", ext_zca, false), + MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false), + MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false), + MULTI_EXT_CFG_BOOL("zce", ext_zce, false), + MULTI_EXT_CFG_BOOL("zcf", ext_zcf, false), + MULTI_EXT_CFG_BOOL("zcmp", ext_zcmp, false), + MULTI_EXT_CFG_BOOL("zcmt", ext_zcmt, false), =20 DEFINE_PROP_END_OF_LIST(), }; =20 -static Property riscv_cpu_vendor_exts[] =3D { - DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), - DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), - DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), - DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), - DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, fal= se), - DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, fal= se), - DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), - DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), - DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false= ), - DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, fal= se), - DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), - DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), +static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] =3D { + MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false), + MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false), + MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false), + MULTI_EXT_CFG_BOOL("xtheadcmo", ext_xtheadcmo, false), + MULTI_EXT_CFG_BOOL("xtheadcondmov", ext_xtheadcondmov, false), + MULTI_EXT_CFG_BOOL("xtheadfmemidx", ext_xtheadfmemidx, false), + MULTI_EXT_CFG_BOOL("xtheadfmv", ext_xtheadfmv, false), + MULTI_EXT_CFG_BOOL("xtheadmac", ext_xtheadmac, false), + MULTI_EXT_CFG_BOOL("xtheadmemidx", ext_xtheadmemidx, false), + MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false), + MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false), + MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false), =20 DEFINE_PROP_END_OF_LIST(), }; =20 /* These are experimental so mark with 'x-' */ -static Property riscv_cpu_experimental_exts[] =3D { - DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), +static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] =3D { + MULTI_EXT_CFG_BOOL("x-zicond", ext_zicond, false), =20 /* ePMP 0.9.3 */ - DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), - DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), - DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), + MULTI_EXT_CFG_BOOL("x-epmp", epmp, false), + MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false), + MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false), =20 - DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), - DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), + MULTI_EXT_CFG_BOOL("x-zvfh", ext_zvfh, false), + MULTI_EXT_CFG_BOOL("x-zvfhmin", ext_zvfhmin, false), =20 - DEFINE_PROP_BOOL("x-zfbfmin", RISCVCPU, cfg.ext_zfbfmin, false), - DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false), - DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false), + MULTI_EXT_CFG_BOOL("x-zfbfmin", ext_zfbfmin, false), + MULTI_EXT_CFG_BOOL("x-zvfbfmin", ext_zvfbfmin, false), + MULTI_EXT_CFG_BOOL("x-zvfbfwma", ext_zvfbfwma, false), =20 DEFINE_PROP_END_OF_LIST(), }; @@ -1926,6 +1941,49 @@ static Property riscv_cpu_options[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value); + + g_hash_table_insert(multi_ext_user_opts, + GUINT_TO_POINTER(multi_ext_cfg->offset), + (gpointer)value); +} + +static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; + bool value =3D isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offse= t); + + visit_type_bool(v, name, &value, errp); +} + +static void cpu_add_multi_ext_prop(Object *cpu_obj, + RISCVCPUMultiExtConfig *multi_cfg) +{ + object_property_add(cpu_obj, multi_cfg->name, "bool", + cpu_get_multi_ext_cfg, + cpu_set_multi_ext_cfg, + NULL, (void *)multi_cfg); + + /* + * Set def val directly instead of using + * object_property_set_bool() to save the set() + * callback hash for user inputs. + */ + isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, + multi_cfg->enabled); +} + #ifndef CONFIG_USER_ONLY static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, const char *name, @@ -1945,10 +2003,11 @@ static void cpu_set_cfg_unavailable(Object *obj, Vi= sitor *v, } #endif =20 -static void riscv_cpu_add_qdev_prop_array(DeviceState *dev, Property *arra= y) +static void riscv_cpu_add_multiext_prop_array(Object *obj, + RISCVCPUMultiExtConfig *arra= y) { - for (Property *prop =3D array; prop && prop->name; prop++) { - qdev_property_add_static(dev, prop); + for (RISCVCPUMultiExtConfig *prop =3D array; prop && prop->name; prop+= +) { + cpu_add_multi_ext_prop(obj, prop); } } =20 @@ -1971,9 +2030,9 @@ static void riscv_cpu_add_kvm_unavail_prop(Object *ob= j, const char *prop_name) } =20 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, - Property *array) + RISCVCPUMultiExtConfig *a= rray) { - for (Property *prop =3D array; prop && prop->name; prop++) { + for (RISCVCPUMultiExtConfig *prop =3D array; prop && prop->name; prop+= +) { riscv_cpu_add_kvm_unavail_prop(obj, prop->name); } } @@ -2008,8 +2067,6 @@ static void riscv_cpu_add_kvm_properties(Object *obj) */ static void riscv_cpu_add_user_properties(Object *obj) { - DeviceState *dev =3D DEVICE(obj); - #ifndef CONFIG_USER_ONLY riscv_add_satp_mode_properties(obj); =20 @@ -2021,10 +2078,13 @@ static void riscv_cpu_add_user_properties(Object *o= bj) =20 riscv_cpu_add_misa_properties(obj); =20 - riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_extensions); - riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_options); - riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_vendor_exts); - riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_experimental_exts); + riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); + riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); + riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); + + for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { + qdev_property_add_static(DEVICE(obj), prop); + } } =20 /* @@ -2035,7 +2095,7 @@ static void riscv_init_max_cpu_extensions(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - Property *prop; + RISCVCPUMultiExtConfig *prop; =20 /* Enable RVG, RVJ and RVV that are disabled by default */ set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); --=20 2.41.0 From nobody Sat May 18 04:30:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1692139753; cv=none; d=zohomail.com; s=zohoarc; b=JbUb0+p9k8AW76wCgaV17rL4L6Aav4qgVSuNk5h+oorZx5qsSOCAvtoGGji5rKS2c2frDouBn6ArWRaUO0TngijreN9QMAoK+Hu72f1TCMliYfaUudmDZV9OO6rxwqNOXWHGDcpscdcdWr1FHs6j9CSejlieL1QtfJ4DdvMrpEU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1692139753; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=61rviudoS0tPwh5erQkA5DyOXPmz9WRzdOuGC0M2QpM=; b=hye5cYS8raF220nmrlvAxL4fDQ1RyZhtC5z8PQa530bHUyk8SqwjXYaszT1sSXlt3v94TZMVzxN0wfcuBcW7NYXwKNrWVEqpzb9VxzWISsyPJGiTQbYDQDFBc4pwVl4HyHABjBpP2slebMz9RO+55Fi3Dw3HwEI4iAPmONoGl2k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1692139753303652.3300284568228; Tue, 15 Aug 2023 15:49:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qW2pg-0006ol-5o; Tue, 15 Aug 2023 18:48:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qW2pe-0006oI-6w for qemu-devel@nongnu.org; Tue, 15 Aug 2023 18:48:10 -0400 Received: from mail-ot1-x32c.google.com ([2607:f8b0:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qW2pb-0008Hw-UV for qemu-devel@nongnu.org; Tue, 15 Aug 2023 18:48:09 -0400 Received: by mail-ot1-x32c.google.com with SMTP id 46e09a7af769-6bd06470b68so4059397a34.1 for ; Tue, 15 Aug 2023 15:48:07 -0700 (PDT) Received: from grind.. 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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id q9-20020a9d4b09000000b006b9f26b9b94sm5655668otf.28.2023.08.15.15.48.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 15:48:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692139686; x=1692744486; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=61rviudoS0tPwh5erQkA5DyOXPmz9WRzdOuGC0M2QpM=; b=QR/QIphGjmBNBtDc7jBpoC9rP1KIPJarq92uYFRfsSHx+MJaFL4ssGxeHbJNCRCE4g OaBZl2P2XwJkjeFGjxMq7YRx18bEvulP0puvoOpavjJQ6nJENIpR5cS4N2l+4cQY8Lh1 jsho5kNTh1jtgisiHm7Md1GlT3N17tiLFSIchyKT0dRC6QGEyKK1jp6gIAY26gBJW/ju 7su2z57ktK0eP+wyjODpKsynMUsHVwgd2n0u70YlTcZRUlN1h7Tt/74jKWSq8Uf06vtd 802cLk0EHfdUKjnpto1N3LH9eO3VcCzOq8OzUwZX6qJkzaJ4ABOXM0UV9CpBgx2eYaot YVjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692139686; x=1692744486; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=61rviudoS0tPwh5erQkA5DyOXPmz9WRzdOuGC0M2QpM=; b=ImqaoD9gNzU3jk5hBwxDFJninVL8pWlbE/2cWlRwkhFPybn+/ql5/Shg2g9xizrmPV esBdHa/TNg0lWFAaa1xAQTXshHy10Ad1qZsfk1/eImakh2kNu4QOwNMjdaBS/ebEHQzC L+OK3hO5LkdRYd1Z0gmvJ00pWSih7SJ+mkYKlWQBJ9geDM1bOb4lQ4WHT0i+MIC+mKH5 FtwDkWvf4k3g+Uu++h6vb7GfHZmiZ12gTmGBF2sz9ERbhOyBpuEzBVj7Xqh7AJlgseAG Z3z7ARjBmtv3uEhVivQYgS4jHYPndX/96HO/gHV6JyxRz6LykiAMzj53wW7R7jd8X7y1 ZkTA== X-Gm-Message-State: AOJu0Yy4P7xpRpySnQmX7M8NYd1lJ2mlg+PONM7V4VWitXBFtWgT0nTc T9q/ieBwi0C6mpIm+qyX2mTiXOFnYdUl60KIbK4= X-Google-Smtp-Source: AGHT+IEGa4iHbzPBRfHGOBEDgS7iBvwqGV27Qar95TfQXv1DSP0U7oS0lNP77mSEsuqxFc2L01gQHA== X-Received: by 2002:a9d:5a96:0:b0:6b8:b83c:a1f8 with SMTP id w22-20020a9d5a96000000b006b8b83ca1f8mr2075626oth.19.1692139686616; Tue, 15 Aug 2023 15:48:06 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v3 6/8] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions() Date: Tue, 15 Aug 2023 19:47:31 -0300 Message-ID: <20230815224733.434682-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815224733.434682-1-dbarboza@ventanamicro.com> References: <20230815224733.434682-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1692139754643100003 Content-Type: text/plain; charset="utf-8" Before adding support to detect if an extension was user set we need to handle how we're enabling extensions in riscv_init_max_cpu_extensions(). object_property_set_bool() calls the set() callback for the property, and we're going to use this callback to set the 'multi_ext_user_opts' hash. This means that, as is today, all extensions we're setting for the 'max' CPU will be seen as user set in the future. Let's change set_bool() to isa_ext_update_enabled() that will just enable/disable the flag on a certain offset. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f8be03a536..e24085fd64 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2101,24 +2101,24 @@ static void riscv_init_max_cpu_extensions(Object *o= bj) set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); =20 for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { - object_property_set_bool(obj, prop->name, true, NULL); + isa_ext_update_enabled(cpu, prop->offset, true); } =20 /* set vector version */ env->vext_ver =3D VEXT_VERSION_1_00_0; =20 /* Zfinx is not compatible with F. Disable it */ - object_property_set_bool(obj, "zfinx", false, NULL); - object_property_set_bool(obj, "zdinx", false, NULL); - object_property_set_bool(obj, "zhinx", false, NULL); - object_property_set_bool(obj, "zhinxmin", false, NULL); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); =20 - object_property_set_bool(obj, "zce", false, NULL); - object_property_set_bool(obj, "zcmp", false, NULL); - object_property_set_bool(obj, "zcmt", false, NULL); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); =20 if (env->misa_mxl !=3D MXL_RV32) { - object_property_set_bool(obj, "zcf", false, NULL); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); } } =20 --=20 2.41.0 From nobody Sat May 18 04:30:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1692139729; cv=none; d=zohomail.com; s=zohoarc; b=ggJLAun3avFwqZUxze7M0xqjffaqrHc/yG5XGTiwOTp13dAwvjc0cNkPY/uTDsBqdH5h6Ak+6vLZw6OunTFhGGeEg9hK/rexikzX6YUpmkOHPoJCdeMuFRtLJcdr3s9RY29uXOZ+ZxdDPTuQ9bi2qO0jw2DQuefaep28hKvpHPw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1692139729; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nHZruyGhS61hd7x1Y8uBGx8vYdEXaf7f0K0Y/6jZHbo=; b=iinEZNK4eQZWg7GAbvBBCo+skorEVvRtrTtqkbiwnoRM+/UXa1+/pbkI8zIxI/4NrGg0nBxx/Y5yjez4JvPgli828S0WnWqarSvRs0mxYX/GU0ImwaGXHuThDOhapUYtlveXCaFU+w5Q5xxA9r5YMIr2hTu1CQz6BFkeh9kXwTY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169213972908139.87457107082662; Tue, 15 Aug 2023 15:48:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qW2pj-0006qU-0b; Tue, 15 Aug 2023 18:48:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qW2ph-0006pr-Le for qemu-devel@nongnu.org; Tue, 15 Aug 2023 18:48:13 -0400 Received: from mail-oa1-x31.google.com ([2001:4860:4864:20::31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qW2pf-0008Ic-Eq for qemu-devel@nongnu.org; Tue, 15 Aug 2023 18:48:13 -0400 Received: by mail-oa1-x31.google.com with SMTP id 586e51a60fabf-1bbdddd3c94so4621476fac.0 for ; Tue, 15 Aug 2023 15:48:11 -0700 (PDT) Received: from grind.. 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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id q9-20020a9d4b09000000b006b9f26b9b94sm5655668otf.28.2023.08.15.15.48.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 15:48:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692139689; x=1692744489; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nHZruyGhS61hd7x1Y8uBGx8vYdEXaf7f0K0Y/6jZHbo=; b=f56eKBTC4sNCCjFlYrE+mSxa8BlcbGvrOnlGPkfhhf+uV3vGTTMH1nlmaBRmvhvcE5 0bfzsTrTEUxdI1UJY+R77UEp6in0g6YFp1FzLXIlbWuP39ALP0ynoDyV8CyfFkGI3AG8 ykU2T5zastD87wRn/VNNcHIRz6jZDa1vUHCWEVU9UrlabAOApzO+YB1GzVYqgANIp5Nq 83Q6N2dQCToQFgQurKSqQhLKZCHd6B6k1bNDtV48h9KIIIuXF5T4K5JjA7B+Z+Y+X9fq /O9fKl5f2+ici+0u1jh0Yd0vlnPHepF2JVBn7SYNm6sNFkMHM4ZMl5NjxFk1f6wAbJYt 337A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692139689; x=1692744489; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nHZruyGhS61hd7x1Y8uBGx8vYdEXaf7f0K0Y/6jZHbo=; b=j9/arL6/GlNwGVyMYxT8cCecbJSeMftZjoF4TzN/Icg01Ryvnf+jNzKuIOmq35VY/5 J3qfEYN9uvVxbDCO4SXqSFyrLYVnLtUi/YTl2k2Xgii2xPkoRo7wZlcN39pxYyGwXZxp zAW2imYyTIk5mskdQ3xtv7qZLxKDsi2MMv5MRbhCgs5bT5/YO8IrVcQl+qlBPi6B+lgP pR5pHVCMzQDSccBO3Mi6FQAurAiPnBB7GqOyn5IBS8HhspTMUxL8I86hfoWaeNsOHsei NIYHmYqUxPn0shrjx3I5gC4oQ+LBZXoOskhcMOHlo5BlyFgOHlgcplYf3dIIIm4QzEO4 QBrg== X-Gm-Message-State: AOJu0YyU9FzlJbNs187h9WvJKiT/MmMJQdQvItkdROzAohH1EomS9SsN tO/HJqcr1oL8vNmDNOsB0jVPxyfF4gE4OHsCXHk= X-Google-Smtp-Source: AGHT+IF9QtcXGTHFaIGCXV0nkQh7+UaiQEvI8rWtgxClBYsHoEPqNxlpMTLwTicd5iKGBPEUGtW1mA== X-Received: by 2002:a05:6870:f60c:b0:1bf:a95:7a3f with SMTP id ek12-20020a056870f60c00b001bf0a957a3fmr33911oab.54.1692139689630; Tue, 15 Aug 2023 15:48:09 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v3 7/8] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update() Date: Tue, 15 Aug 2023 19:47:32 -0300 Message-ID: <20230815224733.434682-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815224733.434682-1-dbarboza@ventanamicro.com> References: <20230815224733.434682-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1692139730764100003 Content-Type: text/plain; charset="utf-8" Add a new cpu_cfg_ext_is_user_set() helper to check if an extension was set by the user in the command line. Use it inside cpu_cfg_ext_auto_update() to verify if the user set a certain extension and, if that's the case, do not change its value. This will make us honor user choice instead of overwriting the values. Users will then be informed whether they're using an incompatible set of extensions instead of QEMU setting a magic value that works. For example, we'll now error out if the user explictly set 'zce' to true and 'zca' to false: $ ./build/qemu-system-riscv64 -M virt -cpu rv64,zce=3Dtrue,zca=3Dfalse -nog= raphic qemu-system-riscv64: Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca extension This didn't happen before because we were enabling 'zca' if 'zce' was enabl= ed regardless if the user explictly set 'zca' to false. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e24085fd64..2bab425f9f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -185,6 +185,12 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_of= fset) return PRIV_VERSION_1_10_0; } =20 +static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) +{ + return g_hash_table_contains(multi_ext_user_opts, + GUINT_TO_POINTER(ext_offset)); +} + static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, bool value) { @@ -196,6 +202,10 @@ static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uin= t32_t ext_offset, return; } =20 + if (cpu_cfg_ext_is_user_set(ext_offset)) { + return; + } + if (value && env->priv_ver !=3D PRIV_VERSION_LATEST) { /* Do not enable it if priv_ver is older than min_version */ min_version =3D cpu_cfg_ext_get_min_version(ext_offset); --=20 2.41.0 From nobody Sat May 18 04:30:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1692139753; cv=none; d=zohomail.com; s=zohoarc; b=K1F2uEP9fUKML5Q7xSJHr5HdpQJ3IQS6AQCfhSYx6uXDfpTZoo9vdGcqHeK8KjWmOdHKNzpHzG3Va85DvXmL6rpRBmYHyEcc74mUKqinLzRhZJzM0fx30m1PWSUxG32qC0wkuP3416sFOxyApJ7HVcPK1nMCMSKwQYulIrGRVQw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1692139753; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GOMe29cQF2wDUzsUpAhXMdDgBLedr0DT4vrKcm/eM6Q=; b=hRg7EflCMUiKKCh5I8+BWC6mwqKk7ApcJvJ8lxMbyyLAkjoIfW4hJeQWlKpG9WPZdXsyNMBynbWiJfIuxxV5fDgoPjbx8KqCEFyfrLDHFDWiYZ9kgX2Mmc6X+pFdGa6uG7RJmMShMke9eH3pnFfn03/spN0bUBD18xIN25GDQmo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1692139753621314.4000819034727; Tue, 15 Aug 2023 15:49:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qW2pn-0006rS-IE; Tue, 15 Aug 2023 18:48:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qW2pl-0006qy-9a for qemu-devel@nongnu.org; Tue, 15 Aug 2023 18:48:17 -0400 Received: from mail-ot1-x32d.google.com ([2607:f8b0:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qW2ph-0008J5-UZ for qemu-devel@nongnu.org; Tue, 15 Aug 2023 18:48:17 -0400 Received: by mail-ot1-x32d.google.com with SMTP id 46e09a7af769-6bcac140aaaso4856236a34.2 for ; Tue, 15 Aug 2023 15:48:13 -0700 (PDT) Received: from grind.. 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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id q9-20020a9d4b09000000b006b9f26b9b94sm5655668otf.28.2023.08.15.15.48.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 15:48:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692139692; x=1692744492; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GOMe29cQF2wDUzsUpAhXMdDgBLedr0DT4vrKcm/eM6Q=; b=VmD1A2FBOYULK5oakH/1MaL4+DaWEdcfIdkxJFzt2Wot0ug+VgC9qBI1ZrS6PNfCmA dRyXPET00QTAazgA2b2nvQefQJL7ERuEQN5teIHCPX4+kkfLxEYrntyd/eEjNiNUjcGH MTtTcjHnUaehCbYeEG3BFTURWI40ByulaJ0SZuNlxfc4YKzFFTH5cXOzYhZGMsoFD+8h SZenH0jS8oj61qwH6d8Epwb98H8DzzI23HhOUOn1xNj5W4kx/OaEJkUbarrqQI8MeSnB s5NuFBPXBnXWN7MqiesmWCLpYwMKVH81dHSiSyFbJdKVNvCcC9QlPjdz7sUta9ig2Tkq Zn0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692139692; x=1692744492; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GOMe29cQF2wDUzsUpAhXMdDgBLedr0DT4vrKcm/eM6Q=; b=W6SDquZjUQguRGR0O/O72GpE6OJ9ZgX5ydb+RvQLzosus1Cc9Q+nsPrEOK5KEM3dbS PUQa3xFwjRSq/jARRVYvH86oGOUDQvUHFPZkrsFvDSI7fwTDyqQUGZI+ZNmuQLxJOyDz Ama/s7SK/nxOTDoxm1JWb9FpPYbiMYaewZLiQoMOa8uYnepEnj75scvBxLVe89hc7WYc JjY4CMwMr1m6SJXaubqDnv1rfejDm3JqQef0vXdhQcszhrhmdCPtcpDSAYBlaPHkP6Ef M3453CUaoyN+Tnn0W1SSW3uVIVx6d2OErZZ6petXLjkcLgonLIu5cEz1fFjj6jYR7ena z/DQ== X-Gm-Message-State: AOJu0YyDnrpuI9p8qyAdp4FoHRFr1BTjPSahBlvlesx5G5XNPg32r3+T 9UcDSZTT2o+0oNHrOtqYQEccR1QphVqZQg7isHE= X-Google-Smtp-Source: AGHT+IHUCwktIOVBiB+z/PFYAGj6d29Ks4krgtxJLUJf7WLwTCciiXSaf79sltsLQqrht7XHw+v96Q== X-Received: by 2002:a9d:7985:0:b0:6b8:6785:ed0b with SMTP id h5-20020a9d7985000000b006b86785ed0bmr65372otm.30.1692139692731; Tue, 15 Aug 2023 15:48:12 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v3 8/8] target/riscv/cpu.c: consider user option with RVG Date: Tue, 15 Aug 2023 19:47:33 -0300 Message-ID: <20230815224733.434682-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815224733.434682-1-dbarboza@ventanamicro.com> References: <20230815224733.434682-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32d; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1692139755421100007 Content-Type: text/plain; charset="utf-8" Enabling RVG will enable a set of extensions that we're not checking if the user was okay enabling or not. And in this case we want to error out, instead of ignoring, otherwise we will be inconsistent enabling RVG without all its extensions. After this patch, disabling ifencei or icsr while enabling RVG will result in error: $ ./build/qemu-system-riscv64 -M virt -cpu rv64,g=3Dtrue,Zifencei=3Dfalse -= -nographic qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei qemu-system-riscv64: RVG requires Zifencei but user set Zifencei to false Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2bab425f9f..d608026a28 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1133,8 +1133,22 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu= , Error **errp) riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_icsr =3D true; - cpu->cfg.ext_ifencei =3D true; + + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) && + !cpu->cfg.ext_icsr) { + error_setg(errp, "RVG requires Zicsr but user set Zicsr to fal= se"); + return; + } + + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) && + !cpu->cfg.ext_ifencei) { + error_setg(errp, "RVG requires Zifencei but user set " + "Zifencei to false"); + return; + } + + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true); =20 env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; env->misa_ext_mask |=3D RVI | RVM | RVA | RVF | RVD; --=20 2.41.0