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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id be15-20020a056808218f00b003a40b3fce01sm5903418oib.10.2023.08.15.15.38.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 15:38:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692139086; x=1692743886; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+V2uJDGM7UK+i6uFrn6LQi2aVYMe08c1CeeSTBFBbVk=; b=TGxtVyZnj3KbmA/V3RlQfebFZbFd7OVQ4SGZsWK9zQ/UMMFBBYRcf1Dudpu8blwb+a LAfQN5eTBH9b9Ab/VXQOap0QpYUAvd9EJ4hYqszufNxDIjDsgu0enMTXM3uDOu3IvV1G V10tHiGZpzhVkPvWsEbmNjaMSQxnduCpYlPpELHiQpjYCDAULgUD+fbfo9UPAC3gwGYt SZjy36xn9gsiYUlfdQBb6WFe8AtvboASGYkGPW2pOrtXCeX4jcFqJclRWdN6eMuD07aZ aLMKigCuCUPJenqzbe9BswtSbTUapChpgWZbK14a997BKkUF3TDbvL5gj34vxcinboKY tKUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692139086; x=1692743886; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+V2uJDGM7UK+i6uFrn6LQi2aVYMe08c1CeeSTBFBbVk=; b=XDQmJsSAwmlsSiF28F/XkDJrFlY1c42nmwIP9s55sEAue9w+ZatQD5n96MXwmZJGnF R0/KUwRSbdkqeL/PQ8BHEi/HuddryWG+X9kNv3TDBYFa7GlXyATxnwKVB1OD4r45DvN3 OhMhliHNPTerSnKxtZytTlGKjIC6Wyl3MpBT38N/3LuTLSOQ7N54ixaQviEOhsVLJXDS r3YPT4MpZIvgMRe5Pmh7xY+REiiCYtVXhdUjKk11UUcYx9w/Y+FyOoSVEzPGdFKY+fl6 /sU5t1SjBpl0VcjaXsYsjnPwTOcnQ1sDrCjXC3c7/2XBMkFU+Oa69+8BwzGEn3XdzOSG 0IuA== X-Gm-Message-State: AOJu0Yzjm9vuyc5Ej0IMcnGIYIiovGwTjg/7KAsKra4bhjsCgpvQJMWd ci+A9s6DLLl8uDw8sU5LhMBNXGCQ/JbykfoIogQ= X-Google-Smtp-Source: AGHT+IFxVsBy0eWzcPZL+lSToCDaogS9qAMSInEQNEdexRpmMeSXHMAdI8QaPUEdti2h74C76FBEAg== X-Received: by 2002:a05:6808:159:b0:3a7:a379:63a with SMTP id h25-20020a056808015900b003a7a379063amr44791oie.41.1692139086806; Tue, 15 Aug 2023 15:38:06 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v8 06/12] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[] Date: Tue, 15 Aug 2023 19:37:35 -0300 Message-ID: <20230815223741.433763-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815223741.433763-1-dbarboza@ventanamicro.com> References: <20230815223741.433763-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1692139203224100001 Content-Type: text/plain; charset="utf-8" Create a new riscv_cpu_experimental_exts[] to store the non-ratified extensions properties. Once they are ratified we'll move them back to riscv_cpu_extensions[]. riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() are changed to keep adding non-ratified properties to users. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 42 +++++++++++++++++++++++++++--------------- 1 file changed, 27 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3cd025b678..520c5c9f96 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1807,21 +1807,6 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false), DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false), =20 - /* These are experimental so mark with 'x-' */ - DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), - - /* ePMP 0.9.3 */ - DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), - DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), - DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), - - DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), - DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), - - DEFINE_PROP_BOOL("x-zfbfmin", RISCVCPU, cfg.ext_zfbfmin, false), - DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false), - DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false), - DEFINE_PROP_END_OF_LIST(), }; =20 @@ -1842,6 +1827,25 @@ static Property riscv_cpu_vendor_exts[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +/* These are experimental so mark with 'x-' */ +static Property riscv_cpu_experimental_exts[] =3D { + DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), + + /* ePMP 0.9.3 */ + DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), + DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), + DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), + + DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), + DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), + + DEFINE_PROP_BOOL("x-zfbfmin", RISCVCPU, cfg.ext_zfbfmin, false), + DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false), + DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false), + + DEFINE_PROP_END_OF_LIST(), +}; + static Property riscv_cpu_options[] =3D { DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), =20 @@ -1913,6 +1917,10 @@ static void riscv_cpu_add_kvm_properties(Object *obj) riscv_cpu_add_kvm_unavail_prop(obj, prop->name); } =20 + for (prop =3D riscv_cpu_experimental_exts; prop && prop->name; prop++)= { + riscv_cpu_add_kvm_unavail_prop(obj, prop->name); + } + for (prop =3D riscv_cpu_options; prop && prop->name; prop++) { /* Check if KVM created the property already */ if (object_property_find(obj, prop->name)) { @@ -1956,6 +1964,10 @@ static void riscv_cpu_add_user_properties(Object *ob= j) for (prop =3D riscv_cpu_vendor_exts; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } + + for (prop =3D riscv_cpu_experimental_exts; prop && prop->name; prop++)= { + qdev_property_add_static(dev, prop); + } } =20 static Property riscv_cpu_properties[] =3D { --=20 2.41.0