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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id be15-20020a056808218f00b003a40b3fce01sm5903418oib.10.2023.08.15.15.37.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 15:37:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692139072; x=1692743872; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LCch6fM7rUgQScUqXb+DtD/viZ/OLl4eViDfh6qTFO8=; b=oXaHOCx8Lox9WSOUp0THx9W6I044tQwjJG4kPGB9ZKL0elGFJpGhwWPWEX4sPVBoXy 3CKlHPajJ9FyzDfhcVKG/1EMi+N7uj8xJq70/Kls9d87ocJECuVJnj+9oH8vcr2Y2n7q hPgqcyaV3M8WyCnc/Bqt8apRBSviCyNdxSWLMGmLNcjEpdxqF8EidxCieDrrdBIa3mkS beSq6G/FtTRL14XJHzMe6CznYuRPbOaqshQulPqnTpbu25cb8s3X7gdmkxBp+2j2dZqu JvtmGa6wvWRH6PEMt9UUPJewGqWT9TIllNNreCyb2jSqjnqkOfKdteKFXQN5M88o2JAS 0ZWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692139072; x=1692743872; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LCch6fM7rUgQScUqXb+DtD/viZ/OLl4eViDfh6qTFO8=; b=StMTm0xRjMg515nHm3bTCdtjEUbzkTHrEd85hFr4e+T4BFJp/iQ+RPvxS9+qBzc/cz lR/EE+4o3jCJ2dgWK7SWnEdpN+glkzudZyMhv8bbRFnD7Z5G9SxV8bXNVLW944jBOzGZ hQ6643c/fRukVso+zyTPZnJFI551p4SS5GRj1Uxgl2KQhAUy46jw82GUchoBZwjNjOGr kuYGjuvPUPytNq+IfAtjCEd2fttdwKmh+W1dB2WOTbx3ke5yTSrD6T3CL7FabQ8QnTuZ SI1bkMgD7tGttaAh6MqYIXl2dWVHojnsXq+ao1xVby3S1ENNYBG9+dW8+5RtUsazNahr 8rZQ== X-Gm-Message-State: AOJu0YwJf6yElOaaMAE61ox3h/Bg1XGwsIMD0laMH2maJxDHsjh2bgiR YFUJPNNwOIiHwLB13xbw6w1um3FtjLfIdjSLBrE= X-Google-Smtp-Source: AGHT+IHa5BDubx02rYyu7jjbiYiugA6yvulQMJKXiSO+SZSjevZqTd8nAZuUggC0gTkJFXiIejxE5w== X-Received: by 2002:a05:6808:d48:b0:3a7:b3e7:54d1 with SMTP id w8-20020a0568080d4800b003a7b3e754d1mr34190oik.45.1692139071948; Tue, 15 Aug 2023 15:37:51 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v8 01/12] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] Date: Tue, 15 Aug 2023 19:37:30 -0300 Message-ID: <20230815223741.433763-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815223741.433763-1-dbarboza@ventanamicro.com> References: <20230815223741.433763-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1692139100432100005 Content-Type: text/plain; charset="utf-8" We'll add a new CPU type that will enable a considerable amount of extensions. To make it easier for us we'll do a few cleanups in our existing riscv_cpu_extensions[] array. Start by splitting all CPU non-boolean options from it. Create a new riscv_cpu_options[] array for them. Add all these properties in riscv_cpu_add_user_properties() as it is already being done today. 'mmu' and 'pmp' aren't really extensions in the usual way we think about RISC-V extensions. These are closer to CPU features/options, so move both to riscv_cpu_options[] too. In the near future we'll need to match all extensions with all entries in isa_edata_arr[], and so it happens that both 'mmu' and 'pmp' do not have a riscv,isa string (thus, no priv spec version restriction). This further emphasizes the point that these are more a CPU option than an extension. No functional changes made. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6b93b04453..9a3afc0482 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1752,7 +1752,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) =20 static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ - DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), @@ -1764,15 +1763,8 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), - DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), - DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), =20 - DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), - DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), - DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), - DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), - DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false), DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), @@ -1803,9 +1795,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), =20 DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true), - DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), - DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), =20 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), =20 @@ -1849,6 +1839,21 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static Property riscv_cpu_options[] =3D { + DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), + + DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), + DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + + DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), + DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), + + DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), + DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), + + DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), + DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), +}; =20 #ifndef CONFIG_USER_ONLY static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, @@ -1917,6 +1922,14 @@ static void riscv_cpu_add_user_properties(Object *ob= j) #endif qdev_property_add_static(dev, prop); } + + for (int i =3D 0; i < ARRAY_SIZE(riscv_cpu_options); i++) { + /* Check if KVM created the property already */ + if (object_property_find(obj, riscv_cpu_options[i].name)) { + continue; + } + qdev_property_add_static(dev, &riscv_cpu_options[i]); + } } =20 static Property riscv_cpu_properties[] =3D { --=20 2.41.0