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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id v15-20020a0568301bcf00b006b94fb2762asm5526849ota.23.2023.08.15.13.36.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 13:36:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692131812; x=1692736612; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jijFAfkGRrINbSKt8x1n4s5CLaAerjnprfe6w9w/rwE=; b=e9iSMBTinV8F+G5ij2DqiObb3dT8q5ypcbqo8sMmrnqVLZFbL4lUs7zO6ZOtCNFrCA rXPqskaFz70N59qEsN9iu8gw+/ktFHmCxD4MR2PPNIqiPJvSamUsn/eF2ll6drOJBx3A THEiwM0sKIYdoYravrye3xDVxxoGT1xQFIBXjxcTcopTqmbeQ+Ve+d3VGCUywibdagPX xV70gLQ1pz0JBqRjU7ZAZvzWvv49fFA6o+YLESMwi5yxj4AAG+b4X3ZGKjQ3YYJMJ/Pw BSeVWg23GVtWYB28Wq1qvnKFlLEToOERnpxgGf7fUVZavW6CZL94tttSvFD7p30hY7hG 72TA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692131812; x=1692736612; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jijFAfkGRrINbSKt8x1n4s5CLaAerjnprfe6w9w/rwE=; b=I1PLDZbKfzd/d0T1K0nmiMnlN1XE9diFNi12SVfM0SwF2FqjwmxLiiMbTMCGTtFpdo m9vtEtBhC0qKXbzK7dknrfmP7v6x09j5ey7V9UHvj8tAaBriUjn9P6bbWfDYeSxr37V8 +5icA9AliIqSUzuO8UKbYv+U2b11SgX8O1gSk4AFVsMQtQKvhzzeN9mi0mHgL96jYoH1 ctOzECxuFZDhXzKY/0WlGLlVYWejpUpkMIc+AbWIJwsh+fp5IEq9Db9KGsVjRq0YfEgx dtSIetR2iCEB0YguENK4CwrMaXbcaPEbpmZ2SFzz8g1E82KBsOh8xNa5H+pu7Y4+4LDD IIKQ== X-Gm-Message-State: AOJu0Yy+kQOVsiDkjEjET4vCLtCbyu52iIxETZQCTm2dPmvOyZpM2hId wAk4nfN1Iy3A5lWkoHH7Zy98KhWVDFIy7sG/RpI= X-Google-Smtp-Source: AGHT+IE3JYeQsy/8TzVzgDwIeTfEH+km+RWwOKhzpoPVsYJJxu82tqoahJ1EVIbOXRwU/UYROOpq2A== X-Received: by 2002:a9d:7746:0:b0:6b9:9e4f:5f4c with SMTP id t6-20020a9d7746000000b006b99e4f5f4cmr13289727otl.29.1692131812190; Tue, 15 Aug 2023 13:36:52 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v2 4/8] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize() Date: Tue, 15 Aug 2023 17:36:31 -0300 Message-ID: <20230815203635.400179-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230815203635.400179-1-dbarboza@ventanamicro.com> References: <20230815203635.400179-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1692131941926100001 Content-Type: text/plain; charset="utf-8" Let's change the other instances in realize() where we're enabling an extension based on a certain criteria (e.g. it's a dependency of another extension). We're leaving icsr and ifencei being enabled during RVG for later - we'll want to error out in that case. Every other extension enablement during realize is now done via cpu_cfg_ext_auto_update(). The end goal is that only cpu init() functions will handle extension flags directly via "cpu->cfg.ext_N =3D true|false". Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 50 +++++++++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 371317e7cc..5b4cc52c15 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1172,7 +1172,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) } =20 if (cpu->cfg.ext_zfh) { - cpu->cfg.ext_zfhmin =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true); } =20 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { @@ -1198,17 +1198,17 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cp= u, Error **errp) } =20 /* The V vector extension depends on the Zve64d extension */ - cpu->cfg.ext_zve64d =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true); } =20 /* The Zve64d extension depends on the Zve64f extension */ if (cpu->cfg.ext_zve64d) { - cpu->cfg.ext_zve64f =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true); } =20 /* The Zve64f extension depends on the Zve32f extension */ if (cpu->cfg.ext_zve64f) { - cpu->cfg.ext_zve32f =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true); } =20 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { @@ -1222,7 +1222,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) } =20 if (cpu->cfg.ext_zvfh) { - cpu->cfg.ext_zvfhmin =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true); } =20 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { @@ -1252,7 +1252,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) =20 /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_zhinx) { - cpu->cfg.ext_zhinxmin =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); } =20 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfi= nx) { @@ -1273,12 +1273,12 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cp= u, Error **errp) } =20 if (cpu->cfg.ext_zce) { - cpu->cfg.ext_zca =3D true; - cpu->cfg.ext_zcb =3D true; - cpu->cfg.ext_zcmp =3D true; - cpu->cfg.ext_zcmt =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { - cpu->cfg.ext_zcf =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } } =20 @@ -1327,26 +1327,26 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cp= u, Error **errp) } =20 if (cpu->cfg.ext_zk) { - cpu->cfg.ext_zkn =3D true; - cpu->cfg.ext_zkr =3D true; - cpu->cfg.ext_zkt =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true); } =20 if (cpu->cfg.ext_zkn) { - cpu->cfg.ext_zbkb =3D true; - cpu->cfg.ext_zbkc =3D true; - cpu->cfg.ext_zbkx =3D true; - cpu->cfg.ext_zkne =3D true; - cpu->cfg.ext_zknd =3D true; - cpu->cfg.ext_zknh =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true); } =20 if (cpu->cfg.ext_zks) { - cpu->cfg.ext_zbkb =3D true; - cpu->cfg.ext_zbkc =3D true; - cpu->cfg.ext_zbkx =3D true; - cpu->cfg.ext_zksed =3D true; - cpu->cfg.ext_zksh =3D true; + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true); } =20 /* --=20 2.41.0