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([2602:47:d483:7301:6bf0:9674:6ac4:f74c]) by smtp.gmail.com with ESMTPSA id z7-20020aa791c7000000b0066ebaeb149dsm287283pfa.88.2023.08.09.19.35.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Aug 2023 19:35:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1691634951; x=1692239751; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=phrIw6b5pWNBBmVHR2P9mXRKZKLN/f9yT3V1nvx09pc=; b=hetcGLSTvMBODJofQGfMVBISegsvqZdiKKEbSfvqqqx+d99tfCCDuaJWnrsG3hV+gX HeX00d8gGHe9ieeT8E3SnzLZiy0K+JL/Vf3EN5EDq1i9CFp1PrEhJ4mVePQ9vO1g7tbZ herQk+zbXxrFUzSytvWYr3gFniGDMuDmXW9GFngAh3r5ExlIX7IiyEzofpDk4+ypzfkG KX43SBIB+cpGu/HC3yzMxaRaVi3mlnug36VLLig+Q2A0/ZwpQ4O0Q3l5uU5e7AY6RIBV PimncngeezMtCofNYYrpyqc49LtO1xjVFWkcLo7R5y/t1KpFpCsRx8Pmrkj6MbxU2VzH H8Rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691634951; x=1692239751; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=phrIw6b5pWNBBmVHR2P9mXRKZKLN/f9yT3V1nvx09pc=; b=AX2PWhf1ZTgUn9kSAckmH1NH+NXZnNCvlHfSG1XupyLA+n8YSU3xWhi7wcd1/93wAN 5IP9RHb8K0K9q90ZPn5rFQs+7dzyBw11QbKQvu212g+jOD3tuVGWbwbgLSb/Lwosbpk8 4DCM1aezieTV0fYFoYztANWibmoCnsiSD5E8yJNJ1SXCTJHZIaOqwk5vsgJgfFTAKxrV P2oCbtGeeYLtlFTVRmUASGvffTMIcwW3COFtfoh54MrbImw4pEhp6WUf+LXsohTcteM1 yVPNGJR84uXi8FoIp/FkJp0kCWhHxgmkUmxDha3EMaGkO9P/3qmJryzPAoP6FKFo9GSX eeCw== X-Gm-Message-State: AOJu0YymsuusrddBxeddiEUJ0uAztZcyPAwt1Tf+kTAdZUpPOXotY6FX ncoqnP+ZnHvlmVFuEtnH+KlqB0FFTMIP4kFz0ho= X-Google-Smtp-Source: AGHT+IEUG51SrYGxqrFVabABdMjUAcKCckHEvErqH8od8fPuYIIAMz9p2mGtyazKJ+rZO1dPB6WhDw== X-Received: by 2002:a05:6a00:23d1:b0:687:520e:4b17 with SMTP id g17-20020a056a0023d100b00687520e4b17mr1382835pfc.8.1691634950943; Wed, 09 Aug 2023 19:35:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-stable@nongnu.org Subject: [PATCH 1/5] target/arm: Disable FEAT_TRF in neoverse-v1 Date: Wed, 9 Aug 2023 19:35:44 -0700 Message-Id: <20230810023548.412310-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230810023548.412310-1-richard.henderson@linaro.org> References: <20230810023548.412310-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1691635017150100001 Content-Type: text/plain; charset="utf-8" Self-hosted trace is out of scope for QEMU. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson --- target/arm/tcg/cpu64.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 8019f00bc3..60e5f034d9 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -618,7 +618,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->dcz_blocksize =3D 4; cpu->id_aa64afr0 =3D 0x00000000; cpu->id_aa64afr1 =3D 0x00000000; - cpu->isar.id_aa64dfr0 =3D 0x000001f210305519ull; + cpu->isar.id_aa64dfr0 =3D 0x000000f210305519ull; /* w/o FEAT_TRF */ cpu->isar.id_aa64dfr1 =3D 0x00000000; cpu->isar.id_aa64isar0 =3D 0x1011111110212120ull; /* with FEAT_RNG */ cpu->isar.id_aa64isar1 =3D 0x0111000001211032ull; @@ -628,7 +628,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.id_aa64pfr0 =3D 0x1101110120111112ull; /* GIC filled in lat= er */ cpu->isar.id_aa64pfr1 =3D 0x0000000000000020ull; cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_dfr0 =3D 0x15011099; + cpu->isar.id_dfr0 =3D 0x05011099; /* w/o FEAT_TRF */ cpu->isar.id_isar0 =3D 0x02101110; cpu->isar.id_isar1 =3D 0x13112111; cpu->isar.id_isar2 =3D 0x21232042; --=20 2.34.1 From nobody Tue Feb 10 19:50:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1691635049; cv=none; d=zohomail.com; s=zohoarc; b=QDYOrvC2GcjT2E/P7K4jGVy53dLVjNvUc8VrLTfJ4mnLKn3rlfNXkhTkOj+pwvzk7NQAZoC6fUGAqZpGfIKTJHUTyeiuDDLwdbx6e4Bqe04bhZzQYkzs8UW0o+CzibR8CS11gn80xwkZcwiy5b9cGhsmg9nIk995QpfROM9jUPY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1691635049; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UIUuncYK5LuF874bLlgv9Sndabs4GqkeEig1nWblAF4=; b=c0HSiyuE9GjZn0gkk1JgnLmS7Y0ChHG37iDwGg3I2GwJKNFpHXvl1irMG6fJGoalyVVZHXn9dRXBht0E0cqAYWBamt3O2wrgZ8SGgUitwmouiU5R8HRimv1p2+iTTD6arrYgm2s49DdU0DJJUKkWb6RX01Duhj69K5cQqLNb3iM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1691635049495208.50416482219396; Wed, 9 Aug 2023 19:37:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qTvWr-00011B-Kg; Wed, 09 Aug 2023 22:36:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qTvWl-0000vz-4l for qemu-devel@nongnu.org; Wed, 09 Aug 2023 22:35:55 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qTvWj-0004xO-7W for qemu-devel@nongnu.org; Wed, 09 Aug 2023 22:35:54 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-686f38692b3so370707b3a.2 for ; Wed, 09 Aug 2023 19:35:52 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 88e5accda6..7fedbb34ba 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1074,7 +1074,8 @@ struct ArchCPU { bool prop_lpa2; =20 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ - uint32_t dcz_blocksize; + uint8_t dcz_blocksize; + uint64_t rvbar_prop; /* Property/input signals. */ =20 /* Configurable aspects of GIC cpu interface (which is part of the CPU= ) */ --=20 2.34.1 From nobody Tue Feb 10 19:50:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1691635062; cv=none; d=zohomail.com; s=zohoarc; b=Kk9LNnQpvbQThPFrDESHI7paraaRZBRXwaLq9PbTnZMpQ3r04ZR4OEtmDW3Ef75hmc7wDPxJ4uZ8m3M9+vK2f5noGC1UTWaetnAWrGIjo9G+F2gzVSxZUk/J4PTinkhmWY+nklEamXgoOv8TnI+f2RAzKWsBl1RYt6LZxrsps6o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1691635062; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Nf9XjMu3LHBxXgSXZqt7S0nPQIM+HaIPhW4YZS55L/M=; b=gqVQ+wB7Et6rZYJWI1T6hwtaoxB1ofq6gnoqP5UcnKRPlgCJJvX0JBCfguEcbnolbNrZcHKEQSV17AIbdoT1x0StLjjS8W7cTfYEnNiNWM07AaL/vokMR9c51fqg10dm7ahL4tImZQiSNeZ6mknsmW8iMYozpXbCUZc0xjoUIhw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1691635062583980.8409317689516; Wed, 9 Aug 2023 19:37:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qTvWr-00011y-VK; Wed, 09 Aug 2023 22:36:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qTvWl-0000wg-P9 for qemu-devel@nongnu.org; Wed, 09 Aug 2023 22:35:57 -0400 Received: from mail-qk1-x735.google.com ([2607:f8b0:4864:20::735]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qTvWj-0004xl-Uq for qemu-devel@nongnu.org; Wed, 09 Aug 2023 22:35:55 -0400 Received: by mail-qk1-x735.google.com with SMTP id af79cd13be357-76ad8892d49so32778185a.1 for ; Wed, 09 Aug 2023 19:35:53 -0700 (PDT) Received: from stoup.. ([2602:47:d483:7301:6bf0:9674:6ac4:f74c]) by smtp.gmail.com with ESMTPSA id z7-20020aa791c7000000b0066ebaeb149dsm287283pfa.88.2023.08.09.19.35.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Aug 2023 19:35:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1691634953; x=1692239753; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Nf9XjMu3LHBxXgSXZqt7S0nPQIM+HaIPhW4YZS55L/M=; b=BY3fq7DTH1R8/mWIJh41Tbldrn7lZoQn9OFh9Eq4rZSq+en2APuk6TI6ocT+qBcg+f dGvr4UzJ0SJghLhapRh/s2IaevB7OOPdW9FNH4vvUTll3IhJmoMscePcz2ulf9N+7Elz gys/VIGsxW4VyOJ8bjLRHlrR2xRF9zf84QDS41ndOCGOiWhZwiqbcSv1iqdK0Q1lPYzJ pidYXRmuYMYKADxoNFzTU8CDeK7F5OaI+bo8Oo0Biruvic79V6SKf9p9Ch/kaId3yDdz BkmvhbEFSHdT8bEwwb5l0G51AHI7bXhASet+lhwbaS1dH81BT/s6RMC/tLs5KtVSpCCL P57g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691634953; x=1692239753; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Nf9XjMu3LHBxXgSXZqt7S0nPQIM+HaIPhW4YZS55L/M=; b=Lk/vYVBuRWhNASylmS2ce4SPnVO7voS1HftdvEax1SAO+eVvQbpEvA1qgV19DHZoLy nJ9F7yRflcuZjH5YzBU8gO3eoqdO/t3r4EMY2oxzNu0qkAZFdDtKdqhkHb+RDeW5fvn+ TPnQK6WY5sBHA74+peJk35W3IWeJJA4YRzsT+436iSH8wX7XaLQ9YiseMqZaJIy/MhdQ /I6QM0F+KoXfi29mwZ6AdewAez+JkAvtxYaSUAnRpXsbwszg/wqB+flrSt+uB2mT+dyt TMQNevvfIli2kx8l5EDNbKAyegPiilrSJiuJ/+JvxVLzz6MdnyxMZaZVN8lPLI33CxWm RUCA== X-Gm-Message-State: AOJu0YyVD8pM4z5Q24VTU0Z+t4c+AXP3qH/61ESukP2E2cbOMU5+7yu/ pcmO3Mwuc/ikvrYyBpf+P4WGwfucNTIUedKNSCc= X-Google-Smtp-Source: AGHT+IEZq4A0W6kGPTJ3bKFHLySh1crqkio8cDWrvDuofqH+E4pHHH3bV5iwYohX1xm9Kc66f8VHYw== X-Received: by 2002:a05:620a:3953:b0:768:14a8:9eb with SMTP id qs19-20020a05620a395300b0076814a809ebmr1113205qkn.9.1691634952888; Wed, 09 Aug 2023 19:35:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 3/5] target/arm: Allow cpu to configure GM blocksize Date: Wed, 9 Aug 2023 19:35:46 -0700 Message-Id: <20230810023548.412310-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230810023548.412310-1-richard.henderson@linaro.org> References: <20230810023548.412310-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::735; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x735.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1691635063264100002 Content-Type: text/plain; charset="utf-8" Previously we hard-coded the blocksize with GMID_EL1_BS. But the value we choose for -cpu max does not match the value that cortex-a710 uses. Mirror the way we handle dcz_blocksize. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/internals.h | 6 ----- target/arm/tcg/translate.h | 2 ++ target/arm/helper.c | 11 +++++--- target/arm/tcg/cpu64.c | 1 + target/arm/tcg/mte_helper.c | 46 ++++++++++++++++++++++------------ target/arm/tcg/translate-a64.c | 5 ++-- 7 files changed, 45 insertions(+), 28 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7fedbb34ba..dfa02eb4dc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1075,6 +1075,8 @@ struct ArchCPU { =20 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ uint8_t dcz_blocksize; + /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ + uint8_t gm_blocksize; =20 uint64_t rvbar_prop; /* Property/input signals. */ =20 diff --git a/target/arm/internals.h b/target/arm/internals.h index 0f01bc32a8..6fcf12c178 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1243,12 +1243,6 @@ void arm_log_exception(CPUState *cs); =20 #endif /* !CONFIG_USER_ONLY */ =20 -/* - * The log2 of the words in the tag block, for GMID_EL1.BS. - * The is the maximum, 256 bytes, which manipulates 64-bits of tags. - */ -#define GMID_EL1_BS 6 - /* * SVE predicates are 1/8 the size of SVE vectors, and cannot use * the same simd_desc() encoding due to restrictions on size. diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index d1cacff0b2..f748ba6f39 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -151,6 +151,8 @@ typedef struct DisasContext { int8_t btype; /* A copy of cpu->dcz_blocksize. */ uint8_t dcz_blocksize; + /* A copy of cpu->gm_blocksize. */ + uint8_t gm_blocksize; /* True if this page is guarded. */ bool guarded_page; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 50f61e42ca..f5effa30f7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7643,10 +7643,6 @@ static const ARMCPRegInfo mte_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 6, .access =3D PL1_RW, .accessfn =3D access_mte, .fieldoffset =3D offsetof(CPUARMState, cp15.gcr_el1) }, - { .name =3D "GMID_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 4, - .access =3D PL1_R, .accessfn =3D access_aa64_tid5, - .type =3D ARM_CP_CONST, .resetvalue =3D GMID_EL1_BS }, { .name =3D "TCO", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 7, .type =3D ARM_CP_NO_RAW, @@ -9237,6 +9233,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) * then define only a RAZ/WI version of PSTATE.TCO. */ if (cpu_isar_feature(aa64_mte, cpu)) { + ARMCPRegInfo gmid_reginfo =3D { + .name =3D "GMID_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 4, + .access =3D PL1_R, .accessfn =3D access_aa64_tid5, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->gm_blocksize, + }; + define_one_arm_cp_reg(cpu, &gmid_reginfo); define_arm_cp_regs(cpu, mte_reginfo); define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 60e5f034d9..5ca9070c14 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -868,6 +868,7 @@ void aarch64_max_tcg_initfn(Object *obj) cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ cpu->dcz_blocksize =3D 7; /* 512 bytes */ #endif + cpu->gm_blocksize =3D 6; /* 256 bytes */ =20 cpu->sve_vq.supported =3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); cpu->sme_vq.supported =3D SVE_VQ_POW2_MAP; diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 9c64def081..3640c6e57f 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -421,46 +421,54 @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr) } } =20 -#define LDGM_STGM_SIZE (4 << GMID_EL1_BS) - uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) { int mmu_idx =3D cpu_mmu_index(env, false); uintptr_t ra =3D GETPC(); + int gm_bs =3D env_archcpu(env)->gm_blocksize; + int gm_bs_bytes =3D 4 << gm_bs; void *tag_mem; =20 - ptr =3D QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE); + ptr =3D QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); =20 /* Trap if accessing an invalid page. */ tag_mem =3D allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD, - LDGM_STGM_SIZE, MMU_DATA_LOAD, - LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra); + gm_bs_bytes, MMU_DATA_LOAD, + gm_bs_bytes / (2 * TAG_GRANULE), ra); =20 /* The tag is squashed to zero if the page does not support tags. */ if (!tag_mem) { return 0; } =20 - QEMU_BUILD_BUG_ON(GMID_EL1_BS !=3D 6); /* - * We are loading 64-bits worth of tags. The ordering of elements - * within the word corresponds to a 64-bit little-endian operation. + * The ordering of elements within the word corresponds to + * a little-endian operation. */ - return ldq_le_p(tag_mem); + switch (gm_bs) { + case 6: + /* 256 bytes -> 16 tags -> 64 result bits */ + return ldq_le_p(tag_mem); + default: + /* cpu configured with unsupported gm blocksize. */ + g_assert_not_reached(); + } } =20 void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) { int mmu_idx =3D cpu_mmu_index(env, false); uintptr_t ra =3D GETPC(); + int gm_bs =3D env_archcpu(env)->gm_blocksize; + int gm_bs_bytes =3D 4 << gm_bs; void *tag_mem; =20 - ptr =3D QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE); + ptr =3D QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); =20 /* Trap if accessing an invalid page. */ tag_mem =3D allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, - LDGM_STGM_SIZE, MMU_DATA_LOAD, - LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra); + gm_bs_bytes, MMU_DATA_LOAD, + gm_bs_bytes / (2 * TAG_GRANULE), ra); =20 /* * Tag store only happens if the page support tags, @@ -470,12 +478,18 @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uin= t64_t val) return; } =20 - QEMU_BUILD_BUG_ON(GMID_EL1_BS !=3D 6); /* - * We are storing 64-bits worth of tags. The ordering of elements - * within the word corresponds to a 64-bit little-endian operation. + * The ordering of elements within the word corresponds to + * a little-endian operation. */ - stq_le_p(tag_mem, val); + switch (gm_bs) { + case 6: + stq_le_p(tag_mem, val); + break; + default: + /* cpu configured with unsupported gm blocksize. */ + g_assert_not_reached(); + } } =20 void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 5fa1257d32..d822d9a9af 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3786,7 +3786,7 @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag = *a) gen_helper_stgm(cpu_env, addr, tcg_rt); } else { MMUAccessType acc =3D MMU_DATA_STORE; - int size =3D 4 << GMID_EL1_BS; + int size =3D 4 << s->gm_blocksize; =20 clean_addr =3D clean_data_tbi(s, addr); tcg_gen_andi_i64(clean_addr, clean_addr, -size); @@ -3818,7 +3818,7 @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag = *a) gen_helper_ldgm(tcg_rt, cpu_env, addr); } else { MMUAccessType acc =3D MMU_DATA_LOAD; - int size =3D 4 << GMID_EL1_BS; + int size =3D 4 << s->gm_blocksize; =20 clean_addr =3D clean_data_tbi(s, addr); tcg_gen_andi_i64(clean_addr, clean_addr, -size); @@ -13900,6 +13900,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->cp_regs =3D arm_cpu->cp_regs; dc->features =3D env->features; dc->dcz_blocksize =3D arm_cpu->dcz_blocksize; + dc->gm_blocksize =3D arm_cpu->gm_blocksize; =20 #ifdef CONFIG_USER_ONLY /* In sve_probe_page, we assume TBI is enabled. */ --=20 2.34.1 From nobody Tue Feb 10 19:50:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1691635007; cv=none; d=zohomail.com; s=zohoarc; b=I7N6wKj2dmM8OAXa24qOeN2MiQmkYgYeaYF6J/DAXoNFTpgXEVNSsAXNkCLom2IOW61sh1rdDJfUZML0SckSm3xUGcA0+Vh4PldDUPE+Zu+INsyileXquaa5EqphKrF3wGOnmpkUjb3Ry/t65UQ37y5WG+BbKb5TUJdnZhqFzcg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1691635007; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DxgqNR4/eVoHsIiiFC5Te9EYL+Uy4Gcd+N/BbwRB+MQ=; b=aqPowUrHyrsyBj0aaeZ93+Zcnj+8aHq0uis8AOzJNV+KRK4cMGYYD87qlaAqszVZc4vhI7CP2ja8aQ2A63pv5vrNXHJxTmq9DG5cFYj0nYCTJOcgyI+M92wrVAKY18K9qAvRK4bFpoATFIxD0dsV/ADKecUbFKdBc5XIxLlk70M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1691635007113237.44027864507325; Wed, 9 Aug 2023 19:36:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qTvWq-00010L-U2; Wed, 09 Aug 2023 22:36:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qTvWn-0000x7-3c for qemu-devel@nongnu.org; Wed, 09 Aug 2023 22:35:57 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qTvWk-0004yA-TX for qemu-devel@nongnu.org; Wed, 09 Aug 2023 22:35:56 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-686f0d66652so382587b3a.2 for ; Wed, 09 Aug 2023 19:35:54 -0700 (PDT) Received: from stoup.. ([2602:47:d483:7301:6bf0:9674:6ac4:f74c]) by smtp.gmail.com with ESMTPSA id z7-20020aa791c7000000b0066ebaeb149dsm287283pfa.88.2023.08.09.19.35.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Aug 2023 19:35:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1691634953; x=1692239753; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DxgqNR4/eVoHsIiiFC5Te9EYL+Uy4Gcd+N/BbwRB+MQ=; b=f5dJmtSxVZskh73aGB1ynAf/qnaTllGhYpUrauK0PYHAXj020th+U2B0UqM7akwREb NrQtRV4stAv1H7oaJU5dteu3ruw/OYMoq8VoDq8vMzEHgUrnwUPPmrsT2oCisxJ3f1P7 UOPiIyCHMTwt65dO6SDb3rRvkOx/7h+V6ndv+ouW1HRQLRVStlJNObnoaEDWU+9c6o9g x0Y09fcp1EmDEeYtw1YA1/bPzHhYzDZA2pToNM5mtwSEynVp4I5q+IQRhdicNX7I6L4I 83hSNCt6jUvm8L4Wj3Xp2w0G9sKhDUq6qiQqoMAKiqPKjWCftnT7i89ra6q208yoD26o 9B4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691634953; x=1692239753; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DxgqNR4/eVoHsIiiFC5Te9EYL+Uy4Gcd+N/BbwRB+MQ=; b=Y+bef9XXcExaRBP/nxWZ7w3lCEbB3q4XCdZERsRH9I3dQ5g8UUrF7fiq0bau0Q+nxA 12tMvAZP4jEpxZaWf5IJQiZHEQs/TvRomlNAlR10YAHAji/uZkXSm1aNJFVKcJJUKIYI /R2iqapSGdnn+zOndNFEIXSFwB0cGj2iMqsb8Ymhjh+vru15474qh1/ZSSHwQ+K74b/z WT2Ps//aNn0qHr0GgSsJq+kM4bTBS8UQieRivYcL5sLhXNxYQwU0GUDu5btlfGvQ77Or nGIY7wEw76CsSUgL3o+Y18FLuyffEM1vNXH47TQup414WPyb6s64INli5ABGmShcd2eY jGbw== X-Gm-Message-State: AOJu0Yx97Q27SYcwJ9E2SZb2cUSHv+SilADsvE7CvzqE9Jqh82hiP5aL HjRT2ybPKGssFEpL0prnOxckJYGCrg3cnqlFtWM= X-Google-Smtp-Source: AGHT+IEvL+EHVOmMwbaEjyap8Hl+Cojnkete5hPgoTVeLWn2ZJsso2QHZ9V8oA0fGtHzAkb3a5CVKA== X-Received: by 2002:a05:6a00:1588:b0:64d:46b2:9a58 with SMTP id u8-20020a056a00158800b0064d46b29a58mr1753737pfk.26.1691634953603; Wed, 09 Aug 2023 19:35:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 4/5] target/arm: Support more GM blocksizes Date: Wed, 9 Aug 2023 19:35:47 -0700 Message-Id: <20230810023548.412310-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230810023548.412310-1-richard.henderson@linaro.org> References: <20230810023548.412310-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1691635008080100001 Content-Type: text/plain; charset="utf-8" Support all of the easy GM block sizes. Use direct memory operations, since the pointers are aligned. While BS=3D2 (16 bytes, 1 tag) is a legal setting, that requires an atomic store of one nibble. This is not difficult, but there is also no point in supporting it until required. Note that cortex-a710 sets GM blocksize to match its cacheline size of 64 bytes. I expect many implementations will also match the cacheline, which makes 16 bytes very unlikely. Signed-off-by: Richard Henderson --- target/arm/tcg/mte_helper.c | 61 ++++++++++++++++++++++++++++++++----- 1 file changed, 53 insertions(+), 8 deletions(-) diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 3640c6e57f..6faf4e42d5 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -428,6 +428,8 @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) int gm_bs =3D env_archcpu(env)->gm_blocksize; int gm_bs_bytes =3D 4 << gm_bs; void *tag_mem; + uint64_t ret; + int shift; =20 ptr =3D QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); =20 @@ -443,16 +445,39 @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) =20 /* * The ordering of elements within the word corresponds to - * a little-endian operation. + * a little-endian operation. Computation of shift comes from + * + * index =3D address + * data =3D tag + * + * Because of the alignment of ptr above, BS=3D6 has shift=3D0. + * All memory operations are aligned. */ switch (gm_bs) { - case 6: - /* 256 bytes -> 16 tags -> 64 result bits */ - return ldq_le_p(tag_mem); - default: + case 2: /* cpu configured with unsupported gm blocksize. */ g_assert_not_reached(); + case 3: + /* 32 bytes -> 2 tags -> 8 result bits */ + ret =3D *(uint8_t *)tag_mem; + break; + case 4: + /* 64 bytes -> 4 tags -> 16 result bits */ + ret =3D cpu_to_le16(*(uint16_t *)tag_mem); + break; + case 5: + /* 128 bytes -> 8 tags -> 32 result bits */ + ret =3D cpu_to_le32(*(uint32_t *)tag_mem); + break; + case 6: + /* 256 bytes -> 16 tags -> 64 result bits */ + return cpu_to_le64(*(uint64_t *)tag_mem); + default: + /* cpu configured with invalid gm blocksize. */ + g_assert_not_reached(); } + shift =3D extract64(ptr, LOG2_TAG_GRANULE, 4) * 4; + return ret << shift; } =20 void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) @@ -462,6 +487,7 @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint6= 4_t val) int gm_bs =3D env_archcpu(env)->gm_blocksize; int gm_bs_bytes =3D 4 << gm_bs; void *tag_mem; + int shift; =20 ptr =3D QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); =20 @@ -480,14 +506,33 @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uin= t64_t val) =20 /* * The ordering of elements within the word corresponds to - * a little-endian operation. + * a little-endian operation. See LDGM for comments on shift. + * All memory operations are aligned. */ + shift =3D extract64(ptr, LOG2_TAG_GRANULE, 4) * 4; + val >>=3D shift; switch (gm_bs) { + case 2: + /* cpu configured with unsupported gm blocksize. */ + g_assert_not_reached(); + case 3: + /* 32 bytes -> 2 tags -> 8 result bits */ + *(uint8_t *)tag_mem =3D val; + break; + case 4: + /* 64 bytes -> 4 tags -> 16 result bits */ + *(uint16_t *)tag_mem =3D cpu_to_le16(val); + break; + case 5: + /* 128 bytes -> 8 tags -> 32 result bits */ + *(uint32_t *)tag_mem =3D cpu_to_le32(val); + break; case 6: - stq_le_p(tag_mem, val); + /* 256 bytes -> 16 tags -> 64 result bits */ + *(uint64_t *)tag_mem =3D cpu_to_le64(val); break; default: - /* cpu configured with unsupported gm blocksize. */ + /* cpu configured with invalid gm blocksize. */ g_assert_not_reached(); } } --=20 2.34.1 From nobody Tue Feb 10 19:50:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1691635046; cv=none; d=zohomail.com; s=zohoarc; b=NvBwR2bYoeXRpauO9SGD7M3AIh7LTSfNZpDLIErJpXfJj4IEJSsr+WT1ayXeRCUGU/MMwJmUFwRk8ZKptM1lw640hLa2Dgnurzqw3o5REyszb0kVbErB4clhNq2OagC1A30q+Iz69FB6ADd32BOjyVu9NS1nLvEFh6gAuBX8A88= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1691635046; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zAYDJTdawZ3d8edXM0V7IrgfXqP83Zo/hY/QUM86iSw=; b=m+jfvrBnxC+HiKE0rAuZi2DVuliMyl2UOvsR7AQKr7LqXefLO4fxqhoEHfC3VRc+rWVC+6NWMIObSZpKeSeY9Wg7y2bDGs7Y0TPqZDsyd2zC1Wz8SsWbtuubkmEmd8WOPXMlnGIH8oLsLp4wr1h+xIJRqHtpT4FLokkIgb5K/P0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169163504689750.828413275422236; Wed, 9 Aug 2023 19:37:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qTvWr-00011M-NL; Wed, 09 Aug 2023 22:36:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qTvWo-0000yX-IK for qemu-devel@nongnu.org; Wed, 09 Aug 2023 22:35:59 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qTvWl-0004ye-VT for qemu-devel@nongnu.org; Wed, 09 Aug 2023 22:35:57 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-686daaa5f1fso314632b3a.3 for ; Wed, 09 Aug 2023 19:35:55 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson --- docs/system/arm/virt.rst | 1 + hw/arm/virt.c | 1 + target/arm/tcg/cpu64.c | 167 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 169 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 51cdac6841..e1697ac8f4 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -58,6 +58,7 @@ Supported guest CPU types: - ``cortex-a57`` (64-bit) - ``cortex-a72`` (64-bit) - ``cortex-a76`` (64-bit) +- ``cortex-a710`` (64-bit) - ``a64fx`` (64-bit) - ``host`` (with KVM only) - ``neoverse-n1`` (64-bit) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 7d9dbc2663..d1522c305d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -211,6 +211,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a55"), ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a76"), + ARM_CPU_TYPE_NAME("cortex-a710"), ARM_CPU_TYPE_NAME("a64fx"), ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("neoverse-v1"), diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 5ca9070c14..6f555a39ce 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -700,6 +700,172 @@ static void aarch64_neoverse_v1_initfn(Object *obj) aarch64_add_sve_properties(obj); } =20 +static const ARMCPRegInfo cortex_a710_cp_reginfo[] =3D { + /* TODO: trapped by HCR_EL2.TIDCP */ + { .name =3D "CPUACTLR4_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUECTLR2_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 5, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR5_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 8, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR6_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 8, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR7_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 8, .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPPMCR4_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 2, .opc2 =3D 4, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPPMCR5_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 2, .opc2 =3D 5, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPPMCR6_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 2, .opc2 =3D 6, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 4, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPOR2_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 8, .opc2 =3D 4, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPMR2_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 8, .opc2 =3D 5, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + + /* + * Stub RAMINDEX, as we don't actually implement caches, + * BTB, or anything else with cpu internal memory. + * "Read" zeros into the IDATA* and DDATA* output registers. + */ + { .name =3D "RAMINDEX_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, + .access =3D PL3_W, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IDATA0_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, + .access =3D PL3_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IDATA1_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 0, .opc2 =3D 1, + .access =3D PL3_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IDATA2_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 0, .opc2 =3D 2, + .access =3D PL3_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "DDATA0_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 1, .opc2 =3D 0, + .access =3D PL3_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "DDATA1_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 1, .opc2 =3D 1, + .access =3D PL3_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "DDATA2_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 1, .opc2 =3D 2, + .access =3D PL3_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, +}; + +static void define_cortex_a710_cp_reginfo(ARMCPU *cpu) +{ + /* + * The Cortex A710 has all of the Neoverse V1's IMPDEF + * registers and a few more of its own. + */ + define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); + define_arm_cp_regs(cpu, neoverse_v1_cp_reginfo); + define_arm_cp_regs(cpu, cortex_a710_cp_reginfo); +} + +static void aarch64_a710_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a710"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by Section B.4: AArch64 registers */ + cpu->midr =3D 0x412FD471; /* r2p1 */ + cpu->revidr =3D cpu->midr; /* mirror midr: "no significance" */ + cpu->isar.id_pfr0 =3D 0x21110131; + cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + cpu->isar.id_dfr0 =3D 0x06011099; /* w/o FEAT_TRF */ + cpu->id_afr0 =3D 0; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x11011121; + cpu->isar.id_mmfr4 =3D 0x21021110; + cpu->isar.id_isar6 =3D 0x01111111; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->isar.id_pfr2 =3D 0x00000011; + /* GIC filled in later; w/o FEAT_MPAM */ + cpu->isar.id_aa64pfr0 =3D 0x1201101120111112ull; + cpu->isar.id_aa64pfr1 =3D 0x0000000000000221ull; + cpu->isar.id_aa64zfr0 =3D 0x0000110100110021ull; + cpu->isar.id_aa64dfr0 =3D 0x000000f210305619ull; /* w/o FEAT_{TRF,TRB= E} */ + cpu->isar.id_aa64dfr1 =3D 0; + cpu->id_aa64afr0 =3D 0; + cpu->id_aa64afr1 =3D 0; + cpu->isar.id_aa64isar0 =3D 0x0221111110212120ull; + cpu->isar.id_aa64isar1 =3D 0x0010111101211032ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000022200101122ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x1221011110101011ull; + cpu->clidr =3D 0x0000002282000023ull; + cpu->gm_blocksize =3D 4; + cpu->ctr =3D 0x00000004b444c004ull; /* with DIC set */ + cpu->dcz_blocksize =3D 4; + /* TODO FEAT_MPAM: mpamidr_el1 =3D 0x0000_0001_0006_003f */ + + /* Section B.5.2: PMCR_EL0 */ + cpu->isar.reset_pmcr_el0 =3D 0xa000; /* with 20 counters */ + + /* Section B.6.7: ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + + /* Section 14: Scalable Vector Extensions support */ + cpu->sve_vq.supported =3D 1 << 0; /* 128bit */ + + /* + * The cortex-a710 TRM does not list CCSIDR values. + * The layout of the cache is in text in Table 7-1 (L1-I), + * Table 8-1 (L1-D), and Table 9-1 (L2). + * + * L1: 4-way set associative 64-byte line size, total either 32K or 64= K. + * We pick 64K, so this has 256 sets. + * + * L2: 8-way set associative 64 byte line size, total either 256K or 5= 12K. + * We pick 512K, so this has 1024 sets. + */ + cpu->ccsidr[0] =3D 0x000000ff0000001aull; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x000000ff0000001aull; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x000003ff0000003aull; /* 512KB L2 cache */ + + /* ??? Not documented -- copied from neoverse-v1 */ + cpu->reset_sctlr =3D 0x30c50838; + + define_cortex_a710_cp_reginfo(cpu); + aarch64_add_pauth_properties(obj); + aarch64_add_sve_properties(obj); +} + /* * -cpu max: a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c; @@ -889,6 +1055,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a55", .initfn =3D aarch64_a55_initfn }, { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn }, + { .name =3D "cortex-a710", .initfn =3D aarch64_a710_initfn }, { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "neoverse-v1", .initfn =3D aarch64_neoverse_v1_init= fn }, --=20 2.34.1