From nobody Thu Nov 28 14:46:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1691495888; cv=none; d=zohomail.com; s=zohoarc; b=SbCYN4g6FQfxlG/M+84YKGwriaOIyiMiKPeWw6dlHU+I1wHwNRAZZR4Gxuth+7sfSRqrxWujhsZCF0k4hKS2gJVaBw6cklt5ASscrZVqRf+c8FAV7NShmZPn5TPRN0A6NifdjMLvZwRD1e9+ty6fJq+2iqCxquD14T8MKA5IQDU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1691495888; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=KSmZtiHoXj0fPGC7TVY1TyJIu6083yk5gIVLleSH8jM=; b=UVg0/z4P45zr1ZzNG8cewwYodKJoYEFGgHTeRAqhOG7vOJ+TPXJzz2l//C+jK7kfRQhzWVza1WnybPpBejCwdOwwRJF1PFfrNQDLjGYn+0Ld8wwsz234j99A2IFcu5lHiWo07APLN92lnRZ6kbF/C9tsi3J6/W9bOm3WytI2s6A= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1691495888931211.2514255475346; Tue, 8 Aug 2023 04:58:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qTLLc-0001r0-7U; Tue, 08 Aug 2023 07:58:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qTLLR-0001j6-BL for qemu-devel@nongnu.org; Tue, 08 Aug 2023 07:57:50 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qTLLN-0001S0-7k for qemu-devel@nongnu.org; Tue, 08 Aug 2023 07:57:48 -0400 Received: from lhrpeml500005.china.huawei.com (unknown [172.18.147.207]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4RKs6B4l5Vz67mnJ; Tue, 8 Aug 2023 19:53:54 +0800 (CST) Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 8 Aug 2023 12:57:42 +0100 To: CC: Gavin Shan , , James Morse , "peter . maydell @ linaro . org" , , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Shameerali Kolothum Thodi , Yicong Yang Subject: [RFC PATCH 1/5] hw/acpi: Add PPTT cache descriptions Date: Tue, 8 Aug 2023 12:57:09 +0100 Message-ID: <20230808115713.2613-2-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230808115713.2613-1-Jonathan.Cameron@huawei.com> References: <20230808115713.2613-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhrpeml500001.china.huawei.com (7.191.163.213) To lhrpeml500005.china.huawei.com (7.191.163.240) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1691495890929100003 Content-Type: text/plain; charset="utf-8" Current PPTT tables generated by QEMU only provide information on CPU topology and neglect the description of Caches. This patch adds flexible definition of those caches and updates the table version to 3 to allow for the per CPU cache instance IDs needed for cross references from the MPAM table. If MPAM is not being used, then a unified description can be used, greatly reducing the resulting table size. New machine parameters are used to control the cache toplogy. cache-cluster-start-level: Which caches are associated with the cluster level of the topology. e.g cache-cluster-start-level=3D2 results in shared l2 cache across a cluster. cache-numa-start-level: Which caches are associate with the NUMA (in qemu this is currently the physical package level). For example cache-cluster-start-level=3D2,cache-numa-start-level=3D3 gives private l1, cluster shared l2 and package shared L3. FIXME: Test updates. Signed-off-by: Jonathan Cameron --- qapi/machine.json | 8 +- include/hw/acpi/aml-build.h | 19 +++- include/hw/boards.h | 4 + hw/acpi/aml-build.c | 189 ++++++++++++++++++++++++++++++++++-- hw/arm/virt-acpi-build.c | 130 ++++++++++++++++++++++++- hw/core/machine-smp.c | 8 ++ hw/loongarch/acpi-build.c | 2 +- 7 files changed, 350 insertions(+), 10 deletions(-) diff --git a/qapi/machine.json b/qapi/machine.json index a08b6576ca..cc86784641 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -1494,6 +1494,10 @@ # @maxcpus: maximum number of hotpluggable virtual CPUs in the virtual # machine # +# @cache-cluster-start-level: Level of first cache attached to cluster +# +# @cache-node-start-level: Level of first cache attached to cluster +# # Since: 6.1 ## { 'struct': 'SMPConfiguration', 'data': { @@ -1503,7 +1507,9 @@ '*clusters': 'int', '*cores': 'int', '*threads': 'int', - '*maxcpus': 'int' } } + '*maxcpus': 'int', + '*cache-cluster-start-level': 'int', + '*cache-node-start-level': 'int'} } =20 ## # @x-query-irq: diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index d1fb08514b..055b74820d 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -489,8 +489,25 @@ void build_srat_memory(GArray *table_data, uint64_t ba= se, void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms, const char *oem_id, const char *oem_table_id); =20 +typedef enum ACPIPPTTCacheType { + DATA, + INSTRUCTION, + UNIFIED, +} ACPIPPTTCacheType; + +typedef struct ACPIPPTTCache { + ACPIPPTTCacheType type; + int sets; + int size; + int associativity; + int linesize; + unsigned int pptt_id; + int level; +} ACPIPPTTCache; + void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, - const char *oem_id, const char *oem_table_id); + const char *oem_id, const char *oem_table_id, + int num_caches, ACPIPPTTCache *caches); =20 void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f, const char *oem_id, const char *oem_table_id); diff --git a/include/hw/boards.h b/include/hw/boards.h index ed83360198..6e8ab92684 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -316,6 +316,8 @@ typedef struct DeviceMemoryState { * @cores: the number of cores in one cluster * @threads: the number of threads in one core * @max_cpus: the maximum number of logical processors on the machine + * @cache_cluster_start_level: First cache level attached to cluster + * @cache_node_start_level: First cache level attached to node */ typedef struct CpuTopology { unsigned int cpus; @@ -325,6 +327,8 @@ typedef struct CpuTopology { unsigned int cores; unsigned int threads; unsigned int max_cpus; + unsigned int cache_cluster_start_level; + unsigned int cache_node_start_level; } CpuTopology; =20 /** diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index ea331a20d1..e103cd638f 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -1994,32 +1994,175 @@ static void build_processor_hierarchy_node(GArray = *tbl, uint32_t flags, } } =20 +static void build_cache_nodes(GArray *tbl, ACPIPPTTCache *cache, + uint32_t next_offset, + bool has_id, unsigned int id) +{ + int val; + + /* Type 1 - cache */ + build_append_byte(tbl, 1); + /* Length */ + build_append_byte(tbl, 28); + /* Reserved */ + build_append_int_noprefix(tbl, 0, 2); + /* Flags - everything except possibly the ID */ + build_append_int_noprefix(tbl, has_id ? 0xff : 0x7f, 4); + /* Offset of next cache up */ + build_append_int_noprefix(tbl, next_offset, 4); + build_append_int_noprefix(tbl, cache->size, 4); + build_append_int_noprefix(tbl, cache->sets, 4); + build_append_byte(tbl, cache->associativity); + /* Read and Write allocate amd WB */ + val =3D 0x3 | (1 << 4); + switch (cache->type) { + case INSTRUCTION: + val |=3D (1 << 2); + break; + case DATA: + val |=3D (0 << 2); /* Data */ + break; + case UNIFIED: + val |=3D (3 << 2); /* Unified */ + break; + } + build_append_byte(tbl, val); + build_append_int_noprefix(tbl, cache->linesize, 2); + build_append_int_noprefix(tbl, + has_id ? + (cache->type << 24) | (cache->level << 16) |= id : + 0, 4); +} + +static void build_caches_subset(GArray *table_data, uint32_t pptt_start, + int num_caches, ACPIPPTTCache *caches, + bool assign_ids, int base_id, + uint8_t level_high, uint8_t level_low, + uint32_t *data_offset, uint32_t *instr_off= set) +{ + uint32_t next_level_offset_data =3D 0, next_level_offset_instruction = =3D 0; + uint32_t this_offset, next_offset =3D 0; + int c, l; + + /* Walk caches from top to bottom */ + + for (l =3D level_high; l >=3D level_low; l--) { /* Walk down levels */ + for (c =3D 0; c < num_caches; c++) { + if (caches[c].level !=3D l) { + continue; + } + + /* Assume only unified above l1 for now */ + this_offset =3D table_data->len - pptt_start; + switch (caches[c].type) { + case INSTRUCTION: + next_offset =3D next_level_offset_instruction; + break; + case DATA: + next_offset =3D next_level_offset_data; + break; + case UNIFIED: + /* Either is fine here - hopefully */ + next_offset =3D next_level_offset_instruction; + break; + } + build_cache_nodes(table_data, &caches[c], next_offset, + assign_ids, base_id); + switch (caches[c].type) { + case INSTRUCTION: + next_level_offset_instruction =3D this_offset; + break; + case DATA: + next_level_offset_data =3D this_offset; + break; + case UNIFIED: + next_level_offset_instruction =3D this_offset; + next_level_offset_data =3D this_offset; + break; + } + *data_offset =3D next_level_offset_data; + *instr_offset =3D next_level_offset_instruction; + } + } +} + /* * ACPI spec, Revision 6.3 * 5.2.29 Processor Properties Topology Table (PPTT) */ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, - const char *oem_id, const char *oem_table_id) + const char *oem_id, const char *oem_table_id, + int num_caches, ACPIPPTTCache *caches) { + bool share_structs =3D false; MachineClass *mc =3D MACHINE_GET_CLASS(ms); CPUArchIdList *cpus =3D ms->possible_cpus; int64_t socket_id =3D -1, cluster_id =3D -1, core_id =3D -1; uint32_t socket_offset =3D 0, cluster_offset =3D 0, core_offset =3D 0; uint32_t pptt_start =3D table_data->len; int n; - AcpiTable table =3D { .sig =3D "PPTT", .rev =3D 2, + AcpiTable table =3D { .sig =3D "PPTT", .rev =3D 3, .oem_id =3D oem_id, .oem_table_id =3D oem_table_id= }; + uint32_t l1_data_offset =3D 0; + uint32_t l1_instr_offset =3D 0; + uint32_t cluster_data_offset =3D 0; + uint32_t cluster_instr_offset =3D 0; + uint32_t node_data_offset =3D 0; + uint32_t node_instr_offset =3D 0; + int top_node =3D 7; + int top_cluster =3D 7; + int top_core =3D 7; =20 acpi_table_begin(&table, table_data); =20 + /* Let us have a unified cache description for now */ + + if (share_structs && num_caches >=3D 1) { + if (ms->smp.cache_node_start_level) { + build_caches_subset(table_data, pptt_start, num_caches, caches, + false, 0, + top_node, ms->smp.cache_node_start_level, + &node_data_offset, &node_instr_offset); + top_cluster =3D ms->smp.cache_node_start_level - 1; + } + /* Assumption that some caches below this */ + if (ms->smp.cache_cluster_start_level) { + build_caches_subset(table_data, pptt_start, num_caches, caches, + false, 0, + top_cluster, ms->smp.cache_cluster_start_= level, + &cluster_data_offset, &cluster_instr_offse= t); + top_core =3D ms->smp.cache_cluster_start_level - 1; + } + build_caches_subset(table_data, pptt_start, num_caches, caches, + false, 0, + top_core , 0, + &l1_data_offset, &l1_instr_offset); + } + /* * This works with the assumption that cpus[n].props.*_id has been * sorted from top to down levels in mc->possible_cpu_arch_ids(). * Otherwise, the unexpected and duplicated containers will be * created. */ + for (n =3D 0; n < cpus->len; n++) { if (cpus->cpus[n].props.socket_id !=3D socket_id) { + uint32_t priv_rsrc[2]; + int num_priv =3D 0; + + if (!share_structs && ms->smp.cache_node_start_level) { + build_caches_subset(table_data, pptt_start, num_caches, ca= ches, + true, n, + top_node, ms->smp.cache_node_start_lev= el, + &node_data_offset, &node_instr_offset); + top_cluster =3D ms->smp.cache_node_start_level - 1; + } + priv_rsrc[0] =3D node_instr_offset; + priv_rsrc[1] =3D node_data_offset; + if (node_instr_offset || node_data_offset) { + num_priv =3D node_instr_offset =3D=3D node_data_offset ? 1= : 2; + } assert(cpus->cpus[n].props.socket_id > socket_id); socket_id =3D cpus->cpus[n].props.socket_id; cluster_id =3D -1; @@ -2027,36 +2170,70 @@ void build_pptt(GArray *table_data, BIOSLinker *lin= ker, MachineState *ms, socket_offset =3D table_data->len - pptt_start; build_processor_hierarchy_node(table_data, (1 << 0), /* Physical package */ - 0, socket_id, NULL, 0); + 0, socket_id, priv_rsrc, num_priv); } =20 + if (mc->smp_props.clusters_supported && mc->smp_props.has_clusters= ) { if (cpus->cpus[n].props.cluster_id !=3D cluster_id) { + uint32_t priv_rsrc[2]; + int num_priv =3D 0; + + if (!share_structs && ms->smp.cache_cluster_start_level) { + build_caches_subset(table_data, pptt_start, num_caches, + caches, true, n, + top_cluster, + ms->smp.cache_cluster_start_level, + &cluster_data_offset, + &cluster_instr_offset); + top_core =3D ms->smp.cache_cluster_start_level - 1; + } + priv_rsrc[0] =3D cluster_instr_offset; + priv_rsrc[1] =3D cluster_data_offset; + assert(cpus->cpus[n].props.cluster_id > cluster_id); cluster_id =3D cpus->cpus[n].props.cluster_id; core_id =3D -1; cluster_offset =3D table_data->len - pptt_start; + + if (cluster_instr_offset || cluster_data_offset) { + num_priv =3D cluster_instr_offset =3D=3D cluster_data_= offset ? + 1 : 2; + } build_processor_hierarchy_node(table_data, (0 << 0), /* Not a physical package */ - socket_offset, cluster_id, NULL, 0); + socket_offset, cluster_id, priv_rsrc, num_priv); } } else { cluster_offset =3D socket_offset; } =20 + if (!share_structs && + cpus->cpus[n].props.core_id !=3D core_id) { + build_caches_subset(table_data, pptt_start, num_caches, caches, + true, n, + top_core , 0, + &l1_data_offset, &l1_instr_offset); + } if (ms->smp.threads =3D=3D 1) { + uint32_t priv_rsrc[2] =3D { l1_instr_offset, l1_data_offset }; + build_processor_hierarchy_node(table_data, (1 << 1) | /* ACPI Processor ID valid */ (1 << 3), /* Node is a Leaf */ - cluster_offset, n, NULL, 0); + cluster_offset, n, priv_rsrc, + l1_instr_offset =3D=3D l1_data_offset ? 1 : 2); } else { if (cpus->cpus[n].props.core_id !=3D core_id) { + uint32_t priv_rsrc[2] =3D { l1_instr_offset, l1_data_offse= t }; + assert(cpus->cpus[n].props.core_id > core_id); core_id =3D cpus->cpus[n].props.core_id; core_offset =3D table_data->len - pptt_start; build_processor_hierarchy_node(table_data, (0 << 0), /* Not a physical package */ - cluster_offset, core_id, NULL, 0); + cluster_offset, core_id, priv_rsrc, + l1_instr_offset =3D=3D l1_data_offset ? 1 : 2); } =20 build_processor_hierarchy_node(table_data, diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 6b674231c2..ec8fdcefff 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -922,6 +922,129 @@ static void acpi_align_size(GArray *blob, unsigned al= ign) g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); } =20 +static unsigned int virt_get_caches(VirtMachineState *vms, + ACPIPPTTCache *caches) +{ + ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(0)); + bool ccidx =3D cpu_isar_feature(any_ccidx, armcpu); + unsigned int num_cache, i; + int level_instr =3D 1, level_data =3D 1; + + for (i =3D 0, num_cache =3D 0; i < 7; i++, num_cache++) { + int type =3D (armcpu->clidr >> (3 * i)) & 7; + int bank_index; + int level =3D 0; + ACPIPPTTCacheType cache_type =3D INSTRUCTION; + + if (type =3D=3D 0) { + break; + } + + switch (type) { + case 1: + cache_type =3D INSTRUCTION; + level =3D level_instr; + break; + case 2: + cache_type =3D DATA; + level =3D level_data; + break; + case 4: + cache_type =3D UNIFIED; + level =3D level_instr > level_data ? level_instr : level_data; + break; + case 3: /* Split - Do data first */ + cache_type =3D DATA; + level =3D level_data; + break; + } + /* + * ccsidr is indexed using both the level and whether it is + * an instruction cache. Unified caches use the same storage + * as data caches. + */ + bank_index =3D (i * 2) | ((type =3D=3D 1) ? 1 : 0); + if (ccidx) { + caches[num_cache] =3D (ACPIPPTTCache) { + .type =3D cache_type, + .level =3D level, + .linesize =3D 1 << (FIELD_EX64(armcpu->ccsidr[bank_index], + CCSIDR_EL1, + CCIDX_LINESIZE) + 4), + .associativity =3D FIELD_EX64(armcpu->ccsidr[bank_index], + CCSIDR_EL1, + CCIDX_ASSOCIATIVITY) + 1, + .sets =3D FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL= 1, + CCIDX_NUMSETS) + 1, + }; + } else { + caches[num_cache] =3D (ACPIPPTTCache) { + .type =3D cache_type, + .level =3D level, + .linesize =3D 1 << (FIELD_EX64(armcpu->ccsidr[bank_index], + CCSIDR_EL1, LINESIZE) + 4), + .associativity =3D FIELD_EX64(armcpu->ccsidr[bank_index], + CCSIDR_EL1, + ASSOCIATIVITY) + 1, + .sets =3D FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL= 1, + NUMSETS) + 1, + }; + } + caches[num_cache].size =3D caches[num_cache].associativity * + caches[num_cache].sets * caches[num_cache].linesize; + + /* Break one 'split' entry up into two records */ + if (type =3D=3D 3) { + num_cache++; + bank_index =3D (i * 2) | 1; + if (ccidx) { + /* Instruction cache: bottom bit set when reading banked r= eg */ + caches[num_cache] =3D (ACPIPPTTCache) { + .type =3D INSTRUCTION, + .level =3D level_instr, + .linesize =3D 1 << (FIELD_EX64(armcpu->ccsidr[bank_ind= ex], + CCSIDR_EL1, + CCIDX_LINESIZE) + 4), + .associativity =3D FIELD_EX64(armcpu->ccsidr[bank_inde= x], + CCSIDR_EL1, + CCIDX_ASSOCIATIVITY) + 1, + .sets =3D FIELD_EX64(armcpu->ccsidr[bank_index], CCSID= R_EL1, + CCIDX_NUMSETS) + 1, + }; + } else { + caches[num_cache] =3D (ACPIPPTTCache) { + .type =3D INSTRUCTION, + .level =3D level_instr, + .linesize =3D 1 << (FIELD_EX64(armcpu->ccsidr[bank_ind= ex], + CCSIDR_EL1, LINESIZE) + 4= ), + .associativity =3D FIELD_EX64(armcpu->ccsidr[bank_inde= x], + CCSIDR_EL1, + ASSOCIATIVITY) + 1, + .sets =3D FIELD_EX64(armcpu->ccsidr[bank_index], CCSID= R_EL1, + NUMSETS) + 1, + }; + } + caches[num_cache].size =3D caches[num_cache].associativity * + caches[num_cache].sets * caches[num_cache].linesize; + } + switch (type) { + case 1: + level_instr++; + break; + case 2: + level_data++; + break; + case 3: + case 4: + level_instr++; + level_data++; + break; + } + } + + return num_cache; +} + static void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) { @@ -930,6 +1053,8 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildT= ables *tables) unsigned dsdt, xsdt; GArray *tables_blob =3D tables->table_data; MachineState *ms =3D MACHINE(vms); + ACPIPPTTCache caches[16]; /* Can select up to 16 */ + unsigned int num_cache; =20 table_offsets =3D g_array_new(false, true /* clear */, sizeof(uint32_t)); @@ -949,10 +1074,13 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuil= dTables *tables) acpi_add_table(table_offsets, tables_blob); build_madt(tables_blob, tables->linker, vms); =20 + num_cache =3D virt_get_caches(vms, caches); + if (!vmc->no_cpu_topology) { acpi_add_table(table_offsets, tables_blob); build_pptt(tables_blob, tables->linker, ms, - vms->oem_id, vms->oem_table_id); + vms->oem_id, vms->oem_table_id, + num_cache, caches); } =20 acpi_add_table(table_offsets, tables_blob); diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index 0f4d9b6f7a..cbb0bf1bc7 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -81,6 +81,10 @@ void machine_parse_smp_config(MachineState *ms, unsigned cores =3D config->has_cores ? config->cores : 0; unsigned threads =3D config->has_threads ? config->threads : 0; unsigned maxcpus =3D config->has_maxcpus ? config->maxcpus : 0; + unsigned cache_cl_start =3D config->has_cache_cluster_start_level ? + config->cache_cluster_start_level : 0; + unsigned cache_nd_start =3D config->has_cache_node_start_level ? + config->cache_node_start_level : 0; =20 /* * Specified CPU topology parameters must be greater than zero, @@ -161,6 +165,10 @@ void machine_parse_smp_config(MachineState *ms, ms->smp.max_cpus =3D maxcpus; =20 mc->smp_props.has_clusters =3D config->has_clusters; + if (mc->smp_props.has_clusters) { + ms->smp.cache_cluster_start_level =3D cache_cl_start; + ms->smp.cache_node_start_level =3D cache_nd_start; + } =20 /* sanity-check of the computed topology */ if (sockets * dies * clusters * cores * threads !=3D maxcpus) { diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c index 0b62c3a2f7..51d4ed9a19 100644 --- a/hw/loongarch/acpi-build.c +++ b/hw/loongarch/acpi-build.c @@ -439,7 +439,7 @@ static void acpi_build(AcpiBuildTables *tables, Machine= State *machine) =20 acpi_add_table(table_offsets, tables_blob); build_pptt(tables_blob, tables->linker, machine, - lams->oem_id, lams->oem_table_id); + lams->oem_id, lams->oem_table_id, 0, NULL); =20 acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, machine); --=20 2.39.2